CN113675262A - Field plate structure applied to semiconductor device and manufacturing method and application thereof - Google Patents
Field plate structure applied to semiconductor device and manufacturing method and application thereof Download PDFInfo
- Publication number
- CN113675262A CN113675262A CN202010406304.3A CN202010406304A CN113675262A CN 113675262 A CN113675262 A CN 113675262A CN 202010406304 A CN202010406304 A CN 202010406304A CN 113675262 A CN113675262 A CN 113675262A
- Authority
- CN
- China
- Prior art keywords
- field plate
- region
- layer
- oxide
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 42
- 210000000746 body region Anatomy 0.000 claims description 40
- 238000009792 diffusion process Methods 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 6
- 230000008878 coupling Effects 0.000 abstract description 9
- 238000010168 coupling process Methods 0.000 abstract description 9
- 238000005859 coupling reaction Methods 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 230000000694 effects Effects 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a field plate structure applied to a semiconductor device and a manufacturing method and application thereof. The field plate structure applied to the semiconductor device comprises a first field plate and a second field plate, wherein the first field plate is arranged in the oxide layer, the second field plate covers the oxide layer and completely covers a grid electrode, a local area of the second field plate is directly in electric contact with or electrically combined with the first field plate, and meanwhile the second field plate is grounded through a conductive through hole. In the field plate structure applied to the semiconductor device, the topmost field plate completely spans the grid, so that the coupling between the grid and the drain metal interconnection is isolated, the Cgd is effectively reduced, and the field plate can be grounded through more through holes, so that the ground resistance of the field plate structure is reduced, and the loss of the field plate under high frequency is reduced.
Description
Technical Field
The invention relates to a semiconductor device, in particular to a field plate structure applied to the semiconductor device and a manufacturing method and application thereof, and belongs to the technical field of semiconductors.
Background
A lateral power device needs to use a field plate to enhance and reduce surface electric field effect (RESURF) so as to achieve the best design compromise between breakdown voltage and on-resistance, taking a lateral double-diffused metal oxide semiconductor transistor (LDMOS) as an example, a field plate structure of an LDMOS device commonly used at present is shown in fig. 1, fig. 1 is a cross-sectional schematic view of an LDMOS device, in which 10 is a gate, 11 is a source, 12 is a drain, 13 is a body contact, 14 is a substrate, 5 is a drift region of the LDMOS device for bearing high voltage of the drain, 16 is a first field plate, 17 is a second field plate, 18 is silicon dioxide, fig. 2 is a top-down schematic view of the LDMOS device, in which 20 is the gate, 21 is the first field plate, 22 is the second field plate, 23 is a bridge of the first field plate, 24 is a bridge of the second field plate, and 25 is a through hole.
In the field plate structure of the existing device, two field plates respectively cross a grid through bridges made of the same material and are grounded through holes, the grounding field plate is positioned above a drift region, the RESURF effect is enhanced by adjusting the peak electric field intensity of the drift region, the breakdown voltage of the device is improved, and therefore the optimal compromise design of the breakdown voltage and the on-resistance is realized; the field plate can also reduce the coupling between the drain interconnect metal and the gate, thereby reducing the parasitic capacitance Cgd between the gate and the drain.
However, the existing field plate structure has the following two defects: firstly, a field plate is grounded through a bridge connecting through hole, the resistance of the field plate mainly depends on the resistance of a bridge, and the resistance is larger due to the limited number of the bridges; for power devices, especially for power devices for radio frequency applications, under high-frequency signals, a large alternating current flows through a field plate to generate loss, the loss is larger when the resistance is larger, the field plate cannot follow the response of the high-frequency signals, and further the effect of the field plate is reduced.
Secondly, the field plate does not completely cover the gate and does not effectively reduce the coupling between the gate and the drain, which in the rf power device reduces the isolation of the device and affects the gain and efficiency of the device.
Disclosure of Invention
The present invention is directed to a field plate structure for a semiconductor device, and a method for fabricating the field plate structure and an application thereof, so as to overcome the disadvantages of the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
the embodiment of the invention provides a field plate structure applied to a semiconductor device, wherein the semiconductor device comprises a semiconductor substrate and a grid, a body region and a drift region are distributed in the semiconductor substrate, an active region and a drain region are respectively formed in the body region and the drift region, the active region and the drain region are respectively matched with a source electrode and a drain electrode, a body region leading-out region is further arranged in the body region, an oxide layer covers the semiconductor substrate, and the grid is arranged in the oxide layer; the field plate structure comprises a first field plate and a second field plate, wherein the first field plate is arranged in the oxide layer, the second field plate covers the oxide layer and completely covers the grid, a local area of the second field plate is directly in electric contact with or electrically combined with the first field plate, and meanwhile the second field plate is grounded through a conductive through hole.
Further, at least a local region of the first field plate is masked.
Further, the field plate structure comprises a second field plate and a plurality of first field plates, the plurality of first field plates are arranged inside the oxide layer at intervals along the thickness direction of the oxide layer, and local regions of two adjacent first field plates are in electrical contact or electrical combination, wherein the local region of the second field plate is directly in electrical contact or electrical combination with the first field plate positioned at the topmost layer.
Further, the second field plate is connected with the grounding metal through a through hole.
Further, the source region is connected with the body region lead-out region, and the drain region is connected with the drift region.
The embodiment of the invention also provides a manufacturing method of the field plate structure applied to the semiconductor device, which comprises the following steps:
providing a semiconductor substrate, wherein a body region and a drift region are distributed in the semiconductor substrate, a source region and a drain region are respectively formed in the body region and the drift region, the source region and the drain region are respectively matched with a source electrode and a drain electrode, and a body region leading-out region is also arranged in the body region;
manufacturing a grid electrode, a first field plate and an oxide layer on the semiconductor substrate, wherein the grid electrode and the first field plate are positioned in the oxide layer, and part of the first field plate is exposed from a designated area of the oxide layer;
and forming a second field plate on the oxide layer, wherein the second field plate completely covers the grid electrode, and part of the second field plate is electrically contacted or combined with the first field plate from a designated area on the oxide layer.
Furthermore, the manufacturing method specifically comprises the following steps:
forming a layer of oxide on at least the semiconductor substrate in the regions corresponding to the grid electrode and the first field plate, respectively manufacturing the grid electrode and the first field plate on the oxide, and then forming a layer of oxide on the semiconductor substrate to enable the oxide to cover the grid electrode and the first field plate so as to form the oxide layer;
etching a designated area of the oxide layer until an opening exposing the first field plate is formed;
and forming a second field plate on the oxide layer and in the opening, wherein the second field plate at least covers part of the first field plate, and the second field plate is electrically contacted or combined with the first field plate from the opening.
Furthermore, the manufacturing method specifically comprises the following steps:
1) forming a first layer of oxide on at least the semiconductor substrate in the regions corresponding to the gate and the first field plate, and respectively forming the gate and the first field plate on the first layer of oxide,
2) forming a second layer of oxide on at least the first layer of first field plate, etching a designated area of the second layer of oxide until an opening exposing the first field plate is formed, then manufacturing a second layer of first field plate on the second layer of oxide, and enabling the second layer of first field plate to be in electrical contact or electrical combination with the first layer of first field plate from the opening;
3) repeating the step 2) to manufacture a plurality of first field plates which are arranged in a stacked mode and distributed at intervals, wherein oxide is arranged between any two adjacent first field plates, and the two adjacent first field plates are in electrical contact or electrical combination;
4) forming a layer of oxide on the first field plate at the topmost layer and the semiconductor substrate to further form the oxide layer, wherein the plurality of first field plates are positioned in the oxide layer, etching the appointed region of the oxide layer until an opening exposing the first field plate at the topmost layer is formed, and then manufacturing a second field plate on the oxide layer to enable the second field plate to completely cover the grid electrode and enable the second field plate to be in electric contact with or be electrically combined with the first field plate at the topmost layer from the opening.
Furthermore, the material of the oxide layer comprises silicon dioxide.
Furthermore, the body region and the drift region are formed by local processing of the semiconductor substrate by means of ion implantation and thermal diffusion.
Furthermore, the source region is formed by local processing of the body region by means of ion implantation and thermal diffusion, and the drain region is formed by local processing of the drift region by means of ion implantation and thermal diffusion.
The embodiment of the invention also provides a semiconductor device which comprises the field plate structure.
Compared with the prior art, the field plate structure applied to the semiconductor device provided by the embodiment of the invention has the advantages that the topmost field plate completely spans the gate, the coupling between the gate and the drain metal interconnection is isolated, the Cgd (gate-to-drain capacitance) is effectively reduced, and the gate is completely spanned, so that the field plate can be grounded through more through holes, the grounding resistance of the field plate is reduced, and the loss of the field plate under high frequency is reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of an LDMOS device of the prior art;
FIG. 2 is a top view of an LDMOS device of the prior art;
FIG. 3 is a schematic cross-sectional view of a semiconductor device having a multi-field plate structure in an exemplary embodiment of the invention;
FIG. 4 is a top view of a semiconductor device having a multi-field plate structure in an exemplary embodiment of the invention;
fig. 5 is a schematic diagram of a manufacturing process of a semiconductor device having a multi-field plate structure according to an exemplary embodiment of the present invention.
Detailed Description
In view of the deficiencies in the prior art, the inventors of the present invention have made extensive studies and extensive practices to provide technical solutions of the present invention. The technical solution, its implementation and principles, etc. will be further explained as follows.
In order to reduce the resistance of the field plate structure, enhance the effect of the field plate under high frequency, reduce the loss of the field plate and improve the shielding effect of the field plate on the coupling between the gate and the drain, the novel field plate structure provided by the invention not only enhances the shielding effect of the field plate on the coupling between the gate and the drain, but also greatly reduces the contact resistance of the field plate on the premise of not changing the RESURF effect of the field plate on the drift region.
The embodiment of the invention provides a field plate structure applied to a semiconductor device, wherein the semiconductor device comprises a semiconductor substrate and a grid, a body region and a drift region are distributed in the semiconductor substrate, an active region and a drain region are respectively formed in the body region and the drift region, the active region and the drain region are respectively matched with a source electrode and a drain electrode, a body region leading-out region is further arranged in the body region, an oxide layer covers the semiconductor substrate, and the grid is arranged in the oxide layer; the field plate structure comprises a first field plate and a second field plate, wherein the first field plate is arranged in the oxide layer, the second field plate covers the oxide layer and completely covers the grid, a local area of the second field plate is directly in electric contact with or electrically combined with the first field plate, and meanwhile the second field plate is grounded through a conductive through hole.
The embodiment of the invention also provides a manufacturing method of the field plate structure applied to the semiconductor device, which comprises the following steps:
providing a semiconductor substrate, wherein a body region and a drift region are distributed in the semiconductor substrate, a source region and a drain region are respectively formed in the body region and the drift region, the source region and the drain region are respectively matched with a source electrode and a drain electrode, and a body region leading-out region is also arranged in the body region;
forming a first oxide layer on the semiconductor substrate, forming a grid and a first field plate on the first oxide layer, and then forming a second oxide layer on the first oxide layer, the grid and the first field plate, wherein part of the first field plate is exposed from a designated area of the second oxide layer;
and forming a second field plate on the second oxide layer, wherein the second field plate completely covers the grid electrode, and part of the second field plate is electrically contacted or combined with the first field plate from a designated area on the second oxide layer.
Referring to fig. 3 and 4, a semiconductor device with a multi-field plate structure may be an LDMOS Transistor (lateral double diffusion metal oxide semiconductor Transistor), which includes a semiconductor substrate 14 and a gate 10, a body region and a drift region 15 are distributed in the semiconductor substrate 14, an active region 11 and a drain region 12 are respectively formed in the body region and the drift region 15, the active region 11 and the drain region 12 are respectively matched with a source and a drain, a body region lead-out region 13 is further disposed in the body region, an oxide layer 18 is further covered on the semiconductor substrate 14, and the gate 10 is disposed in the oxide layer 18; and the semiconductor further has a field plate structure comprising a first field plate 16 and a second field plate 17, wherein the first field plate 16 is disposed within the oxide layer 18, the second field plate 17 covers the oxide layer 18 and completely covers the gate 10, and a local region of the second field plate 17 is in electrical contact with or electrically bonded to the first field plate 16, and the second field plate 17 crosses the gate 10 from the surface of the oxide layer 18 and is grounded through a plurality of vias 25.
Specifically, the field plate structure may further include a plurality of first field plates, the plurality of first field plates are spaced apart from each other in the thickness direction of the oxide layer and are disposed in the oxide layer 18, and portions of two adjacent first field plates are in electrical contact or electrically connected to each other, wherein a portion of the second field plate 17 is in electrical contact with or electrically connected to the topmost first field plate 16, and at least a portion of the first field plate 16 is covered.
Specifically, the second field plate 17 serves as a ground field plate, which is connected to the ground metal 310 through a plurality of vias 25, thereby achieving grounding. The plurality of first field plates may be located on one side of the gate, and the structures of the plurality of first field plates may be the same or different, and may be specifically configured according to different situations.
According to the semiconductor device with the multi-field plate structure, the second field plate completely spans the grid and is grounded through the large-area through hole, so that the coupling of grid and drain interconnection metal is effectively shielded, and Cgd is reduced; on the other hand, the second field plate and the first field plate are interconnected by adopting large-area contact, so that the resistance of the field plates is effectively reduced, the loss of the field plates is reduced, and the high-frequency response of the device is improved.
Specifically, referring to fig. 5, a method for fabricating a semiconductor device having a multi-field plate structure includes:
1) providing a semiconductor substrate 14, and processing a body region and a drift region 15 in the semiconductor substrate 14 by adopting an ion implantation and heating diffusion manner, and processing a source region 11 and a body region extraction region 13 in the body region by adopting an ion implantation and heating diffusion manner, and processing a drain region 12 in the drift region by adopting an ion implantation and heating diffusion manner;
2) depositing a layer of silicon dioxide as a first layer of oxide on the whole area on the semiconductor substrate 14 or the area below the gate on the semiconductor substrate 14 and corresponding to the first field plate, and respectively manufacturing a gate 10 and a first field plate 16 on the first layer of oxide;
3) a layer of silicon dioxide is deposited as a second layer of oxide over the semiconductor substrate 14 and the first field plate 16 to form an oxide layer 18, the gate 10 and the first field plate 16 are disposed within the oxide layer 18,
4) etching the region of the oxide layer 18 corresponding to the first field plate 16 to remove the oxide layer 18 in that region until an opening or hole 19 is formed that exposes the first field plate 16;
5) forming a second field plate 17 on said oxide layer 18, said second field plate 17 continuously spanning the gate 10 and being in direct electrical contact or electrical engagement with the first field plate 16 from said opening or hole 19;
6) the second field plate 17 is connected to the grounding metal 310 through a plurality of through holes, the through holes are conductive through holes, the conductive through holes include holes arranged in the semiconductor device and conductive materials filled in the holes, the material of the conductive materials is the same as that of the first field plate or the second field plate, and the specific processing process can be realized by adopting the technology known by those skilled in the art, and the detailed description is omitted here.
In the semiconductor device with the multi-field plate structure provided by the embodiment of the invention, each field plate in the field plate structure does not need to be connected with a connecting bridge, a part of oxide layer above the first field plate is cut before the second field plate is manufactured on one side of the drift region, and the second field plate and the first field plate are connected together when the second field plate is deposited; on one side of the drift region, the effective structure of the field plate is not changed, the field plate structure does not need to be redesigned, meanwhile, the large-area interconnection of the two field plates is realized, the large-area interconnection of the second field plate and the through hole is realized, and the resistance of the field plate is reduced.
Specifically, for a field plate structure of a multilayer field plate, the method for manufacturing the semiconductor device with the multilayer field plate structure may include:
1) providing a semiconductor substrate 14, and processing a body region and a drift region 15 in the semiconductor substrate 14 by adopting an ion implantation and heating diffusion manner, and processing a source region 11 and a body region extraction region 13 in the body region by adopting an ion implantation and heating diffusion manner, and processing a drain region 12 in the drift region by adopting an ion implantation and heating diffusion manner;
2) depositing a layer of silicon dioxide as a first layer of oxide on the whole area on the semiconductor substrate 14 or the area below the gate on the semiconductor substrate 14 and corresponding to the first field plate, and respectively manufacturing a gate 10 and a first layer of first field plate 16 on the first layer of oxide;
3) depositing a layer of silicon dioxide on at least the first layer of the first field plate 16 as a second layer of oxide, etching a designated region of the second layer of oxide until an opening exposing the first layer of the first field plate is formed, then manufacturing the second layer of the first field plate on the second layer of oxide, and enabling the second layer of the first field plate to be in electrical contact with or be electrically combined with the first layer of the first field plate from the opening;
4) repeating the step 2) to form a plurality of layers of first field plates and a plurality of layers of oxides at intervals, wherein the first field plate positioned on the upper layer and the first field plate positioned on the lower layer are electrically contacted or combined, and a layer of oxide is formed between any two adjacent layers of first field plates;
5) depositing silicon dioxide on the nth layer of the first field plate on the topmost layer and the semiconductor substrate to form an oxide layer, etching a designated region of the oxide layer until an opening exposing the first field plate on the topmost layer is formed, and then manufacturing a second field plate on the oxide layer, wherein the second field plate 17 continuously crosses over the grid and is electrically contacted or combined with the first field plate on the topmost layer from the opening;
6) the second field plate is connected to the ground metal 310 through a plurality of vias.
The semiconductor device with the multi-field plate structure, in particular to a transverse power semiconductor device, provided by the embodiment of the invention, has a multi-layer field plate structure, wherein field plates positioned at the lower layer are interconnected through direct contact and field plates positioned at the upper layer, and the like, and the field plate positioned at the topmost layer spans a grid and is grounded through a through hole.
The field plate structure applied to the semiconductor device provided by the embodiment of the invention can enhance the shielding effect on the coupling between the gate and the drain and reduce Cgd on the one hand; on the other hand, the resistance of the field plate can be reduced, the loss under high-frequency application is reduced, and the high-frequency response of the device is improved.
According to the field plate structure applied to the semiconductor device, the topmost field plate completely spans the grid, coupling between the grid and the drain metal interconnection is isolated, Cgd is effectively reduced, and the gate is completely spanned, so that more through holes can be used for grounding, grounding resistance of the field plate is reduced, and loss of the field plate under high frequency is reduced.
It should be understood that the above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and therefore, the protection scope of the present invention is not limited thereby. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (10)
1. A field plate structure applied to a semiconductor device comprises a semiconductor substrate and a grid, wherein a body region and a drift region are distributed in the semiconductor substrate, an active region and a drain region are respectively formed in the body region and the drift region, the active region and the drain region are respectively matched with a source electrode and a drain electrode, a body region leading-out region is further arranged in the body region, an oxide layer covers the semiconductor substrate, and the grid is arranged in the oxide layer; the method is characterized in that: the field plate structure comprises a first field plate and a second field plate, wherein the first field plate is arranged in the oxide layer, the second field plate covers the oxide layer and completely covers the grid, a local area of the second field plate is directly in electric contact with or electrically combined with the first field plate, and meanwhile the second field plate is grounded through a conductive through hole.
2. The field plate structure applied to the semiconductor device according to claim 1, wherein: at least a local region of the first field plate is masked.
3. The field plate structure applied to the semiconductor device according to claim 1, wherein; the field plate structure comprises a second field plate and a plurality of first field plates, wherein the plurality of first field plates are arranged inside the oxide layer at intervals along the thickness direction of the oxide layer, and local regions of two adjacent first field plates are in electric contact or electric combination, wherein the local region of the second field plate is directly in electric contact or electric combination with the first field plate positioned at the topmost layer.
4. The field plate structure applied to the semiconductor device according to claim 1 or 3, wherein: the second field plate is connected with the grounding metal through a through hole.
5. The field plate structure applied to the semiconductor device according to claim 1, wherein: the source region is connected with the body region leading-out region, and the drain region is connected with the drift region.
6. The method for manufacturing a field plate structure applied to a semiconductor device according to any one of claims 1 to 5, comprising:
providing a semiconductor substrate, wherein a body region and a drift region are distributed in the semiconductor substrate, a source region and a drain region are respectively formed in the body region and the drift region, the source region and the drain region are respectively matched with a source electrode and a drain electrode, and a body region leading-out region is also arranged in the body region;
manufacturing a grid electrode, a first field plate and an oxide layer on the semiconductor substrate, wherein the grid electrode and the first field plate are positioned in the oxide layer, and part of the first field plate is exposed from a designated area of the oxide layer;
and forming a second field plate on the oxide layer, wherein the second field plate completely covers the grid electrode, and part of the second field plate is electrically contacted or combined with the first field plate from a designated area on the oxide layer.
7. The manufacturing method according to claim 6, characterized by specifically comprising:
forming a layer of oxide on at least the semiconductor substrate in the regions corresponding to the grid electrode and the first field plate, respectively manufacturing the grid electrode and the first field plate on the oxide, and then forming a layer of oxide on the semiconductor substrate to enable the oxide to cover the grid electrode and the first field plate so as to form the oxide layer;
etching a designated area of the oxide layer until an opening exposing the first field plate is formed;
and forming a second field plate on the oxide layer and in the opening, wherein the second field plate at least covers part of the first field plate, and the second field plate is electrically contacted or combined with the first field plate from the opening.
8. The manufacturing method according to claim 6, characterized by specifically comprising:
1) forming a first layer of oxide on at least the semiconductor substrate in the regions corresponding to the gate and the first field plate, and respectively forming the gate and the first field plate on the first layer of oxide,
2) forming a second layer of oxide on at least the first layer of first field plate, etching a designated area of the second layer of oxide until an opening exposing the first field plate is formed, then manufacturing a second layer of first field plate on the second layer of oxide, and enabling the second layer of first field plate to be in electrical contact or electrical combination with the first layer of first field plate from the opening;
3) repeating the step 2) to manufacture a plurality of first field plates which are arranged in a stacked mode and distributed at intervals, wherein oxide is arranged between any two adjacent first field plates, and the two adjacent first field plates are in electrical contact or electrical combination;
4) forming a layer of oxide on the first field plate at the topmost layer and the semiconductor substrate to further form the oxide layer, wherein the plurality of first field plates are positioned in the oxide layer, etching the appointed region of the oxide layer until an opening exposing the first field plate at the topmost layer is formed, and then manufacturing a second field plate on the oxide layer to enable the second field plate to completely cover the grid electrode and enable the second field plate to be in electric contact with or be electrically combined with the first field plate at the topmost layer from the opening.
9. The method of manufacturing according to claim 7, wherein: the body region and the drift region are formed by local processing of the semiconductor substrate in a mode of ion implantation and heating diffusion; and/or the source region is formed by locally processing the body region by means of ion implantation and thermal diffusion, and the drain region is formed by locally processing the drift region by means of ion implantation and thermal diffusion.
10. A semiconductor device characterized by comprising a field plate structure according to any of claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010406304.3A CN113675262B (en) | 2020-05-14 | 2020-05-14 | Field plate structure applied to semiconductor device and manufacturing method and application thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010406304.3A CN113675262B (en) | 2020-05-14 | 2020-05-14 | Field plate structure applied to semiconductor device and manufacturing method and application thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113675262A true CN113675262A (en) | 2021-11-19 |
| CN113675262B CN113675262B (en) | 2023-12-05 |
Family
ID=78537174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010406304.3A Active CN113675262B (en) | 2020-05-14 | 2020-05-14 | Field plate structure applied to semiconductor device and manufacturing method and application thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113675262B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1950945A (en) * | 2004-05-11 | 2007-04-18 | 美商克立股份有限公司 | Wide bandgap transistors with multiple field plates |
| CN101707208A (en) * | 2009-11-03 | 2010-05-12 | 苏州远创达科技有限公司 | Multi-field plate LDMOS device and processing method thereof |
| CN102237410A (en) * | 2010-04-29 | 2011-11-09 | Nxp股份有限公司 | Semiconductor transistor comprising two electrically conductive shield elements |
| CN102790086A (en) * | 2012-07-10 | 2012-11-21 | 苏州远创达科技有限公司 | LDMOS device with stepped multiple discontinuous filed plate and manufacturing method for LDMOS device |
| CN103872123A (en) * | 2012-12-12 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | N-channel radio frequency LDMOS (Lateral Double-diffused Metal Oxide Semiconductor field effect transistor) device and manufacturing method |
| JP2015170821A (en) * | 2014-03-10 | 2015-09-28 | 古河電気工業株式会社 | Nitride semiconductor device, field effect transistor and cascode connection circuit |
| CN105720096A (en) * | 2013-12-27 | 2016-06-29 | 电力集成公司 | High-electron-mobility transistors |
| US20190334032A1 (en) * | 2014-11-25 | 2019-10-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact field plate |
-
2020
- 2020-05-14 CN CN202010406304.3A patent/CN113675262B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1950945A (en) * | 2004-05-11 | 2007-04-18 | 美商克立股份有限公司 | Wide bandgap transistors with multiple field plates |
| CN101707208A (en) * | 2009-11-03 | 2010-05-12 | 苏州远创达科技有限公司 | Multi-field plate LDMOS device and processing method thereof |
| CN102237410A (en) * | 2010-04-29 | 2011-11-09 | Nxp股份有限公司 | Semiconductor transistor comprising two electrically conductive shield elements |
| CN102790086A (en) * | 2012-07-10 | 2012-11-21 | 苏州远创达科技有限公司 | LDMOS device with stepped multiple discontinuous filed plate and manufacturing method for LDMOS device |
| CN103872123A (en) * | 2012-12-12 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | N-channel radio frequency LDMOS (Lateral Double-diffused Metal Oxide Semiconductor field effect transistor) device and manufacturing method |
| CN105720096A (en) * | 2013-12-27 | 2016-06-29 | 电力集成公司 | High-electron-mobility transistors |
| JP2015170821A (en) * | 2014-03-10 | 2015-09-28 | 古河電気工業株式会社 | Nitride semiconductor device, field effect transistor and cascode connection circuit |
| US20190334032A1 (en) * | 2014-11-25 | 2019-10-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact field plate |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113675262B (en) | 2023-12-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100856299B1 (en) | Insulated gate type semiconductor device | |
| KR101213068B1 (en) | Semiconductor device and method for fabricating the same | |
| TWI402960B (en) | Ground shields for semiconductors | |
| US7888712B2 (en) | Semiconductor device and method for manufacturing same | |
| US8445958B2 (en) | Power semiconductor device with trench bottom polysilicon and fabrication method thereof | |
| US11588040B2 (en) | LDMOS device and method for forming the same | |
| JP4491875B2 (en) | Trench type MOS semiconductor device | |
| US20120202342A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN102280482B (en) | Radio frequency lateral diffusion metal oxide semiconductor device and preparation method thereof | |
| CN109698239B (en) | NLDMOS device and manufacturing method thereof | |
| CN115274848B (en) | Super-junction LDMOS device of patterned layout interlayer oxide layer SOI | |
| CN117174756B (en) | SiC MOSFET cell structure with double multilayer shielding structure, device and preparation method | |
| EP2421044B1 (en) | Edge Termination Region for Semiconductor Device | |
| US5888889A (en) | Integrated structure pad assembly for lead bonding | |
| CN109888016B (en) | NLDMOS device and manufacturing method thereof | |
| CN113675262B (en) | Field plate structure applied to semiconductor device and manufacturing method and application thereof | |
| CN111986991A (en) | Groove etching method, silicon carbide device preparation method and silicon carbide device | |
| CN114464663B (en) | Multi-layer well region LDMOS device applied to radio frequency amplification and manufacturing method thereof | |
| CN114429908A (en) | RFLDMOS device and manufacturing method thereof | |
| CN105702678A (en) | An integrated structure of an LDMOS and a JFET and a manufacturing method thereof | |
| US9508846B2 (en) | Vertical MOS semiconductor device for high-frequency applications, and related manufacturing process | |
| CN116504829A (en) | LDMOS device structure of multilayer field plate and manufacturing method thereof | |
| CN110444594B (en) | Grid-controlled power device with low parasitic resistance and manufacturing method thereof | |
| US11227928B1 (en) | Termination structures for trench-gate field-effect transistors | |
| CN116581149B (en) | Double-groove SiC MOSFET cell structure with interlayer, device and preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 215000 10-1f, creative industry park, 328 Xinghu street, Suzhou Industrial Park, Jiangsu Province Applicant after: Suzhou Huatai Electronic Technology Co.,Ltd. Address before: Room B0604, 388 Ruoshui Road, Suzhou Industrial Park, Wuzhong District, Suzhou City, Jiangsu Province Applicant before: SUZHOU HUATAI ELECTRONIC TECHNOLOGY Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |