CN106057905A - Trench gate field effect transistor and manufacturing method - Google Patents
Trench gate field effect transistor and manufacturing method Download PDFInfo
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- CN106057905A CN106057905A CN201610675000.0A CN201610675000A CN106057905A CN 106057905 A CN106057905 A CN 106057905A CN 201610675000 A CN201610675000 A CN 201610675000A CN 106057905 A CN106057905 A CN 106057905A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000002353 field-effect transistor method Methods 0.000 title 1
- 230000005669 field effect Effects 0.000 claims abstract description 51
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 230000015556 catabolic process Effects 0.000 claims abstract description 13
- 230000005684 electric field Effects 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 129
- 239000012535 impurity Substances 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 abstract 2
- 238000005468 ion implantation Methods 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a trench gate field effect transistor, and the field effect transistor comprises a drift region and a body region. A trench passes through the body region to enter the drift region. A gate medium layer and a polysilicon gate are formed in the trench. A reverse doped layer is formed at a part, at the bottom of the trench, of the drift region, and is formed by the overlapping of a second conductive type foreign matter and a first conductive type foreign matter. The second conductive type foreign matter is formed through vertical ion implantation after the forming of the trench and before the forming of the gate medium layer and the polysilicon gate, and the reverse doped layer is enabled to be located at the bottom of the trench in a self-aligned manner. The reverse doped layer is used for reducing the electric field intensity of the part, located at the bottom of the trench, of the drift region, and can increase the breakdown voltage of a device under the conditions that the doping density of the drift region is not reduced and the thickness of the drift region is not increased. The invention also discloses a manufacturing method for the trench gate field effect transistor. The trench gate field effect transistor can increase the breakdown voltage of the device, and does not sacrifice other performances of the device.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of trench-gate field effect transistors.This
Invention further relates to the manufacture method of a kind of trench-gate field effect transistors.
Background technology
Compared with plane type field effect transistor, trench gate field-effect transistor has that device density is big, drive electric current
High advantage.As it is shown in figure 1, be the structural representation of existing trench-gate field effect transistors；As a example by N-type device, existing ditch
Groove grid field effect transistor includes:
The district 102, drift region 101 and PXing Ti of N-type, described body district 102 is positioned at the surface of described drift region 101；Described
Drift region 101 is formed at semiconductor substrate surface.
Groove, described groove is through described body district 102 and enters in described drift region 101.
Interior surface at groove is formed with gate dielectric layer 103, is filled with polysilicon gate 104 in the trench；By institute
State the surface, described body district 102 of polysilicon gate 104 side covering for forming raceway groove.
It is formed with the source region 105 being made up of N-type heavily doped region on surface, described body district 102.
Being formed with the heavily doped drain region of N-type 106 at the back side, described drift region 101, drain region 106 can be by serving as a contrast quasiconductor
Carry out the back side after bottom back side is thinning and inject formation.
The source electrode graphically formed by front metal layer and grid, described grid passes through contact hole and described polysilicon gate
104 connect, and described source region 105 and described body district 102 are connected to described source electrode by the described contact hole at top.
Metal layer on back, described metal layer on back and described drain region 106 contact and as drain electrode.
In existing structure, the drift region 101 of channel bottom is the region that in whole drift region 101, electric lines of force is concentrated most, also
It it is the place being easiest to puncture.
Due to the breakdown voltage that channel bottom drift region 101 is relatively low, device has to use lower drift region 101 to adulterate
Concentration and thicker drift region 101, to reach the breakdown voltage target of device.But so can sacrifice the property such as device on-resistance
Energy.
Summary of the invention
The technical problem to be solved is to provide a kind of trench-gate field effect transistors, can improve puncturing of device
Voltage does not sacrifice other performance of device simultaneously.To this end, the present invention also provides for the manufacturer of a kind of trench-gate field effect transistors
Method.
For solving above-mentioned technical problem, the present invention provides a kind of trench-gate field effect transistors to include:
The drift region of the first conduction type and the body district of the second conduction type, described body district is positioned at the table of described drift region
Face；Described drift region is formed at semiconductor substrate surface.
Groove, described groove is through described body district and enters in described drift region.
Interior surface at groove is formed with gate dielectric layer, is filled with polysilicon gate in the trench；By described polycrystalline
The described body surface that Si-gate side covers is used for forming raceway groove.
Being formed with contra-doping layer in the described drift region of the bottom of described groove, described contra-doping layer is by the second conductive-type
First conductive type impurity superposition of type impurity and described drift region is formed, and described second conductive type impurity is in described ditch flute profile
Formed by vertical ion implanting before after one-tenth and forming described gate dielectric layer and described polysilicon gate in the trench
And making described contra-doping layer autoregistration be positioned at the bottom of described groove, described contra-doping layer is for reducing the drift of described channel bottom
Move the electric field intensity in district, can carry under conditions of the thickness of the doping content and the described drift region of increase that do not reduce described drift region
The breakdown voltage of high device.
Further improving and be, the concentration of described second conductive type impurity is less than or equal to the first conduction of described drift region
The concentration of type dopant, the net doping type of described contra-doping layer is the first conduction of the first conduction type and described contra-doping layer
Type doping content is less than the first conduction type doping content of described drift region.
Or, the concentration of described second conductive type impurity is dense more than the first conductive type impurity of described drift region
Degree, the net doping type of described contra-doping layer is the second conduction type, between described contra-doping layer and adjacent described drift region
Form PN junction.
Further improve and be, described contra-doping layer and the bottom surface contact of described groove and upwardly extend and described instead
The contacts side surfaces upwardly extending part and described groove of doped layer.
Or, described contra-doping layer is positioned at the bottom of the lower surface of described groove and does not contacts.
Further improving is to be formed with the source region being made up of the first conduction type heavily doped region at described body surface；
The first heavily doped drain region of conduction type it is formed with at the back side, described drift region.
Further improving is also to include:
The source electrode graphically formed by front metal layer and grid, described grid is connected by contact hole and described polysilicon gate
Connecing, described source region and described body district are connected to described source electrode by the described contact hole at top.
Metal layer on back, described metal layer on back and described drain contact conduct drain electrode.
Further improving is that described Semiconductor substrate is silicon substrate.
Further improving is that described gate dielectric layer is oxide layer.
Further improving is that described trench-gate field effect transistors is N-type device, and the first conduction type is N-type, second
Conduction type is p-type；Or, described trench-gate field effect transistors is P-type device, and the first conduction type is p-type, the second conduction
Type is N-type.
For solving above-mentioned technical problem, the manufacture method of the trench-gate field effect transistors that the present invention provides includes walking as follows
Rapid:
Step one, form the drift region of the first conduction type at semiconductor substrate surface.
Step 2, be formed described drift region described semiconductor substrate surface formed hard mask layers.
Step 3, the formation region of lithographic definition groove, go the described hard mask layers forming region of described groove
Removing, the described hard mask layers formed outside region of described groove retains.
Step 4, for mask, described Semiconductor substrate performed etching the described groove of formation, institute with described hard mask layers
State groove to be positioned in described drift region and the degree of depth of described groove is more than the degree of depth in body district being subsequently formed.
Step 5, with described hard mask layers for mask carry out the second conduction type vertical ion inject, this vertically from
Son is infused in autoregistration in the described drift region of the bottom of described groove and injects the second conductive type impurity, is conducted electricity by described second
First conductive type impurity superposition of type dopant and described drift region forms contra-doping layer, and described contra-doping layer is used for reducing institute
State the electric field intensity of the drift region of channel bottom, not reducing the doping content of described drift region and described drift region can be increased
The breakdown voltage of device is improved under conditions of thickness.
Step 6, remove described hard mask layers.
Step 7, described groove interior surface formed gate dielectric layer, be filled with polysilicon gate in the trench；
Step 8, form the body district of the second conduction type on surface, described drift region；Covered by described polysilicon gate side
Described body surface be used for forming raceway groove.
Further improving and be, the concentration of described second conductive type impurity is less than or equal to the first conduction of described drift region
The concentration of type dopant, the net doping type of described contra-doping layer is the first conduction of the first conduction type and described contra-doping layer
Type doping content is less than the first conduction type doping content of described drift region.
Or, the concentration of described second conductive type impurity is dense more than the first conductive type impurity of described drift region
Degree, the net doping type of described contra-doping layer is the second conduction type, between described contra-doping layer and adjacent described drift region
Form PN junction.
Further improve and be, described contra-doping layer and the bottom surface contact of described groove and upwardly extend and described instead
The contacts side surfaces upwardly extending part and described groove of doped layer.
Or, described contra-doping layer is positioned at the bottom of the lower surface of described groove and does not contacts.
Further improving is to further comprise the steps of:
Step 9, the source region being made up of the first conduction type heavily doped region in the formation of described body surface.
Step 10, described Semiconductor substrate is carried out thinning back side and carries out backside particulate and be infused in the back side, described drift region
Form the first heavily doped drain region of conduction type.
Further improving is also to include:
Following front technique is also included after step 9, before step 10:
Form interlayer film in described Semiconductor substrate front, form the contact hole through described interlayer film, form front gold
Belonging to layer shapeization and form source electrode and grid, described grid is connected by contact hole and described polysilicon gate, described source region and described
Body district is connected to described source electrode by the described contact hole at top.
Following back process is also included after step 10:
Form metal layer on back, described metal layer on back and described drain contact and as drain electrode.
Further improve and be, step 7 uses thermal oxidation technology form described grid Jie in the interior surface of described groove
Matter layer.
Further improving is that described hard mask layers is formed by silicon oxide and silicon nitride superposition.
The present invention is by forming contra-doping layer in the drift region of channel bottom, and the second conduction type in contra-doping layer is miscellaneous
Mass-energy makes the first clean impurity of conduction type of contra-doping layer reduce or be directly changed into the structure of the second clean impurity of conduction type,
This can reduce the electric field intensity of drift region of channel bottom, thus improves the breakdown voltage of device.
It addition, the second conductive type impurity of the contra-doping layer of the present invention is to form rear gate dielectric layer and polycrystalline by groove
Si-gate is formed by vertical ion implanting before being formed, and contra-doping layer and groove have autoregistration relation, so make counter mixing
Diamicton can be accurately located at the bottom of groove, produces impact from the doping without the drift region on other region, so this
The bright breakdown voltage that can improve device under conditions of the process conditions such as doping content not changing drift region and thickness；And by
Improve the breakdown voltage of device in the present invention and need not change the process conditions of drift region, so other performance such as electric conduction of device
Resistance can be maintained.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is the structural representation of existing trench-gate field effect transistors；
Fig. 2 is the structural representation of the embodiment of the present invention one trench-gate field effect transistors；
Fig. 3 is the structural representation of the embodiment of the present invention two trench-gate field effect transistors；
Fig. 4 is that the device architecture in the manufacture method of the embodiment of the present invention one trench-gate field effect transistors is intended to.
Detailed description of the invention
As in figure 2 it is shown, be the structural representation of the embodiment of the present invention one trench-gate field effect transistors；The embodiment of the present invention
One trench-gate field effect transistors includes:
The drift region 1 of the first conduction type and the body district 2 of the second conduction type, described body district 2 is positioned at described drift region 1
Surface；Described drift region 1 is formed at semiconductor substrate surface.Preferably, described Semiconductor substrate is silicon substrate.
Groove, described groove is through described body district 2 and enters in described drift region 1.
Interior surface at groove is formed with gate dielectric layer 3, is filled with polysilicon gate 4 in the trench；By described many
The surface, described body district 2 that crystal silicon grid 4 side covers is used for forming raceway groove.Preferably, described gate dielectric layer 3 is oxide layer.
Being formed with contra-doping layer 7a in the described drift region 1 of the bottom of described groove, described contra-doping layer 7a is by second
First conductive type impurity superposition of conductive type impurity and described drift region 1 is formed, and described second conductive type impurity is in institute
Before stating after groove is formed and formed in the trench described gate dielectric layer 3 and described polysilicon gate 4 by vertical from
Son injects and is formed and make described contra-doping layer 7a autoregistration be positioned at the bottom of described groove, and described contra-doping layer 7a is used for reducing institute
State the electric field intensity of the drift region 1 of channel bottom, not reducing the doping content of described drift region 1 and described drift region can be increased
The breakdown voltage of device is improved under conditions of the thickness of 1.
In the embodiment of the present invention one, the concentration of described second conductive type impurity is more than the first conduction of described drift region 1
The concentration of type dopant, the net doping type of described contra-doping layer 7a is the second conduction type, and described contra-doping layer 7a is with adjacent
Described drift region 1 between formed PN junction.In other embodiments, also can be: the concentration of described second conductive type impurity is little
In the concentration of the first conductive type impurity equal to described drift region 1, the net doping type of described contra-doping layer 7a is first to lead
The first conduction type doping content of electricity type and described contra-doping layer 7a is less than the first conduction type doping of described drift region 1
Concentration.
Described contra-doping layer 7a and the bottom surface contact of described groove and upwardly extend and described contra-doping layer 7a to
Upper extension and the contacts side surfaces of described groove.Understand as shown in Figure 2, between described contra-doping layer 7a and described drift region 1
The bottom of described groove is also surrounded by the PN junction structure ringwise that formed.
It is formed with the source region 5 being made up of the first conduction type heavily doped region on surface, described body district 2；In described drift region 1
The back side is formed with the first heavily doped drain region of conduction type 6.
Also include:
The source electrode graphically formed by front metal layer and grid, described grid passes through contact hole and described polysilicon gate 4
Connecting, described source region 5 and described body district 2 are connected to described source electrode by the described contact hole at top.
Metal layer on back, described metal layer on back and described drain region 6 contact and as drain electrode.
In the embodiment of the present invention one, described trench-gate field effect transistors is N-type device, and the first conduction type is N-type, the
Two conduction types are p-type；Second conductive type impurity of described contra-doping layer 7a can be boron, indium etc..In other embodiments, also
Can be: described trench-gate field effect transistors is P-type device, the first conduction type be p-type, and the second conduction type is N-type, described
Second conductive type impurity of contra-doping layer 7a can be arsenic, phosphorus, antimony etc..
As it is shown on figure 3, be the structural representation of the embodiment of the present invention two trench-gate field effect transistors；The embodiment of the present invention
It is that the present invention implements in place of the difference of two trench-gate field effect transistors and the embodiment of the present invention one trench-gate field effect transistors
Described contra-doping layer 7b in example two is positioned at the bottom of the lower surface of described groove and does not contacts.
As shown in Figure 4, be the embodiment of the present invention one groove 203 grid field effect transistor manufacture method in device architecture
Being intended to, the manufacture method of the embodiment of the present invention one groove 203 grid field effect transistor comprises the steps:
Step one, form the drift region 1 of the first conduction type at semiconductor substrate surface.
Step 2, be formed described drift region 1 described semiconductor substrate surface formed hard mask layers.Preferably,
Described hard mask layers is formed by silicon oxide 201 and silicon nitride 202 superposition.
Step 3, the formation region of lithographic definition groove 203, cover the described hard forming region of described groove 203
Mold layer is removed, and the described hard mask layers formed outside region of described groove 203 retains.
Step 4, for mask, described Semiconductor substrate performed etching the described groove 203 of formation with described hard mask layers,
Described groove 203 is positioned in described drift region 1 and the degree of depth of described groove 203 is more than the degree of depth in body district 2 being subsequently formed.
Step 5, with described hard mask layers for mask carry out the second conduction type vertical ion inject, this vertically from
In the described drift region 1 of the bottom that son is infused in described groove 203, the second conductive type impurity 204 is injected in autoregistration.To described
Second conductive type impurity 204 formed after annealing as shown in Figure 2 by described second conductive type impurity 204 and described drift
The first conductive type impurity superposition formation the contra-doping floor 7a, described contra-doping layer 7a moving district 1 is used for reducing described groove 203 end
The electric field intensity of the drift region 1 in portion, not reducing the doping content of described drift region 1 and can increase the thickness of described drift region 1
Under conditions of improve the breakdown voltage of device.
In the embodiment of the present invention one method, the concentration of described second conductive type impurity 204 is more than the of described drift region 1
The concentration of one conductive type impurity, the net doping type of described contra-doping layer 7a is the second conduction type, described contra-doping layer 7a
And between adjacent described drift region 1, form PN junction.Other embodiments method also can be: described second conductive type impurity
The concentration of 204 is less than or equal to the concentration of the first conductive type impurity of described drift region 1, the net doping class of described contra-doping layer 7a
Type is that the first conduction type doping content of the first conduction type and described contra-doping layer 7a is led less than the first of described drift region 1
Electricity type doping content.
As in figure 2 it is shown, described contra-doping layer 7a and the bottom surface contact of described groove 203 and upwardly extend and described instead
The contacts side surfaces upwardly extending part and described groove 203 of doped layer 7a.Other embodiments method also can be: such as Fig. 3
Shown in, described contra-doping layer 7b is positioned at bottom the lower surface of described groove 203 and does not contacts.
Step 6, remove described hard mask layers.
Step 7 as in figure 2 it is shown, described groove 203 interior surface formed gate dielectric layer 3, in described groove 203
It is filled with polysilicon gate 4.Preferably, thermal oxidation technology is used to form described gate dielectric layer in the interior surface of described groove 203
3。
Step 8 as in figure 2 it is shown, form the body district 2 of the second conduction type on surface, described drift region 1；By described polycrystalline
The surface, described body district 2 that Si-gate 4 side covers is used for forming raceway groove.
As in figure 2 it is shown, further comprise the steps of:
Step 9, the source region 5 being made up of the first conduction type heavily doped region in the formation of surface, described body district 2.
Form interlayer film in described Semiconductor substrate front, form the contact hole through described interlayer film, form front gold
Belonging to layer and shapeization forms source electrode and grid, described grid is connected by contact hole and described polysilicon gate 4, described source region 5 and institute
Shu Ti district 2 is connected to described source electrode by the described contact hole at top.
Step 10, described Semiconductor substrate is carried out thinning back side and carries out backside particulate and be infused in described drift region 1 and carry on the back
Face forms the first heavily doped drain region of conduction type 6.
Forming metal layer on back, described metal layer on back contacts with described drain region 6 and as drain electrode.
Above by specific embodiment, the present invention is described in detail, but these have not constituted the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improves, and these also should
It is considered as protection scope of the present invention.
Claims (17)
1. a trench-gate field effect transistors, it is characterised in that including:
The drift region of the first conduction type and the body district of the second conduction type, described body district is positioned at the surface of described drift region；Institute
State drift region and be formed at semiconductor substrate surface；
Groove, described groove is through described body district and enters in described drift region；
Interior surface at groove is formed with gate dielectric layer, is filled with polysilicon gate in the trench；By described polysilicon gate
The described body surface that side covers is used for forming raceway groove；
Being formed with contra-doping layer in the described drift region of the bottom of described groove, described contra-doping layer is miscellaneous by the second conduction type
First conductive type impurity superposition of matter and described drift region is formed, and described second conductive type impurity is after described groove is formed
And formed by vertical ion implanting before forming described gate dielectric layer and described polysilicon gate in the trench and make
Described contra-doping layer autoregistration is positioned at the bottom of described groove, and described contra-doping layer is for reducing the drift region of described channel bottom
Electric field intensity, can not reduce described drift region doping content and increase described drift region thickness under conditions of improve device
The breakdown voltage of part.
2. trench-gate field effect transistors as claimed in claim 1, it is characterised in that:
The concentration of described second conductive type impurity is less than or equal to the concentration of the first conductive type impurity of described drift region, described
The net doping type of contra-doping layer is that the first conduction type doping content of the first conduction type and described contra-doping layer is less than institute
State the first conduction type doping content of drift region；
Or, the concentration of described second conductive type impurity is more than the concentration of the first conductive type impurity of described drift region, institute
The net doping type stating contra-doping layer is the second conduction type, forms PN between described contra-doping layer and adjacent described drift region
Knot.
3. trench-gate field effect transistors as claimed in claim 2, it is characterised in that: described contra-doping layer and described groove
Bottom surface contact also upwardly extends and the contacts side surfaces upwardly extending part and described groove of described contra-doping layer；
Or, described contra-doping layer is positioned at the bottom of the lower surface of described groove and does not contacts.
4. trench-gate field effect transistors as claimed in claim 1, it is characterised in that: it is formed by the at described body surface
The source region of one conduction type heavily doped region composition；
The first heavily doped drain region of conduction type it is formed with at the back side, described drift region.
5. trench-gate field effect transistors as claimed in claim 4, it is characterised in that also include:
The source electrode graphically formed by front metal layer and grid, described grid is connected by contact hole and described polysilicon gate,
Described source region and described body district are connected to described source electrode by the described contact hole at top；
Metal layer on back, described metal layer on back and described drain contact conduct drain electrode.
6. trench-gate field effect transistors as claimed in claim 1, it is characterised in that: described Semiconductor substrate is silicon substrate.
7. trench-gate field effect transistors as claimed in claim 1, it is characterised in that: described gate dielectric layer is oxide layer.
8. the trench-gate field effect transistors as described in any claim in claim 1-7, it is characterised in that: described groove
Grid field effect transistor is N-type device, and the first conduction type is N-type, and the second conduction type is p-type；Or, described trench gate field
Effect transistor is P-type device, and the first conduction type is p-type, and the second conduction type is N-type.
9. the manufacture method of a trench-gate field effect transistors, it is characterised in that comprise the steps:
Step one, form the drift region of the first conduction type at semiconductor substrate surface；
Step 2, be formed described drift region described semiconductor substrate surface formed hard mask layers；
Step 3, the formation region of lithographic definition groove, remove the described hard mask layers forming region of described groove, institute
The described hard mask layers formed outside region stating groove retains；
Step 4, for mask, described Semiconductor substrate performed etching the described groove of formation, described ditch with described hard mask layers
Groove is positioned in described drift region and the degree of depth of described groove is more than the degree of depth in body district being subsequently formed；
Step 5, with described hard mask layers for mask carry out the second conduction type vertical ion inject, this vertical ion note
Enter autoregistration in the described drift region of the bottom of described groove and inject the second conductive type impurity, by described second conduction type
First conductive type impurity superposition of impurity and described drift region forms contra-doping layer, and described contra-doping layer is used for reducing described ditch
The electric field intensity of the drift region of trench bottom, not reducing the doping content of described drift region and can increase the thickness of described drift region
Under conditions of improve the breakdown voltage of device；
Step 6, remove described hard mask layers；
Step 7, described groove interior surface formed gate dielectric layer, be filled with polysilicon gate in the trench；
Step 8, form the body district of the second conduction type on surface, described drift region；The institute covered by described polysilicon gate side
State body surface for forming raceway groove.
10. the manufacture method of trench-gate field effect transistors as claimed in claim 9, it is characterised in that:
The concentration of described second conductive type impurity is less than or equal to the concentration of the first conductive type impurity of described drift region, described
The net doping type of contra-doping layer is that the first conduction type doping content of the first conduction type and described contra-doping layer is less than institute
State the first conduction type doping content of drift region；
Or, the concentration of described second conductive type impurity is more than the concentration of the first conductive type impurity of described drift region, institute
The net doping type stating contra-doping layer is the second conduction type, forms PN between described contra-doping layer and adjacent described drift region
Knot.
The manufacture method of 11. trench-gate field effect transistors as claimed in claim 9, it is characterised in that: described contra-doping layer
With the bottom surface contact of described groove and upwardly extend and described contra-doping layer upwardly extend part and the side of described groove
Face contacts；
Or, described contra-doping layer is positioned at the bottom of the lower surface of described groove and does not contacts.
The manufacture method of 12. trench-gate field effect transistors as claimed in claim 9, it is characterised in that further comprise the steps of:
Step 9, the source region being made up of the first conduction type heavily doped region in the formation of described body surface；
Step 10, described Semiconductor substrate is carried out thinning back side and carry out backside particulate be infused in the back side, described drift region formed
The first heavily doped drain region of conduction type.
The manufacture method of 13. trench-gate field effect transistors as claimed in claim 12, it is characterised in that also include:
Following front technique is also included after step 9, before step 10:
Form interlayer film in described Semiconductor substrate front, form the contact hole through described interlayer film, form front metal layer
And shapeization forms source electrode and grid, described grid is connected by contact hole and described polysilicon gate, described source region and described body district
It is connected to described source electrode by the described contact hole at top；
Following back process is also included after step 10:
Form metal layer on back, described metal layer on back and described drain contact and as drain electrode.
The manufacture method of 14. trench-gate field effect transistors as claimed in claim 9, it is characterised in that: described quasiconductor serves as a contrast
The end is silicon substrate.
The manufacture method of 15. trench-gate field effect transistors as claimed in claim 9, it is characterised in that: step 7 uses
Thermal oxidation technology forms described gate dielectric layer in the interior surface of described groove.
The manufacture method of 16. trench-gate field effect transistors as claimed in claim 9, it is characterised in that: described hardmask
Layer is formed by silicon oxide and silicon nitride superposition.
The manufacture method of 17. trench-gate field effect transistors as described in any claim in claim 0-16, its feature
Being: described trench-gate field effect transistors is N-type device, the first conduction type is N-type, and the second conduction type is p-type；Or
Person, described trench-gate field effect transistors is P-type device, and the first conduction type is p-type, and the second conduction type is N-type.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111223931A (en) * | 2018-11-26 | 2020-06-02 | 深圳尚阳通科技有限公司 | Trench MOSFET and method of manufacturing the same |
| CN112164722A (en) * | 2020-11-04 | 2021-01-01 | 深圳市威兆半导体有限公司 | Shielded gate MOSFET device with uniformly doped channel and processing technology |
| CN112802753A (en) * | 2020-12-31 | 2021-05-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
| CN115376918A (en) * | 2022-10-26 | 2022-11-22 | 深圳市美浦森半导体有限公司 | IGBT device and manufacturing method thereof |
| WO2023092477A1 (en) * | 2021-11-26 | 2023-06-01 | 华为技术有限公司 | Method for preparing transistor, and chip and terminal |
| CN116435336A (en) * | 2023-03-22 | 2023-07-14 | 瑶芯微电子科技(上海)有限公司 | Groove type MOSFET electric field protection structure and preparation method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5168331A (en) * | 1991-01-31 | 1992-12-01 | Siliconix Incorporated | Power metal-oxide-semiconductor field effect transistor |
| DE10005772A1 (en) * | 2000-02-10 | 2001-08-23 | Infineon Technologies Ag | Trench-MOSFET arrangement esp. n-channel type - has gate electrode provided in trench and separated from semiconductor body and semiconductor layer by insulation layer |
| US20100102383A1 (en) * | 2008-10-23 | 2010-04-29 | Rohm Co., Ltd. | Semiconductor device |
| CN102103997A (en) * | 2009-12-18 | 2011-06-22 | 上海华虹Nec电子有限公司 | Structure of groove type power MOS (Metal Oxide Semiconductor) device and preparation method thereof |
-
2016
- 2016-08-16 CN CN201610675000.0A patent/CN106057905A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5168331A (en) * | 1991-01-31 | 1992-12-01 | Siliconix Incorporated | Power metal-oxide-semiconductor field effect transistor |
| DE10005772A1 (en) * | 2000-02-10 | 2001-08-23 | Infineon Technologies Ag | Trench-MOSFET arrangement esp. n-channel type - has gate electrode provided in trench and separated from semiconductor body and semiconductor layer by insulation layer |
| US20100102383A1 (en) * | 2008-10-23 | 2010-04-29 | Rohm Co., Ltd. | Semiconductor device |
| CN102103997A (en) * | 2009-12-18 | 2011-06-22 | 上海华虹Nec电子有限公司 | Structure of groove type power MOS (Metal Oxide Semiconductor) device and preparation method thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111223931A (en) * | 2018-11-26 | 2020-06-02 | 深圳尚阳通科技有限公司 | Trench MOSFET and method of manufacturing the same |
| CN111223931B (en) * | 2018-11-26 | 2023-06-23 | 深圳尚阳通科技股份有限公司 | Trench MOSFET and manufacturing method thereof |
| CN112164722A (en) * | 2020-11-04 | 2021-01-01 | 深圳市威兆半导体有限公司 | Shielded gate MOSFET device with uniformly doped channel and processing technology |
| CN112802753A (en) * | 2020-12-31 | 2021-05-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
| WO2023092477A1 (en) * | 2021-11-26 | 2023-06-01 | 华为技术有限公司 | Method for preparing transistor, and chip and terminal |
| CN115376918A (en) * | 2022-10-26 | 2022-11-22 | 深圳市美浦森半导体有限公司 | IGBT device and manufacturing method thereof |
| CN116435336A (en) * | 2023-03-22 | 2023-07-14 | 瑶芯微电子科技(上海)有限公司 | Groove type MOSFET electric field protection structure and preparation method |
| CN116435336B (en) * | 2023-03-22 | 2024-01-12 | 瑶芯微电子科技(上海)有限公司 | Groove type MOSFET electric field protection structure and preparation method |
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