^ 1297525 九、發明說明： • 【發明所屬之技術領域】 • 本發明係關於一種半導體淺溝槽隔離（shallow trench isolation)結構之製造方法，尤指一種具不同深度之半導體 淺溝槽隔離結構之製造方法，其特別適用於隔離高電壓操 作之電晶體。 【先前技術】 隨著積體電路（1C)的快速發展，元件的微小化對於高度 修 積集度（integration)而言已是一主要的趨勢。當每個元件的 尺寸縮小而提高積集度時，在各元件之間的隔離結構也必 須跟著縮小。換言之，當必須使用更複雜的技術來隔離元 件時，隔離元件之距離也跟著縮小。目前，淺溝槽隔離 (shallow trench isolation ; STI)技術已廣泛地被應用在次微 米（sub micron)或更小的積體電路製程上。 STI技術係在一基板（substrate)上形成溝槽（trench)，之後 再將氧化物沉積在該溝槽中，作為隔離鄰近電晶體之隔離 ® 層。因為STI之結構具有容易調整其尺寸大小之優點而不會 發生如傳統的區域氧化隔離法（Local Oxidation Isolation Method ; LOCOS)之鳥嘴現象（Bird’s Beak)，因此STI技術非 常適合應用在次微米或更小尺寸之積體電路製程上。 一般在STI製程中只需要一個溝槽即可有效隔離相鄰的 電晶體，但當應用在高電壓時，有時則需要兩個溝槽（具不 同深度）方可有效達到隔離的作用。圖1(a)至1(e)為習知之不 同深度淺溝槽隔離之製作流程示意圖。 w〇788i 109465 005363746-1 1297525 參圖1 (a)，在一基板表面藉由微影（lithography)及钱刻 製程定義一钱刻遮罩12，再藉由該蝕刻遮罩12蝕刻未被遮 蔽之基板10’而於該基板10中形成兩個具一第一深度d之溝 槽11a及lib。接著，利用微影製程形成一光阻13覆蓋該溝 槽lib，而曝露出溝槽iia，如圖1(b)所示。 參圖1(c)，進行另一蝕刻製程，使得曝露之溝槽Ua之深 度加深成為一第二深度D。因為蝕刻過程係使用電漿 (plasma)將反應氣體離子化（i〇nizati〇n)，因此該基板1〇及該 餘刻遮罩12之介面處（即區域a)於餃刻後會因電漿的破壞 而造成凹坑（devoid)，導致往後操作時造成介面漏電流 (junction leakage current)。隨後利用氧電漿（〇xygen plasma) 及溼式蝕刻（wet etching)將該光阻13移除，如圖丨⑷所示。 此時位於溝槽1 lb之該基板1 〇與該蝕刻遮罩12之介面處（即 區域B)因受到溼式蝕刻製程之酸性蝕刻液侵蝕，因此亦會 產生如圖1(c)區域A之凹坑，而造成介面漏電流。 之後，>儿積一咼雄、度電漿（high density plasma ; HDP)氧 化層14至填滿該溝槽lla& llb，再經化學機械研磨 (chemical mechanical polishing ; CMP)後，形成不同深度淺 溝槽隔離結構，如圖1(e)所示。 【發明内容】 本發明之主要目的係提供一種不同深度之半導體淺溝槽 隔離結構之製造方法，藉由形成一阻障襯裡（Hner)保護基板 與蝕刻遮罩之介面，以避免因後續製程之電漿及蝕刻酸液 傷害所造成之凹坑，而得以消除介面漏電流。 1297525 ::明之另二目的係提供一種不同深度之半導體淺溝槽 、、“之製造方法，藉由沉積一阻障襯裡於溝槽之表 二餘刻較深深度之溝槽時可保持較佳之形貌—帅 $月揭不一種不同深度之淺溝槽隔 、、^構之製造方法。首先$ 尤办成遮罩層於一基板上，蝕刻 被該遮罩層覆蓋之該基板’而於該基板中形成至少二個 具一第一深度之第一淺溝槽。其次，於該第一淺溝槽之表 2形成-氧化層，及形成一阻障襯裡於該氧化層及該遮罩 «表面接著’移除位於該第—淺溝槽底部之該阻障概 裡及該氧化層，且敍刻至少_該第一淺溝槽下方之該基板 至-弟二深度而形成至少一第二淺溝槽，其中該第二深度 大於該第一深度。 上述开/成δ亥第一淺溝槽時，可利用光阻或介電質覆蓋不 欲進行姓刻之第一淺溝槽，而以該光阻或介電質作為姓刻 罩幕進行姓刻而形成該第二淺溝槽。該第一及第二淺溝槽 中所填入作為電氣隔離之介，可同時或分次沉積形成。 、本發明利用一阻障襯裡保護基板及姓刻遮軍之介面，以 避免因後續製程之電漿或姓刻酸液傷害而造成凹坑，進而 消除介面漏電流。另外，當由第一淺溝槽姓刻形成第二淺 溝槽的過程中，藉由該阻障襯裡的約束，可使第二淺溝槽 具有較佳的形貌，意即可抑制側向㈣刻。因此，本發明曰 之不同深度之半導體淺溝槽隔離之製作方法確實可達成預 期目的。 【實施方式】 W07881 χ〇9465 0〇5363746-ι I297525 Q 2(a)至2(h)例示本發明第一實施例之不同深度半導體 =溝槽隔離結構之製作方法，其說明如下。參圖2⑷，首先 提供-具料層22(mask)之基板2〇。該料層22包含複數 個第一開孔21a及複數個第二開孔21b，其中該第一開孔21& 及該第二開孔21b係以微影及蝕刻製程形成。為說明方便， 各圖僅以單一之第一開孔21a及第二開孔2ib代表。之後， 钱刻於該第一開孔21a及第二開孔21b下方之基板2〇，以形^ 1297525 IX. Description of the Invention: • Technical Field of the Invention The present invention relates to a method for fabricating a semiconductor shallow trench isolation structure, and more particularly to a semiconductor shallow trench isolation structure having different depths. A manufacturing method that is particularly suitable for isolating high voltage operated transistors. [Prior Art] With the rapid development of the integrated circuit (1C), the miniaturization of components has become a major trend for highly integrated integration. As each component is reduced in size to increase the degree of integration, the isolation structure between the components must also be reduced. In other words, when more complex techniques must be used to isolate the components, the distance of the isolation components is also reduced. Currently, shallow trench isolation (STI) technology has been widely used in sub-micron or smaller integrated circuit processes. The STI technique forms a trench on a substrate, and then deposits oxide in the trench as an isolation layer that isolates the adjacent transistor. Because the structure of the STI has the advantage of easily adjusting its size without the Bird's Beak of the Local Oxidation Isolation Method (LOCOS), the STI technology is very suitable for sub-micron or Smaller size integrated circuit process. Generally, only one trench is needed in the STI process to effectively isolate adjacent transistors, but when applied at high voltages, sometimes two trenches (with different depths) are required to effectively achieve isolation. Figures 1(a) through 1(e) are schematic diagrams showing the fabrication process of conventional shallow trench isolations of different depths. W〇788i 109465 005363746-1 1297525 Referring to Fig. 1 (a), a mask 12 is defined on the surface of a substrate by lithography and etching process, and the etching is masked by the etching mask 12 The substrate 10' forms two trenches 11a and lib having a first depth d in the substrate 10. Next, a photoresist 13 is formed by the lithography process to cover the trench lib, and the trench iia is exposed, as shown in Fig. 1(b). Referring to Fig. 1(c), another etching process is performed to deepen the depth of the exposed trench Ua to a second depth D. Since the etching process uses plasma to ionize the reaction gas, the interface between the substrate 1 and the mask 12 (ie, the area a) is electrically discharged after the dumpling is engraved. Destruction of the slurry causes devoids, resulting in a junction leakage current during subsequent operations. The photoresist 13 is then removed using an oxygen plasma and wet etching, as shown in Figure 4 (4). At this time, the interface between the substrate 1 〇 of the trench 1 lb and the etch mask 12 (ie, the region B) is eroded by the acidic etching solution subjected to the wet etching process, and thus the region A as shown in FIG. 1(c) is also generated. The pits cause leakage current in the interface. After that, > a high density plasma (HDP) oxide layer 14 is filled to fill the trenches 11a & llb, and then chemical mechanical polishing (CMP), forming different depths Shallow trench isolation structure, as shown in Figure 1 (e). SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for fabricating a semiconductor shallow trench isolation structure of different depths by forming a barrier liner (Hner) to protect the interface between the substrate and the etch mask to avoid subsequent processing. The plasma and the etching acid damage the pits caused by the damage, and the interface leakage current is eliminated. 1297525: The other two objectives are to provide a shallow trench of semiconductors of different depths, "the manufacturing method can be better by depositing a barrier lining on the trenches of the deeper depth of the surface of the trenches." Morphology—Shuany is not a method of manufacturing shallow trenches and structures of different depths. First, a mask layer is formed on a substrate to etch the substrate covered by the mask layer. Forming at least two first shallow trenches having a first depth in the substrate. Secondly, forming an oxide layer on the surface 2 of the first shallow trench, and forming a barrier liner on the oxide layer and the mask The surface is then removed from the barrier layer at the bottom of the first shallow trench and the oxide layer, and the substrate is at least _ the first shallow trench below the substrate to form a depth of at least one a shallow trench, wherein the second depth is greater than the first depth. When the first shallow trench is opened/formed, the first shallow trench may be covered by a photoresist or a dielectric. And the photoresist or dielectric is used as a surname mask to form a second shallow trench. The first and second shallow trenches are filled as electrical isolation, and can be deposited simultaneously or in stages. The present invention utilizes a barrier lining to protect the substrate and the interface of the surname to avoid the subsequent process. The plasma or the surname is damaged by the acid to cause the pit, thereby eliminating the leakage current of the interface. In addition, when the second shallow trench is formed by the first shallow trench, the constraint of the barrier lining can be The second shallow trench has a better topography, which means that the lateral (four) etching can be suppressed. Therefore, the fabrication method of the semiconductor shallow trench isolation of different depths of the present invention can achieve the intended purpose. [Embodiment] W07881 Χ〇9465 0〇5363746-ι I297525 Q 2(a) to 2(h) illustrate a method for fabricating different depth semiconductor=trench isolation structures according to the first embodiment of the present invention, which is described below. Referring to FIG. 2(4), first provided - a substrate 2 having a mask layer 22. The material layer 22 includes a plurality of first openings 21a and a plurality of second openings 21b, wherein the first openings 21 & and the second openings 21b are The lithography and etching processes are formed. For the convenience of explanation, each figure only After the first opening 21a and a second opening on behalf 2ib., Money engraved on the first hole and the second hole 21a of the underlying substrate 2〇 21b, to form
成具一第一洙度d之第一淺溝槽23a。接著於該第一淺溝槽 3a之表面利用熱氧化（thermai⑽丨如如…形成一氧化層 24,如圖2⑻所示。在形成該氧化層辦，可一併使得該第 -淺溝槽23a的角落241變得較為圓滑，而得以減少漏電流 的發生。 立參圖2(c)，接著在該氧化層24及遮罩層“之表面形成一阻 障襯裡25(liner)，其可為一氮化矽(SiN)層或一氮氧化矽 (ON)層。該阻卩平襯裡25遮蔽該基板與該遮罩層u之介 处用以防止後績電漿蝕刻或溼式蝕刻製程對該介面處 之侵蝕。 立參圖2(d)’執行―餘刻製程，將位於該第—淺溝槽仏底 P之“阻卩早襯裡25及该氧化層24移除。隨後，利用微影製 知^義-光阻26’其係覆蓋一側之第一淺溝槽…，即填滿 該第二開孔21b下方之該第一淺溝槽…，如圖2(e)所，示。 參圖2(f)，執行一蝕刻製程，未被該光阻％覆蓋之第一淺 溝槽23a (與該第一開孔仏相對應）下方之基板2〇將被移 除至第一深度D，而形成第二淺溝槽23b。其中該第二深 W07881 109465 005363746-1 -8 - 1297525 度D係大於該第一深度d。 於本實施例中，該第一淺構槽23a及第二淺溝槽23b可採 用反應式離子蝕刻（reactive i〇n etching ; RIE)、高密度電漿 餘刻或其他钱刻方式形成。在蝕刻過程中雖然有電漿產 生’但因該阻障襯裡25可有效遮蔽該基板2〇與該遮罩層22 之介面處，故可避免如習知技術於該介面處產生凹坑。 參圖2(g)，移除該光阻26，沉積一介電質27於該第一淺 溝槽23a及該第二淺溝槽23b中，並形成至該遮罩層上方 一預定高度。本實施例中該介電質27係高密度電漿之氧化 層（HDP oxide)。之後，利用化學機械研磨㈣ mechanical p〇iishing)進行平坦化，將該遮罩層以上方之該 介電質27移除，以形成一不同淡声夕主道 ^ |j /木度之牛導體淺溝槽隔離結 構2，如圖2(h)所示。 圖3(a)至3(d)例示本發明第二實施例之不同深度之半導 體淺溝槽隔離結構之製作方法，其說明如下。首先執行如 圖2⑷至圖2(d)所示之製程步驟。接著，沉積一第一介電質 28而至少填滿該第一淺溝槽23a，如圖3(句所示。"貝 參照圖3(b)，利用微影製程定義一光阻加，其係覆蓋與 該第二開孔21b相應之第一淺溝槽23a。 ^ ^ 要考，進行蝕刻製 程，移除未被該光阻26,覆蓋之該介電質28 、… 下方之基板20至一第二深度E，以形成具一 夂冓槽3a 、、 ’、弟二深度E之第 二淺溝槽23c，如圖3(c)所示。其中該第— -深度d。 木度£係大於該第 參圖3(d)，移除該光阻26, 沉積一第 介電質28,於該第 W07881 109465 005363746-1 ^297525 二淺溝槽23c中。並使用化學機械研磨方式進行平坦化，而 將忒遮罩層22上方之該介電質28及28，移除，以形成本發明 之不同深度之半導體淺溝槽隔離結構2,。 綵上所述’本發明之不同深度之半導體淺溝槽隔離結構 之製作方法在形成第二淺溝槽之前，先利用一阻障襯裡保 遵基板及㈣遮罩之介面，以避免因後續製程之電聚及钱 刻酸液傷害而造成凹坑’進而消除介面漏電流。另外，當 由第一淺溝槽餘刻形成第二淺溝槽的過程中，藉由該阻障 襯裡的約束可抑制側向的蝕刻，使得第二淺溝槽具有較佳 的形貌。據此’本發明之不同深度之半導體淺溝槽隔離之 製作方法確實可達成預期目的。 本發明之技術内容及技術特點已揭示如上，然而熟悉本 項技術之人士仍可能基於本發明之教示及揭#而作種種不 月離本發明精神之替換及修飾。因此，本發明之保護範圍 應不限於實施例所揭示者，而應包括各種不背離本發明之 替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡單說明】 圖1(a)至1(e)係習知之不同深度淺溝槽隔離之製作流程 示意圖； 圖2⑷至2(h)顯示本發明第一實施例之半導體^槽隔 離結構之製作方法；及 圖3(a)至3(d)顯示本發明第二實施例之半導體淺溝槽隔 離結構之製作方法。 【主要元件符號說明】 1297525 2、21不同深度淺溝槽隔離結構 10、20 基板 12 蝕刻遮罩 14、24 氧化層 25 阻障襯裡 28、28’ 第一介電質 21a 第一開孔 23a 第一淺溝槽 241角落 11a 、lib 溝槽 13 ^ 26、26’ 光阻 22 遮罩層 27 介電質 28， 第二介電質 21b 第二開孔 23b 、23c 第二淺溝槽A first shallow trench 23a having a first twist d is formed. Then, an oxide layer 24 is formed on the surface of the first shallow trench 3a by thermal oxidation (theran (10), for example, as shown in FIG. 2 (8). In forming the oxide layer, the first shallow trench 23a can be collectively formed. The corner 241 becomes relatively smooth, and the occurrence of leakage current is reduced. The reference 2 (c), and then a barrier liner 25 (liner) is formed on the surface of the oxide layer 24 and the mask layer, which may be a layer of tantalum nitride (SiN) or a layer of yttrium oxynitride (ON). The barrier lining 25 shields the substrate from the mask layer u to prevent post-production plasma etching or wet etching process The erosion at the interface. The reference 2(d)'execution-receiving process will remove the "resistance early lining 25 and the oxide layer 24 at the bottom of the first shallow trench". Subsequently, using micro The shadow system knows that the photoresist 26' covers the first shallow groove on one side, that is, fills the first shallow groove below the second opening 21b, as shown in Fig. 2(e). Referring to FIG. 2(f), an etching process is performed, and the substrate 2〇 under the first shallow trench 23a (corresponding to the first opening pupil) not covered by the photoresist% is removed to the first Depth D, and forming a second shallow groove 23b, wherein the second deep W07881 109465 005363746-1 -8 - 1297525 degrees D is greater than the first depth d. In the embodiment, the first shallow groove 23a and The second shallow trench 23b may be formed by reactive ion etching (RIE), high-density plasma re-etching or other engraving. Although plasma is generated during the etching process, the barrier may be formed. The lining 25 can effectively shield the interface between the substrate 2 and the mask layer 22, so that the pits can be prevented from being generated at the interface as in the prior art. Referring to FIG. 2(g), the photoresist 26 is removed, and a deposition is performed. The dielectric material 27 is formed in the first shallow trench 23a and the second shallow trench 23b and formed to a predetermined height above the mask layer. In this embodiment, the dielectric 27 is oxidized by high-density plasma. Layer (HDP oxide). Thereafter, planarization is performed by chemical mechanical polishing (4), and the mask layer is removed from the dielectric 27 above to form a different light-sounding main road ^ |j / Woody Bull Conductor Shallow Trench Isolation Structure 2, as shown in Figure 2(h). 3(a) to 3(d) illustrate a method of fabricating a shallow trench isolation structure of a semiconductor having different depths according to a second embodiment of the present invention, which is explained below. First, the process steps as shown in Figs. 2(4) to 2(d) are performed. Next, a first dielectric material 28 is deposited to fill at least the first shallow trench 23a, as shown in FIG. 3 (described in the sentence. "Before referring to FIG. 3(b), a photoresist addition is defined by a lithography process, The first shallow trench 23a corresponding to the second opening 21b is covered. ^ ^ To perform an etching process, the substrate 20 under the dielectric 28, ... not covered by the photoresist 26 is removed. Up to a second depth E to form a second shallow trench 23c having a groove 3a, ', and a depth E, as shown in Fig. 3(c). wherein the first - depth d. The volume is larger than the reference FIG. 3(d), the photoresist 26 is removed, and a dielectric material 28 is deposited in the second shallow trench 23c of the W07881 109465 005363746-1 ^297525. The chemical mechanical polishing method is used. The planarization is performed, and the dielectrics 28 and 28 over the germanium mask layer 22 are removed to form the semiconductor shallow trench isolation structures 2 of different depths of the present invention. Depth semiconductor shallow trench isolation structure is fabricated by using a barrier lining to protect the substrate and (4) the mask interface before forming the second shallow trench The pit is caused by the electro-convergence of the subsequent process and the damage of the acid solution, thereby eliminating the interface leakage current. In addition, when the second shallow trench is formed by the first shallow trench, the barrier lining is used. The constraint can suppress the lateral etching, so that the second shallow trench has a better topography. According to the method of manufacturing the shallow trench isolation of different depths of the present invention, the intended purpose can be achieved. The technical content of the present invention And the technical features have been disclosed as above, but those skilled in the art may still make various alternatives and modifications to the spirit of the present invention based on the teachings and disclosures of the present invention. Therefore, the scope of protection of the present invention should not be limited to the embodiments. The disclosures are intended to cover various alternatives and modifications without departing from the scope of the invention, and are covered by the following claims. FIG. 1(a) to 1(e) are conventional shallow trenches of different depths. 2(4) to 2(h) show a method of fabricating a semiconductor trench isolation structure according to a first embodiment of the present invention; and FIGS. 3(a) to 3(d) show a second embodiment of the present invention Semi-guide Shallow trench isolation structure fabrication method [Main component symbol description] 1297525 2, 21 different depth shallow trench isolation structure 10, 20 substrate 12 etching mask 14, 24 oxide layer 25 barrier lining 28, 28' Electric material 21a first opening 23a first shallow groove 241 corner 11a, lib groove 13^26, 26' photoresist 22 mask layer 27 dielectric 28, second dielectric 21b second opening 23b, 23c second shallow groove