KR100321174B1 - Method of forming isolation layer in semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming an STI type device isolation film, and in particular, the method sequentially deposits a pad Ta ₂ O ₅ film and a polysilicon film on a semiconductor substrate in sequence, and uses a photolithography and etching process using a device isolation mask. After the pad Ta ₂ O ₅ film is patterned, the substrate is etched to a predetermined depth to form a trench, a sacrificial oxide film is formed on and removed from the trenched substrate, and then a liner oxide film is formed on the resultant, and a gap fill oxide film is formed inside the trench. After filling and chemical mechanical polishing, the gap fill oxide and the liner oxide are wet etched to a predetermined thickness to reduce the step difference between the device isolation film and the substrate surface, and the pad Ta ₂ O ₅ film and the polysilicon film pattern are removed to form an oxide film on the substrate. A device isolation film is formed. Therefore, the present invention can safely protect the surface of the substrate from the etching solution during the wet etching and polysilicon removal process performed after the gapfill oxide film polishing process by Ta ₂ O ₅ having excellent etching resistance compared to the silicon oxide film (SiO ₂ ).

Description

Method of forming isolation layer in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to forming a device isolation film of a semiconductor device that suppresses surface pit defects in an active region when a nitride film, which is a mask layer, is replaced with a polysilicon film during a trench isolation device manufacturing process. It is about a method.

Recently, as the development of semiconductor device manufacturing technology and the application of memory devices have been expanded, the development of large-capacity memory devices has been progressed. It has been promoted by a memory cell study. In particular, the reduction of the device isolation film that separates the devices has emerged as one of the important items in the technology of miniaturization of memory devices.

Conventional device isolation technology has mainly been a LOCal Oxidation of Silicon (LOCOS) technology to selectively grow a thick oxide film on the semiconductor substrate to form a device isolation film. However, the LOCOS technique cannot reduce the width of the isolation region due to side diffusion and bird's beak of the isolation layer. Therefore, a new device isolation technology is needed because the LOCOS technology cannot be applied to a large-capacity memory device whose device design dimension is reduced to submicron or less.

As a result, a trench capable of electrically separating devices by forming trenches having a width of about 1Å or less and a depth of several tens to hundreds of Å on a semiconductor substrate due to the necessity of a new device isolation technology and the development of etching technology. Device isolation technology has emerged. This trench device isolation technology allows for a reduction in device isolation area close to 80% compared to conventional LOCOS technology.

Moreover, recently, the STI (Shallow Trench Isolation) process, which greatly reduces the stress applied to the wafer substrate and improves the problem of the trench isolation layer, has emerged. The STI process is a technique for forming a device isolation film by forming a trench having a predetermined depth in a semiconductor substrate, depositing an oxide film on the trench by chemical vapor deposition, and etching an unnecessary oxide film by a chemical mechanical polishing process.

In the conventional STI process, a silicon oxide film (SiO ₂ ) and a nitride film (SiN) are stacked and used as a mask pattern for forming a trench in a substrate. However, the nitride film has a problem that it can not sufficiently digest the stress to the lower substrate generated during the manufacturing process.

To this end, the improved STI technology uses polysilicon as a trench mask pattern that can reduce the stress applied to the bottom instead of the nitride film.

However, when the polysilicon film is used as a mask layer, a subsequent wet etching process is performed due to the crystal grains of the polysilicon (the oxide film of the trench portion to reduce the step difference between the active region and the field region in the state where the thickness of the remaining polysilicon film is low after polishing the gapfill oxide film). In the process of shallow dip, the etching liquid flows through the grains to etch the pad oxide layer under the etching.

When the local etching of the pad oxide film occurs, the polysilicon etching solution is introduced at a portion where the pad oxide film does not exist when polysilicon is removed, thereby causing a pit defect on the surface of the substrate. Such substrate defects are not completely removed even by the sacrificial oxide process, but also affect the gate oxide growth afterward, thereby reducing the reliability and yield of the semiconductor manufacturing process.

An object of the present invention is to use the Ta ₂ O ₅ etch resistance compared to the silicon oxide film (SiO ₂ ) when using polysilicon as a mask pattern in the STI manufacturing process to eliminate the substrate surface pit defects during the wet etching process and polysilicon removal process The present invention provides a method of forming a device isolation film of a semiconductor device, which can prevent and increase yield and reliability of a semiconductor manufacturing process.

1 to 7 are process flowcharts illustrating a method for forming an STI device isolation layer of a semiconductor device using a Ta ₂ O ₅ mask pattern during trench manufacture according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: silicon substrate 12: pad Ta ₂ O ₅ film

14: polysilicon film 16: photoresist pattern

18: trench 20: liner oxide film

22: gap fill oxide ISO: device isolation region of substrate

In order to achieve the above object, according to the present invention, in forming a device isolation film having a trench structure for defining an active region and an isolation region of a device on a semiconductor substrate, a pad Ta ₂ O ₅ film and a polysilicon film are sequentially formed on the semiconductor substrate. After stacking, the photolithography and etching process using the device isolation mask is performed to pattern the stacked polysilicon film and the pad Ta ₂ O ₅ film, and then to open the substrate region to be the device isolation region, and then the patterned polysilicon film and Etching the substrate exposed by the pad Ta ₂ O ₅ film to a predetermined depth to form a trench, and performing an oxidation process to form and then remove the sacrificial oxide film on the trench-formed substrate, and to remove the trench. Forming a liner oxide layer, filling a gapfill oxide layer in the trench, and chemically polishing it , The pad Ta ₂ O ₅ film and removing the polysilicon film pattern comprises: forming a device isolation film on a substrate made of an oxide film.

In the production method of the present invention, the thickness of the pad Ta ₂ O ₅ film is 50 ~ 200Å, the deposition process is using a chemical vapor deposition method, after the Ta ₂ O ₅ film is deposited, a high temperature heat treatment step is further performed. The high temperature heat treatment may be performed at 800 to 1050 ° C. for 10 seconds to 100 minutes in an O ₂ or O ₃ atmosphere, and may further supply N ₂ O gas.

In the manufacturing method of the present invention, before depositing the pad Ta ₂ O ₅ film, it is preferable to further form an oxide film on the substrate for easy removal of the Ta ₂ O ₅ film thereafter.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 7 are process flowcharts illustrating a method of forming an STI type device isolation film of a semiconductor device using a Ta ₂ O ₅ mask pattern when manufacturing a trench according to the present invention.

Referring to this, the manufacturing process of the STI type device isolation film of the present invention is as follows.

First, as shown in FIG. 1, a pad Ta ₂ O ₅ film 12 having a thickness of about 50 to about 200 kPa in order to alleviate stress of a polysilicon film to be subsequently deposited on a silicon substrate 10 as a semiconductor substrate and to prevent etching defects of the substrate. Deposit. Here, the deposition of the pad Ta ₂ O ₅ film 12 uses chemical vapor deposition, but is performed in a low pressure or plasma and metal organic chemical vapor deposition chamber. Then, after depositing a pad Ta ₂ O ₅ film 12 may be subjected to additional high temperature heat treatment step to reduce the public of Ta ₂ O ₅ film. This proceeds in an O ₂ or O ₃ atmosphere at 800 to 1050 ° C. for 10 seconds to 100 minutes, and may further supply N ₂ O gas.

In addition, a polysilicon film 14 is deposited on the pad Ta ₂ O ₅ film 12 to define a device isolation region, and then a polysilicon film 14, which is used for stopping etching during gap-mechanical oxidation and chemical mechanical polishing, is deposited to a thickness of 500 to 4000 kPa. do. In this case, the polysilicon film 14 may be an amorphous or crystalline silicon film alone, or may be used in a ratio of 1 to 9: 1 with an amorphous and crystalline silicon film.

Although not shown in the drawings, a silicon nitride oxide layer (SiON) may be further deposited as a hard mask in order to perform an easy photographing process on the polysilicon layer 14.

Next, as shown in FIG. 2, a photoresist using a device isolation mask is performed to form a photoresist pattern 16 on the polysilicon layer 14.

Next, as shown in FIG. 3, the resultant is subjected to an etching process to pattern the polysilicon film 14 and the pad Ta ₂ O ₅ film 12 stacked in accordance with the photoresist pattern 16. The substrate portion to be an isolation region is opened.

Then, the trench 18 is formed by etching the substrate exposed by the patterned polysilicon film 14 'and the pad Ta ₂ O ₅ film 12' by a predetermined depth, for example, about 1500 to 7000 GPa. Reference numeral M defines a pattern composed of an etched polysilicon film 14 'and a pad Ta ₂ O ₅ film 12'.

Next, although not shown in the figure, a sacrificial oxidation process is performed to smooth the trench edges while eliminating substrate damage that occurs during the etching process to form the trench 18. For example, a sacrificial oxide film (not shown) is formed on the substrate 10 having the trench 18 formed thereon by an oxidation process (temperature of 800 to 1200 ° C), and then the film is removed by this etching process.

Next, as shown in FIG. 4, the resultant is subjected to an oxidation process to form a liner oxide film 20 between the gap fill oxide film and the substrate to be buried in a trench about 20 to 150 kPa. In this case, a silicon oxide film (SiO ₂ ) or Ta ₂ O ₅ may be used as the liner oxide film 20. If Ta ₂ O ₅ is used, the etching resistance can be improved by densification anneal. This annealing process is carried out at a temperature of 800 to 1050 ° C., but using O ₂ , N ₂ O, O ₂ / O ₃ alone or a mixed gas as a reaction gas.

Next, as shown in FIG. 5, the gap fill oxide film 22 is deposited on the resultant by using a high density plasma method, and fills it into the trench 18. In this case, the gapfill oxide layer 22 may be formed of a material having good gapfill characteristics such as O ₃ -TEOS (Tetra Ethyl Ortho Silicate) or HDP (High Density Plasma).

In order to increase the density of the gap fill oxide film 22, an annealing process is performed at 950 to 1200 占 폚.

Next, as shown in FIG. 6, the resultant is planarized by a chemical mechanical polishing (CMP) process, and a cleaning process using HF or BOE is performed to increase the height of the device isolation layer to about 150 to 500 kPa with respect to the silicon substrate. Etch the result so that there is little step That is, the planarized liner oxide film 20 'of the trench portion is reduced in order to reduce the step difference between the active region and the device isolation region in the state where the thickness of the remaining polysilicon film 14' is low after the chemical mechanical polishing of the gapfill oxide film 22 '. And Ta etch to the etch solution when the oxide etch solution passing through the crystal grains of the polysilicon film pattern 14 ′ flows into the Ta ₂ O ₅ film 12 ′ when shallow dips the gapfill oxide film 22 ′. _{Since the} etching resistance of the ₂ O ₅ film is large, it is possible to prevent substrate damage from the etching solution.

Hereinafter, Table 1 compares the etching resistance of the thermal oxide film and the Ta ₂ O ₅ film during the wet etching process.

Etchant Thermal Oxidation Film (Å / sec) Ta ₂ O ₅ film (Å / sec) DI: HF = 5: 1 10 0.125 DI: HF = 50: 1 One 0.0125

Referring to this, it can be seen that the Ta ₂ O ₅ film 12 ′ of the device isolation mask pattern of the present invention has better etching resistance than the oxide film (SiO ₂ ).

Next, as shown in FIG. 7, the polysilicon layer pattern 14 ′ is removed, and the pad Ta ₂ O ₅ layer 12 ′ is removed to form oxide layers 20 ′ and 22 ′ on the substrate. An isolation layer ISO is formed. At this time, since the Ta ₂ O ₅ film 12 ′ protects the substrate surface from the etching solution when the polysilicon layer pattern 14 ′ is removed, occurrence of pit defects on the substrate surface is suppressed.

Between the manufacturing method of the present invention, the pad Ta ₂ O ₅ prior to depositing the film 12, after the Ta ₂ O ₅ film is easy to remove the substrate 10 and the pad Ta ₂ O ₅ film 12 An oxide film may be further formed.

As described above, in the present invention, when polysilicon is used as a mask pattern in an STI type device isolation process, a Ta ₂ O ₅ film having better etching resistance than a silicon oxide film (SiO ₂ ) is used as a pad film between a substrate and a polysilicon film. This prevents the surface defects of the substrate generated during the wet etching process and the polysilicon film removal process performed after the gapfill oxide chemical mechanical chemical chemical mechanical polishing process to reduce the step between the device isolation film and the substrate surface.

Therefore, the present invention can greatly improve the yield and reliability of the semiconductor manufacturing process.

Claims (6)

In forming a device isolation film having a trench structure to define an active region and an isolation region of a device on a semiconductor substrate, After sequentially stacking the pad Ta ₂ O ₅ film and the polysilicon film on the semiconductor substrate, the photolithography and etching process using the device isolation mask was performed to pattern the stacked polysilicon film and the pad Ta ₂ O ₅ film, and then Opening a substrate portion to be a separation region; Etching the substrate exposed by the patterned polysilicon film and the pad Ta ₂ O ₅ film to a predetermined depth to form a trench; Performing an oxidation process to form a sacrificial oxide film on the trenched substrate and then removing the sacrificial oxide film; Forming a liner oxide layer on the resultant trench; Filling a gapfill oxide layer into the trench and chemically polishing it; And And removing the pad Ta ₂ O ₅ film and the polysilicon film pattern to form a device isolation film formed of an oxide film on a substrate. The method of claim 1, wherein the thickness of the pad Ta ₂ O ₅ film is 50 to 200 kPa. The method of claim 1, wherein the pad Ta ₂ O ₅ film is deposited using a chemical vapor deposition method, and after the Ta ₂ O ₅ film is deposited, a high temperature heat treatment step is further performed. The method of claim 3, wherein the high temperature heat treatment is performed at 800 to 1050 ° C. for 10 seconds to 100 minutes in an O ₂ or O ₃ atmosphere. The method of claim 4, wherein the N ₂ O gas is additionally supplied during the high temperature heat treatment process. The method of claim 1, further comprising, before depositing the pad Ta ₂ O ₅ film, further forming an oxide film on the substrate for easy removal of the Ta ₂ O ₅ film.