CN112201616A - Method for improving copper hillock in copper interconnection process - Google Patents
Method for improving copper hillock in copper interconnection process Download PDFInfo
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- CN112201616A CN112201616A CN202010992783.1A CN202010992783A CN112201616A CN 112201616 A CN112201616 A CN 112201616A CN 202010992783 A CN202010992783 A CN 202010992783A CN 112201616 A CN112201616 A CN 112201616A
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- copper
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- layer
- protective film
- planarization process
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- 239000010949 copper Substances 0.000 title claims abstract description 132
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 131
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 131
- 238000000034 method Methods 0.000 title claims abstract description 97
- 230000001681 protective effect Effects 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000007669 thermal treatment Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
Abstract
The invention relates to a method for improving copper hillock in copper interconnection process, which relates to the semiconductor integrated circuit manufacturing technology, in the copper interconnection process, by adding a rapid heat treatment process and a second planarization process before the process of forming a copper protective film layer, the copper hillock can be released in advance, the released copper hillock can be eliminated, the serious product reliability problem caused by the occurrence of the copper hillock caused by the formation process of the protective film layer is avoided, and the method has the advantages of simple process, no influence on the original process, low cost and easy realization.
Description
Technical Field
The present invention relates to semiconductor integrated circuit manufacturing technology, and more particularly, to a method for improving copper hillocks in copper interconnect process.
Background
In the fabrication of semiconductor integrated circuits, copper vias (via) or copper metal layers (metal) are often used to interconnect various parts of a semiconductor device.
Fig. 1 is a partial schematic view of an exemplary semiconductor device including a copper via and a copper metal layer, as shown in fig. 1, a via is formed in a silicon substrate 100, the via is filled with copper to form a copper via 110 for realizing a conductive function, and a metal layer 120 is formed on a dielectric layer, and the metal layer 120 can be electrically connected with other metal layers through the via. Fig. 1 is merely an exemplary illustration of the problem of copper vias and copper hillocks in copper metal layers, and fig. 1 is not intended to limit the relative positions of the layers and structures, as an actual product is shown in fig. 1.
In the prior art, a protective film layer 130 is usually formed on the copper via and the copper metal layer after the copper via and the copper metal layer are formed, and the protective film layer 130 plays a role of isolating and protecting copper in the copper via and the copper metal layer to prevent, for example, copper diffusion. Then, since the protection film layer 130 is usually formed at a certain temperature, for example, 300 to 400 degrees celsius, which causes the uneven copper hillocks 140 to protrude from the copper surface, and the protection film layer 130 is not covered well, referring to fig. 2, fig. 2 is a schematic diagram of the protection film layer formed in the prior art, as shown in fig. 2, the protection film layer 130 is split or pierced by the copper hillocks 140 to form the through holes 150. Further, as shown in fig. 3, in the schematic diagram of the prior art in which copper diffuses out through the protective film via, as shown in fig. 3, after the protective film 130 is split or broken by the copper mound 140 to form a via 150, copper diffuses out through the via 150 in the subsequent process, and even the copper via and the copper metal layer themselves form a hole, which causes a serious product reliability problem.
Disclosure of Invention
The invention provides a method for improving copper hillocks in a copper interconnection process, which comprises the following steps: s1: forming a groove of the semiconductor device for forming a copper interconnection structure, wherein a dielectric layer is filled around the groove; s2: forming a copper layer, wherein the copper layer fills the groove and covers the surface of the dielectric layer; s3: carrying out a first planarization process to remove copper outside the groove; s4: carrying out a rapid thermal treatment process to form copper hillocks on the surface of the copper; s5: carrying out a second planarization process to remove the copper hillocks and form a copper interconnection structure; and S6: a protective film layer is formed over the copper interconnect structure.
Further, the groove is a groove for forming a copper via.
Furthermore, the groove is used for forming a copper metal layer.
Further, step S2 includes forming a barrier layer on the surface of the recess, and then forming a seed layer.
Furthermore, the first planarization process and the second planarization process jointly enable the thickness of the dielectric layer to meet the requirements of the processes.
Furthermore, the time of the first planarization process is longer than that of the second planarization process.
Furthermore, the time of the second planarization process is between 10s and 30 s.
Further, the temperature of the rapid thermal processing in step S4 is higher than the temperature of the protective film forming process in step S6.
Further, the temperature of the protective film forming process in the step S6 is 350 degrees celsius, and the temperature of the rapid thermal processing process in the step S4 is 400 degrees celsius.
Furthermore, the groove is a through silicon via.
In the copper interconnection process, the rapid heat treatment process and the second planarization process are added before the process of forming the copper protective film, so that the copper hillock can be released in advance and eliminated, the problem of serious product reliability caused by the occurrence of the copper hillock caused by the forming process of the protective film is solved, the process is simple, the original process is not influenced, the cost is low, and the method is easy to realize.
Drawings
Fig. 1 is a partial schematic view of a typical semiconductor device including a copper via and a copper metal layer.
Fig. 2 is a schematic diagram of a prior art after a protective film layer is formed.
Fig. 3 is a schematic diagram of copper diffusion through a protective film via hole in the prior art.
Fig. 4a to 4f are schematic views illustrating a process of forming a copper via according to an embodiment of the invention.
Fig. 5 is a schematic diagram illustrating a protective film layer formed according to an embodiment of the invention.
FIG. 6 is a schematic diagram of the diffusion of Cu through the through hole of the passivation layer according to one embodiment of the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In one embodiment, the present invention provides a method for improving copper hillocks in a copper interconnect process, comprising: s1: forming a groove of the semiconductor device for forming a copper interconnection structure, wherein a dielectric layer is filled around the groove; s2: forming a copper layer, wherein the copper layer fills the groove and covers the surface of the dielectric layer; s3: carrying out a first planarization process to remove copper outside the groove; s4: carrying out a rapid thermal treatment process to form copper hillocks on the surface of the copper; s5: carrying out a second planarization process to remove the copper hillocks and form a copper interconnection structure; and S6: a protective film layer is formed over the copper interconnect structure.
Specifically, referring to fig. 4a to 4f, fig. 4a to 4f are schematic views illustrating a process of forming a copper via according to an embodiment of the invention. Referring to fig. 5 and 6, fig. 5 is a schematic diagram illustrating a protective film layer formed according to an embodiment of the invention, and fig. 6 is a schematic diagram illustrating copper diffused through a through hole of the protective film layer according to an embodiment of the invention. The method for improving the copper hillock in the copper interconnection process, provided by the embodiment of the invention, comprises the following steps:
s1: forming a groove 210 of the semiconductor device for forming a copper interconnection structure, wherein the periphery of the groove 210 is filled with a dielectric layer 220;
as shown in fig. 4a, for example, to form a copper via, a recess 210 is formed in a semiconductor substrate 200 and a dielectric layer 220 thereon. As shown in fig. 4a, the formation of a copper via is taken as an example, but the groove 210 may also be a groove for forming a copper metal layer.
S2: forming a copper layer 213, wherein the copper layer 213 fills the groove 210 and covers the surface of the dielectric layer 220;
as shown in fig. 4a, the method further comprises forming a barrier layer 211 on the surface of the recess 210, then forming a seed layer 212, and then forming a copper layer 213 as shown in fig. 4b, wherein the copper layer 213 fills the recess 210 and covers the surface of the dielectric layer 220.
S3: carrying out a first planarization process to remove the copper outside the groove 210;
as shown in fig. 4c, only the copper in the recess 210 remains after the first planarization process.
S4: performing a rapid thermal processing process to form copper hillocks 240 on the surface of the copper;
as shown in fig. 4d, the surface copper grains are recrystallized to grow copper hillocks 240 under the heat of the rapid thermal processing. That is, the rapid thermal processing process releases the copper hillocks of copper in the recess 210.
S5: as shown in fig. 4e, a second planarization process is performed to remove the copper hillocks 240 and form a copper interconnect structure 250;
in one embodiment, the first planarization process and the second planarization process together enable the thickness of the dielectric layer 220 to meet the process requirements.
In one embodiment, the time of the first planarization process is longer than the time of the second planarization process. Specifically, the time of the second planarization process is between 10s and 30s, such as 20 s.
S6: as shown in fig. 4f, a protective film layer 230 is formed on the copper interconnect structure 250.
In one embodiment, the protection film 230 is a SIN/TEOS protection layer.
Because the copper hillocks of the copper in the groove 210 are released in advance under the heat effect of the rapid thermal processing in step S4, and then are flattened by the second planarization process in step S5, the copper hillocks can be released and eliminated in advance, so that the severity of the copper hillocks caused by the heat in the subsequent protective film 230 forming process is greatly reduced, and even the occurrence of the copper hillocks can be completely avoided, as shown in fig. 4f, only very tiny copper hillocks 260 are formed, and the tiny copper hillocks 260 greatly reduce the possibility of the protective film 230 being split or pierced, as shown in fig. 5, compared with fig. 2, the number of the protective film being split or pierced by the copper hillocks to form perforations is greatly reduced, and even if there are perforations, the area of the perforations is greatly reduced, so that the protective film 230 can play a good role in isolating and protecting the copper, thereby preventing the risk of copper diffusing out through the protective film 230 in the subsequent processes, as shown in fig. 6, compared to fig. 3, since there is substantially no copper diffusion, the rapid thermal process of step S4 and the second planarization process of step S5 are added before the process of forming the protective film, so that the copper hillocks can be released in advance and eliminated, thereby avoiding the occurrence of copper hillocks caused by the process of forming the protective film and causing serious product reliability problems. And the process is simple, has no influence on the original process, is low in cost and is easy to realize.
In one embodiment, the temperature of the rapid thermal processing in step S4 is higher than the temperature of the protective film 230 forming process in step S6, so that the cu hillock is sufficiently advanced in the rapid thermal processing in step S4. In one embodiment, the temperature of the process of forming the protective film 230 in step S6 is 350 degrees celsius, and the temperature of the rapid thermal processing in step S4 is 400 degrees celsius.
The specific numbers in the above embodiments may have a deviation, and in one embodiment, the deviation is 20%, preferably, the deviation is 10%, and more preferably, the deviation is 5%.
As mentioned above, the method for improving copper hillocks in copper interconnection process of the invention can be applied to copper interconnection process of copper via and copper metal layer.
In one embodiment, the recess 210 is a through silicon via, which is used to realize the connection between the logic wafer and the pixel wafer. With the emergence of emerging fields such as the internet of things/artificial intelligence, the importance of a CMOS Image Sensor (CIS) is increasing day by day. The Stacked CMOS Image Sensor (UTS CIS) can be manufactured by separating a logic wafer and a pixel wafer, and then by combining an upper and a lower stacking and bonding processes, the area ratio of a pixel region can be greatly increased, which is a new favorite in the subminiature smart terminal chip market. In two silicon chips of the stack CIS, one logic wafer mainly has the functions of a logic function circuit, a time sequence circuit, a storage unit and the like of the CIS; and the other pixel wafer mainly has the functions of providing a pixel unit of the CIS, a photodiode and the like. Through-silicon-via (TSV) is the most popular connection technology currently used, and copper in the TSV is also a critical wire module in the stacked CIS wafer. However, the copper hillocks (hillocks) are easily formed by the existing silicon through hole copper filling manufacturing process, which causes poor back coverage, and the method for improving the copper hillocks in the copper interconnection process can eliminate and reduce the copper hillocks of copper in the silicon through holes, and is of great importance for ensuring the performance of the UTS image sensor chip.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for improving copper hillocks in a copper interconnect process, comprising:
s1: forming a groove of the semiconductor device for forming a copper interconnection structure, wherein a dielectric layer is filled around the groove;
s2: forming a copper layer, wherein the copper layer fills the groove and covers the surface of the dielectric layer;
s3: carrying out a first planarization process to remove copper outside the groove;
s4: carrying out a rapid thermal treatment process to form copper hillocks on the surface of the copper;
s5: carrying out a second planarization process to remove the copper hillocks and form a copper interconnection structure; and
s6: a protective film layer is formed over the copper interconnect structure.
2. The method of claim 1, wherein the recess is a recess for forming a copper via.
3. The method of claim 1, wherein the recess is a recess for forming a copper metal layer.
4. The method of claim 1, further comprising forming a barrier layer on the surface of the recess and then forming a seed layer between step S2.
5. The method of claim 1, wherein the first planarization process and the second planarization process together enable a thickness of the dielectric layer to meet process requirements.
6. The method of claim 1, wherein the time of the first planarization process is longer than the time of the second planarization process.
7. The method of claim 6, wherein the time for the second planarization process is between 10s and 30 s.
8. The method of claim 1, wherein the temperature of the rapid thermal processing in step S4 is higher than the temperature of the protective film forming process in step S6.
9. The method of claim 8, wherein the temperature of the passivation layer forming process in step S6 is 350 degrees Celsius, and the temperature of the rapid thermal processing process in step S4 is 400 degrees Celsius.
10. The method of claim 1, wherein the recess is a through silicon via.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010992783.1A CN112201616A (en) | 2020-09-21 | 2020-09-21 | Method for improving copper hillock in copper interconnection process |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010992783.1A CN112201616A (en) | 2020-09-21 | 2020-09-21 | Method for improving copper hillock in copper interconnection process |
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| CN112201616A true CN112201616A (en) | 2021-01-08 |
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|---|---|---|---|---|
| TW457683B (en) * | 2000-10-05 | 2001-10-01 | Taiwan Semiconductor Mfg | Cu damascene processes preventing hillock on the surface |
| US20030008494A1 (en) * | 2001-07-03 | 2003-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-step planarizing method for forming a patterned thermally extrudable material layer |
| US20050085066A1 (en) * | 2003-10-16 | 2005-04-21 | Taiwan Semicondutor Manufacturing Co. | Novel method to reduce Rs pattern dependence effect |
| TW200701368A (en) * | 2005-06-29 | 2007-01-01 | Semiconductor Mfg Int Shanghai | Method of Cu interconnect for reducing stress migration |
| TWI292215B (en) * | 2002-06-25 | 2008-01-01 | Taiwan Semiconductor Mfg | |
| CN102339786A (en) * | 2010-07-16 | 2012-02-01 | 中芯国际集成电路制造(上海)有限公司 | Method for processing copper-plated layers in trenches |
| CN104795355A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Silicon through hole structure manufacturing method |
| CN105575828A (en) * | 2014-10-16 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN108630595A (en) * | 2017-03-16 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | The forming method of silicon hole |
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2020
- 2020-09-21 CN CN202010992783.1A patent/CN112201616A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW457683B (en) * | 2000-10-05 | 2001-10-01 | Taiwan Semiconductor Mfg | Cu damascene processes preventing hillock on the surface |
| US20030008494A1 (en) * | 2001-07-03 | 2003-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-step planarizing method for forming a patterned thermally extrudable material layer |
| TWI292215B (en) * | 2002-06-25 | 2008-01-01 | Taiwan Semiconductor Mfg | |
| US20050085066A1 (en) * | 2003-10-16 | 2005-04-21 | Taiwan Semicondutor Manufacturing Co. | Novel method to reduce Rs pattern dependence effect |
| TW200701368A (en) * | 2005-06-29 | 2007-01-01 | Semiconductor Mfg Int Shanghai | Method of Cu interconnect for reducing stress migration |
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Application publication date: 20210108 |