TWI292215B - - Google Patents

Description

^92215 V. INSTRUCTION DESCRIPTION G) FIELD OF THE INVENTION The present invention relates to a method of fabricating a copper damascene structure in a semiconductor process, particularly a thermal tempering and chemical mechanical polishing process to reduce the appearance of hills on the upper surface of the surface mosaic structure The method of bulging. Invented by the ULSI (the ULSI wafers and the continuous inch, the film, the design of the semiconductor (dama continuation: semiconductor industry) design specifications on a specific area to narrow down these components, and then the transfer of the great Difficult industry bets on the reduction of scene proc while the industry is developing rapidly. After entering the grid, high-density integrated electrical domains will define the number of electronic connection structures. However, the degree of lithography resolution is limited. All of them lead to difficulties in the making. And, in order to effectively develop and use a large number of human and spiritual ess), the design trend of the process and the ultra-large integrated circuit circuit is further improved, so that millions of components are produced. Body circuit scale, exposure focus misuse all kinds of components and lines to solve the above problems, in the inlay process, in order to be able to yield in the lithography products. For the traditional metal wire assembly +, good conductivity and cheaper, 5, 'aluminum metal material has a product or (four), is often into: generation;; the process requires any sinking, When considering the wire material of the semiconductor component. However, the structure has also encountered a lot of difficulties. 幵 The use of aluminum as a connection is easy and complete, such as in high-temperature environments, Shaoyuan produces "spike phenomenon", and; ==7 wide. ", and the line of contact is not good. In addition, when the fifth line of the aluminum wire 1292215 V, the invention description (2) ^ inch k with the shrinking of the piece, due to the "electro-migration", each easy to make the aluminum wire structure road. In the semiconductor industry of the 刖, it is often referred to in the copper metal, to replace the value of the first 々 々 ® ® 且 且 且 且 且 且 且 且 且 且 且 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电Step. First, the process is dielectric (contact upper surface. The junction is formed in a resistive substrate 50 and a chemical process is used to form a first view of the middle layer. This figure forms a dielectric layer 52. The layer 52 defines the h ο 1 e ) The opening is along the dielectric barrier 5 4 to prevent it. Subsequently, a bond is deposited (electr copper layer 58 in copper crystals showing a conventional copper damascene structure on the semiconductor substrate 50, and using lithography such as trenches, contact windows to expose a portion of the semiconductor substrate 5 〇 layer 52 and part of the semiconductor substrate 5 上 on the subsequent deposition of copper atoms diffuse to the semi-conductive copper seed layer 56 on the surface of the barrier layer 54, ical chemical plating; ECP) And filling in the above opening, and then referring to the second figure, performing a chemical mechanical polishing (CMP) to remove a portion of the copper layer 58, the copper seed layer 56 and the barrier located on the upper surface of the semiconductor substrate 50. Layer 54' defines a copper damascene structure 60 located in dielectric layer 52. Subsequently, an inter-metal dielectric (IMD) 62 can be deposited over the dielectric layer 52 and the copper damascene structure 60, and the process described above is repeated, and is determined » Page 6 1292215

The metal wiring pattern in this layer is defined. However, it is worth noting that, as shown in the third figure, when a chemical vapor deposition (CVD) process is performed to form the inter-metal dielectric layer 62, the upper surface tends to produce hill-like protrusions 64. The flatness of the inter-metal dielectric layer 62 is severely damaged. The main reason for causing the metal interlayer dielectric layer 62 to generate the hill-like protrusions 64 is due to the copper atoms in the copper damascene structure 60, and the growth and extrusion of crystal grains are carried out in a high temperature environment of a chemical vapor deposition process. caused. In addition, due to the chemical plating process of depositing the copper layer 58 or the subsequent chemical mechanical honing process, it is generally carried out in a room temperature environment, in the process of making the copper mosaic structure 60, copper. The atoms do not reach the most stable state, but exhibit material properties with uneven stress distribution. As a result, the temperature environment in which the inter-metal dielectric layer 6 2 is deposited will cause the copper atoms to undergo grain growth and disperse excessively concentrated structural stress, and an irregular mountain is generated on the upper surface of the copper damascene structure 60. The hill ridges 66, which in turn cause the pattern of the mountain ridges 66 to pass upward, cause the same surface defects in the surface of the inter-metal dielectric layer 62. In addition to the difficulty in controlling the accuracy of the process, such results can significantly reduce the yield of the manufactured product. SUMMARY OF THE INVENTION OBJECTS AND SUMMARY: It is an object of the present invention to provide a method of preventing the formation of protrusions on the upper surface of a copper damascene structure. A further object of the present invention is to provide a surface enhancement of the copper-encrusted structure.

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V. Description of invention (4) Method of candidization. law. The first of the present invention has a semiconductor bump, a surface, and an interlayer interface along the opening layer after the opening of the mechanical mechanism. A further object of the present invention is to provide a method for planarizing the surface. , a copper damascene structure on a conductor substrate in which a dielectric layer is formed on the upper surface of the dielectric layer, and then a deposition process is performed to form copper in the opening pattern. The first step of the copper layer on the upper surface of the barrier layer, the fire procedure to reduce the structure of the copper layer should "generate a hill-like bulge. Subsequently, the mechanical grinding process to remove the hill-like appearance and expose Part of the semiconductor substrate is in the opening pattern. Finally, the metal material, the barrier layer and the copper damascene structure are deposited. The layer of the inter-layer dielectric layer is first deposited, and the opening pattern is deposited. The method comprises: in the semiconductor substrate, the copper layer and the copper layer of the copper layer are partially embedded in the copper layer to have a flat electric layer in a semi-adhesive manner, and the surface is covered. - surface - a chemical barrier layer, the structure is on the semiconductor bottom of the surface of the invention. The invention discloses a method for fabricating a copper mosaic structure in a semi-method. First, a total of <10. Single crystal stone: the bottom of the material is the same as above. 'Other types of semiconductor materials, such as gallium arsenide, germanium or silicon on the insulating layer. On insulator, SOI) can be used as the conductor substrate. In addition, due to the characteristics of the surface of the semiconductor substrate, the present invention

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5. The invention description (5) does not cause special denier / <111>. Then come, shirt day °, you can also choose <11 0> or electric layer 1〇2 with its crystal orientation. In particular, a dielectric substrate 10 can be formed on the semiconductor substrate. First, before the formation of the dielectric layer 102, the semiconductor device 'or the circuit diagram smashes the various active components required for the passive element, the passive meta-oxide, and the material of the nitride H: i dielectric layer 102. Optional. The material of the compound or low dielectric value (low κ value) is constructed by a microlithography process on the dielectric layer 102 to expose the semiconductor substrate 10. Upper surface. Wherein UJ: in the form of a trench or a contact hole in the form of a trench or a contact hole ί n m1. 4 on the upper surface of the dielectric layer 102, along the side of the opening pattern / the exposed semiconductor bottom The surface of the material 100 is covered to prevent diffusion of the subsequently deposited copper layer from the interface of the dielectric layer 102 or the semiconductor substrate 100. In general, tantalum (Ta) or nitride (TaN) materials can be selected for use as the barrier layer 此处04 herein. Wherein, the sputtering process may be performed first, a button layer is deposited on the upper surface of the opening pattern, and the semiconductor substrate 1〇〇 is placed in an environment of N2 or NH3, and the desired nitride button layer is formed by high temperature treatment. Alternatively, by bombarding the button metal with plasma ions, and introducing argon gas and nitrogen gas, the button atoms splashed by bombardment may react with the nitrogen atoms formed by the dissociation reaction. Forming a nitride button and depositing on the opening pattern and the surface 0 of the semiconductor substrate 1 在 after the barrier layer 104 is formed, and then forming a Cu seeding layer 16 on the surface of the barrier layer 104 . In general, you can use well-known

Page 9 1292215 V. Related Art of Invention (6) For example, a physical vapor deposition method (p h y s i c a 1 v a ρ 〇 r deposi tion; PVD), a sputtering method, or the like is used to deposit a copper seed layer 1 〇 6. Next, the semiconductor substrate 1 can be immersed in a copper sulfate solution to perform an electroless plating (Electrical Chemical Plating; ECP) reaction to form a copper layer 108 on the surface of the copper seed layer 1〇6, and filled in the above In the opening pattern. Wherein, in the electroplating process, the copper seed layer 106 is electrically connected to the cathode of the power source, and the copper ions in the copper sulfate solution are 'reduced and deposited on the surface of the copper seed layer 106, thereby covering the whole Above the semiconductor substrate 100. Next, as shown in the fifth figure, a first chemical mechanical polishing method is performed to remove a portion of the copper layer 108. It is worth noting that this first chemical mechanical polishing process stops after exposing the upper surface of the barrier layer 104. Then, the semiconductor substrate 1 is placed on a hot plate or a heating furnace to perform a thermal tempering process to reduce the structural stress of the deposited copper layer 108 and to make the copper atom Has a more stable characteristics. In general, the thermal tempering procedure herein is carried out in an environment at a temperature of about 3 〇 42 to 42 5 ° C for about 30 to 60 minutes. It is worth noting that the excessively concentrated junction & stress in the copper layer 108 due to the thermal tempering process will result in a hill-like projection 11〇 on the upper surface of the copper layer 108 (as shown in Fig. 6). After the thermal tempering process of the element, as shown in the seventh figure, a second chemical mechanical polishing process is performed on the semiconductor substrate 100 to remove the hill-like protrusion 110' located on the upper surface of the semiconductor substrate 100. The copper layer 1 〇 8 and a portion of the barrier layer 104 ′ define the copper damascene structure 112 in the open case described above.

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No. 1292215 five 'invention description (7) Finally, please refer to the eighth figure, forming a metal interlayer dielectric layer 于4 on the partial dielectric layer 102, part of the barrier layer 丨〇4 and the upper surface of the copper damascene structure 丨丨2 Where 'this inter-metal dielectric layer 114 has a flat surface. By the method of the present invention, the property of the last name ..θ in the copper layer can be used in the thermal tempering procedure before the formation of the copper damascene structure, and the ::: structural stress release is made to make it have a more stable inlay. The structure is in the opening pattern ί;; the second chemical mechanical grinding method to form a steel layer, and the copper mosaic structure and the back side except the hill-like protrusions and the upper surface of the partial barrier flat, to achieve the deposition of the metal layer The electrical layer has the purpose of increasing the I-rate yield. The present invention has been described with reference to the preferred embodiments of the present invention, and is not intended to limit the scope of the invention. Therefore, the modifications made within the scope of the patent application mentioned should be included.

Brief Description of the Drawings Brief Description of the Drawings: The above description and the advantages of the invention will be readily understood by the following detailed description in conjunction with the accompanying drawings in which: FIG. A step of depositing a copper layer on a semiconductor substrate according to current industry techniques is shown; the second figure is a cross-sectional view of the semiconductor wafer showing the steps of removing a portion of the copper layer using a chemical mechanical polishing process according to current industry techniques; A cross-sectional view of a semiconductor wafer, according to the current industry technology: after the hill-like protrusion is generated on the upper surface of the copper damascene structure, the dielectric layer between the metal layers is successively deposited on the semiconductor substrate; A cross-sectional view of a wafer showing the step of forming a copper layer on the upper surface of the semiconductor substrate and filling along the surface of the opening in accordance with the present invention; and the fifth drawing is a cross-sectional view of the semiconductor wafer showing the first chemical mechanical polishing in accordance with the present invention. The sixth step is a cross-sectional view of the semiconductor wafer showing the occurrence of a hill-like protrusion on the upper surface of the copper layer according to the present invention. Figure 7 is a cross-sectional view of the semiconductor wafer showing the second chemical mechanical polishing process to form a copper damascene structure in the opening pattern in accordance with the present invention; and the eighth figure is a cross-sectional view of the semiconductor wafer, the display is based on The present invention forms the step of forming a metal interlayer dielectric layer. Chart number comparison table:

Page 12 1292215 Schematic description of semiconductor substrate 50 barrier layer 5 4 copper layer 5 8 metal interlayer dielectric layer 6 2 irregular hill bumps 6 6 dielectric layer 1 0 2 copper seed layer 1 0 6 Hill-like protrusions 110 Inter-metal dielectric layer 11 4 Dielectric layer 5 2 Copper seed layer 5 6 Copper mosaic structure 6 0 Hill-like projections 6 4 Semiconductor substrate 1 0 0 Barrier layer 1 0 4 Copper layer 1 0 8 copper mosaic structure 11 2

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Claims (1)

1292215 VI. Patent Application No. 1 · A method for fabricating a copper damascene structure, first forming a dielectric layer on a semiconductor substrate and having an opening pattern in the dielectric layer, the method comprising at least the following steps: forming a barrier layer The upper surface of the dielectric layer is covered along the surface of the opening pattern; a copper layer is deposited on the barrier layer and filled in the opening pattern; and a first chemical mechanical polishing method is performed to remove the barrier layer a portion of the copper layer on the upper surface of the layer; performing a thermal tempering process on the semiconductor substrate; and performing a second chemical mechanical polishing process on the semiconductor substrate to remove the portion of the barrier layer on the upper surface of the dielectric layer The layer and the copper layer define a copper damascene structure in the opening pattern. 2. For the method and method of claim 1, wherein the barrier layer is a nitride layer. 3. The method of claim 1, wherein the copper layer is formed by electroless plating. 4. The method of claim 1, wherein the thermal tempering step is performed in an environment of a temperature of 300 to 425 ° C for about 30 to 60 minutes. 5. The method of claim 1, wherein the above thermal tempering Page 14 1292215 VI. The scope of the application for patents can be carried out by using a heating plate or a heating furnace tube. The method has a splitting surface covering the sinking surface and reducing the interfacial stress on the surface of the mountain. Forming a hill-like protrusion on the upper surface of the dielectric layer, first forming a dielectric layer on the semiconductor substrate, and patterning the opening in the dielectric layer, the method comprising at least the following steps: forming a barrier layer on the dielectric layer a surface, along the opening pattern, layered on the barrier layer, and filled in the opening pattern; performing a first chemical mechanical polishing method to remove a portion of the copper layer located on the barrier layer; . The semiconductor substrate is subjected to a thermal tempering process to reduce the junction of the copper layer > wherein a hill-like protrusion is formed on the surface of the copper layer; 4 the semiconductor substrate is subjected to a second chemical mechanical polishing process to shift a moire-like protrusion and a portion of the barrier layer, and exposing a portion of the dielectric layer, the copper-embedded structure is in the opening pattern; and 2 inter-metal dielectric layers on the dielectric layer and covering the sodium inlay The surface of the metal interlayer has a flat upper surface. Nitrogen 7 Λ 请 'Please refer to the method of item 6 of the patent scope, # The above mentioned barriers are widely 8. If the patent application range is 6th, it is formed by electroless plating. The method of the above, wherein the copper layer is Page 15 1292215 VI. Application Patent Range 9. The method of claim 6, wherein the above thermal tempering process is performed in an environment of temperature 3 0 0 to 4 2 5 ° C, about 3 0~ Completed in 60 minutes. The method of claim 6, wherein the above thermal tempering step can be carried out using a heating plate or a heating furnace tube. Page 16