TW541659B - Method of fabricating contact plug - Google Patents
Method of fabricating contact plug Download PDFInfo
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- TW541659B TW541659B TW091107694A TW91107694A TW541659B TW 541659 B TW541659 B TW 541659B TW 091107694 A TW091107694 A TW 091107694A TW 91107694 A TW91107694 A TW 91107694A TW 541659 B TW541659 B TW 541659B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 143
- 239000002184 metal Substances 0.000 claims abstract description 143
- 230000004888 barrier function Effects 0.000 claims abstract description 109
- 239000003870 refractory metal Substances 0.000 claims abstract description 72
- 150000004767 nitrides Chemical class 0.000 claims abstract description 65
- 238000000034 method Methods 0.000 claims abstract description 61
- 238000009832 plasma treatment Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 42
- 229910052757 nitrogen Inorganic materials 0.000 claims description 21
- 239000007789 gas Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 12
- 229910052721 tungsten Inorganic materials 0.000 claims description 12
- 239000010937 tungsten Substances 0.000 claims description 12
- 239000010936 titanium Substances 0.000 claims description 11
- 238000004140 cleaning Methods 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 238000011282 treatment Methods 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000004575 stone Substances 0.000 claims description 3
- -1 inscription Inorganic materials 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 2
- 229910045601 alloy Inorganic materials 0.000 claims 2
- 239000000956 alloy Substances 0.000 claims 2
- 229910052802 copper Inorganic materials 0.000 claims 2
- 239000010949 copper Substances 0.000 claims 2
- 229910052762 osmium Inorganic materials 0.000 claims 1
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 claims 1
- 230000008569 process Effects 0.000 description 20
- 238000013508 migration Methods 0.000 description 12
- 230000005012 migration Effects 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000012535 impurity Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910021645 metal ion Inorganic materials 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 229910052778 Plutonium Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000009970 fire resistant effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910017464 nitrogen compound Inorganic materials 0.000 description 1
- 150000002830 nitrogen compounds Chemical class 0.000 description 1
- 230000000414 obstructive effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- NFHFRUOZVGFOOS-UHFFFAOYSA-N palladium;triphenylphosphane Chemical compound [Pd].C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1 NFHFRUOZVGFOOS-UHFFFAOYSA-N 0.000 description 1
- XNGIFLGASWRNHJ-UHFFFAOYSA-L phthalate(2-) Chemical compound [O-]C(=O)C1=CC=CC=C1C([O-])=O XNGIFLGASWRNHJ-UHFFFAOYSA-L 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- OYEHPCDNVJXUIW-UHFFFAOYSA-N plutonium atom Chemical compound [Pu] OYEHPCDNVJXUIW-UHFFFAOYSA-N 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
541659 _案號91107694_年月日__ 五、發明說明（1) 本發明是有關於一種半導體，且特別是有關於一種製 造接觸插塞之方法。 積體電路係製造為如電晶體之各種裝置之組合，且許 多晶片係包含於單一晶圓上。在製造積體電路之製程中， 在如電晶體之各別裝置已製造於矽基底中之後，其必需連 接在一起以執行所需之電路功能。此連接製程一般稱為" 金屬4匕”，且係利用各種不同微影與沉積技術而進行。 接觸插塞係形成以在下層裝置與上層内連接導線間形 成固態電子連接。接觸插塞之製造一般牽涉到形成開口於 介電層，且此開口係由如鋁或鎢等金屬層所填滿或插入。 然而，接觸插塞之鋁或鎢離子可經由摻雜區而遷移入矽基 底中，而造成對基底之短路。為將短路最小化，·某些製程 在沉積鋁或鎢之前會沉積阻障層。阻障材質之一是T i N。 雖然T i N具良好阻障能力，其必需足夠厚以有效當成阻障 層。甚至，當積體電路裝置定義得更微小，接觸插塞之直 徑變d、且更關鍵。因此，厚T i N阻障金屬層在高積體電路 中係不想要的。可發現在T i N中之氮改善阻障功能，也就 是，當於T i N中之氮含量增加，阻障效應也增加。方法之 一是佈植氮至T i N中以增加阻障效應且減少T i N阻障金屬層 之厚度以符合高整合結構需求。佈植氮至T i N之一個方法 是在氫氣之氣體中進行氮電漿處理。現在，有可能形成較 薄之T i N阻障金屬層以符合高積體電路需求。 另一種普遍使用之阻障金屬層是金屬有機CVD鈦 (MOC VD-Ti ) cMOCVD-Ti材質包含如碳與氧之雜質，因而 Μ 0 C V D - T i材質之阻抗值甚高。為減少阻抗值，方法之一是541659 _Case No. 91107694_ Year Month__ V. Description of the Invention (1) The present invention relates to a semiconductor, and in particular to a method for manufacturing a contact plug. Integrated circuits are manufactured as a combination of various devices such as transistors, and many wafers are contained on a single wafer. In the process of manufacturing integrated circuits, after individual devices such as transistors have been fabricated in a silicon substrate, they must be connected together to perform the required circuit functions. This connection process is generally called " Metal 4 Dagger " and is performed using a variety of different lithography and deposition techniques. Contact plugs are formed to form a solid-state electronic connection between a lower-layer device and an upper connecting wire. Manufacturing generally involves forming an opening in the dielectric layer, and the opening is filled or inserted by a metal layer such as aluminum or tungsten. However, aluminum or tungsten ions that contact the plug can migrate into the silicon substrate through the doped region In order to minimize the short circuit, some processes will deposit a barrier layer before depositing aluminum or tungsten. One of the barrier materials is T i N. Although T i N has good barrier capabilities, It must be thick enough to effectively act as a barrier layer. Even when the integrated circuit device is defined smaller, the diameter of the contact plug becomes d and more critical. Therefore, a thick T i N barrier metal layer is used in high-integrated circuit Undesired in the middle system. It can be found that nitrogen in T i N improves the barrier function, that is, as the nitrogen content in T i N increases, the barrier effect also increases. One method is to plant nitrogen to T i N to increase barrier effect and reduce T i N resistance The thickness of the barrier metal layer meets the requirements of a highly integrated structure. One method of implanting nitrogen to T i N is to perform a nitrogen plasma treatment in a hydrogen gas. Now, it is possible to form a thinner T i N barrier metal layer to Meets the requirements of high-integration circuit. Another commonly used barrier metal layer is metal organic CVD titanium (MOC VD-Ti). CMOCVD-Ti material contains impurities such as carbon and oxygen, so the resistance value of M 0 CVD-T i material Very high. One way to reduce the impedance value is
7120twfl . ptd 第 7 頁 541659 _案號 91107694_年月日__ 五、發明說明（2) 利用包括氮氣或氨之電漿氣體來處理阻障層以移除這些雜 質。然而，接續電聚氣體處理而來的，Μ 0 C V D - T i厚度本質 上減少，因而，所形成之處理後MOCVD-T i層具有相當低阻 抗值，然而，其厚度不足以有效地當成阻障層。因而，方 法之一是沉積第二MOCVD-Ti層，而接著電漿氣體處理以移 除雜質而形成所需厚度之阻障金屬層以有效地當成阻障 層。 接觸之效應係被介於阻障金屬層與基底中之摻雜區間 之接觸阻抗值所限制。此接觸阻抗值在正摻雜區中係大於 負摻雜區。接觸阻抗值在CMOS(互補性金氧矽）技術中係特 別重要，其包括具有正摻雜區與負摻雜區之阻障金屬層。 減少接觸阻抗值的方法之一是沉積共形（c ο n f 〇 r m a 1 )对火 (refractory)金屬層於開口中，接著利用熱處理以退火該 耐火金屬層以啟動金屬與矽間之反應而形成矽金屬化合 物。因為矽金屬化合物具有低阻抗值，因而接觸阻抗值可 ‘減少。然而，上述接觸插塞方法之一個問題是，在熱處 理後所得之阻障層提供介電層與鎢層間之不良附著力。 申請人發現在熱處理中，從周圍環境來之氧會與阻障 金屬反應而形成氧化物膜於接觸阻障層之表面上。所形成 之氧化物之問題是，其具有約等於用以填滿接觸開口之鎢 層之z e t a值。因為阻障層對鐫層之相似z e t a值，其會互相 排斥。因而，形成於阻障層上之氧化物膜使得鎢層無法附 著於阻障層之表面上。因而，空隙係形成於導體層中，導 致電子遷移失誤。因為氧化物膜由於zeta值而具不良附著 能力，介電層與接觸中之鎢層間之附著不良。因為如鎢之7120twfl. Ptd page 7 541659 _ case number 91107694_ year month__ V. Description of the invention (2) The plasma barrier gas including nitrogen or ammonia is used to treat the barrier layer to remove these impurities. However, the thickness of M 0 CVD-T i following the treatment with electropolymeric gas is substantially reduced. Therefore, the formed MOCVD-T i layer has a relatively low resistance value. However, its thickness is not sufficient to effectively act as a resistance. Barrier. Therefore, one method is to deposit a second MOCVD-Ti layer, followed by plasma gas treatment to remove impurities to form a barrier metal layer of a desired thickness to effectively function as a barrier layer. The effect of contact is limited by the value of the contact resistance between the barrier metal layer and the doped interval in the substrate. This contact resistance value is larger in the positively doped region than in the negatively doped region. The contact resistance value is particularly important in CMOS (Complementary Metal Oxide Silicon) technology, which includes a barrier metal layer with a positively doped region and a negatively doped region. One method to reduce the contact resistance value is to deposit a conformal (ref tory) metal layer in the opening, and then use heat treatment to anneal the refractory metal layer to initiate the reaction between the metal and silicon to form Silicon metal compounds. Because the silicon metal compound has a low resistance value, the contact resistance value can be reduced. However, a problem with the above-mentioned contact plug method is that the barrier layer obtained after the heat treatment provides poor adhesion between the dielectric layer and the tungsten layer. The applicant found that during the heat treatment, oxygen from the surrounding environment would react with the barrier metal to form an oxide film on the surface contacting the barrier layer. The problem with the formed oxide is that it has a value of z e t a that is approximately equal to the tungsten layer used to fill the contact openings. Because of the similar z e t a values of the barrier layer to the plutonium layer, they will repel each other. Therefore, the oxide film formed on the barrier layer prevents the tungsten layer from being attached to the surface of the barrier layer. As a result, voids are formed in the conductor layer, resulting in erroneous electron migration. Because the oxide film has poor adhesion due to the zeta value, the adhesion between the dielectric layer and the tungsten layer in contact is poor. Because of tungsten
71201 w f 1 . p t d 第8頁 541659 _案號91107694_年月日__ 五、發明說明（3) 導體層與介電層間存在著高熱擴張係數差異，在日後後續 處理中，因為熱擴張所導致之熱應力將變大。因而，傳統 阻障層因無法抵抗熱擴張而斷裂。因而，由於阻障金屬層 結構被破壞，其促進從導體層來之如鋁或鎢原子等離子或 原子擴散至基底中，造成裝置短路。因為導體層之晶格結 構被破壞，其導致由於電子遷移而形成空隙，而導致裝置 之失誤。 由於上述之問題，本發明提供解決上述問題之方法。 有鑑於此，本發明的主要目的就是在提供一種製造接 觸插塞方法以限制在接觸插塞中之導電材質之電子遷移。 本發明提供形成接觸插塞以減少接觸阻抗值之改善方 法。因而，R C延遲時間可上減少。因而，裝置之操作速度 可本質上增加。 本發明提供形成接觸阻障金屬層之方法以改善介電層 與該導電層間之附著度，使得避免阻障金屬層之斷裂或破 裂。因而，裝置之可靠性增加。 本發明提供形成接觸阻障金屬層之方法以改善導電材 質之空隙填滿能力，並增加介電層與該導電層間之附著度 能力，可避免空隙之產生。因而可限制由電子遷移所造成 之裝置失誤，而增加半導體裝置之可靠性。 根據較佳實施例之一，本發明提供製造接觸插塞之改 善方法。係提供具有一導電區之半導體基底，介電層係形 成於整體基底上；蝕刻該介電層以形成接觸開口，其中該 導電區係露出於該接觸開口内。利用預清洗製程以移除殘 餘物，否則將增加接觸阻抗值。接觸開口係覆蓋著第一耐71201 wf 1. Ptd Page 8 541659 _ Case No. 91107694_ year month day__ V. Description of the invention (3) There is a high thermal expansion coefficient difference between the conductor layer and the dielectric layer. In the subsequent processing, it will be caused by thermal expansion. The thermal stress will increase. Therefore, the conventional barrier layer is broken because it cannot resist thermal expansion. Therefore, because the structure of the barrier metal layer is destroyed, it promotes the diffusion of ions or atoms such as aluminum or tungsten atoms from the conductor layer into the substrate, resulting in a short circuit of the device. Because the lattice structure of the conductor layer is destroyed, it leads to the formation of voids due to electron migration, which leads to device failure. Due to the above problems, the present invention provides a method for solving the above problems. In view of this, the main object of the present invention is to provide a method for manufacturing a contact plug to limit the electron migration of a conductive material in the contact plug. The present invention provides an improved method for forming a contact plug to reduce a contact resistance value. Therefore, the R C delay time can be reduced. Thus, the operating speed of the device can be substantially increased. The present invention provides a method for forming a contact barrier metal layer to improve the adhesion between the dielectric layer and the conductive layer, so as to avoid cracking or breaking of the barrier metal layer. Therefore, the reliability of the device is increased. The invention provides a method for forming a contact barrier metal layer to improve the gap filling ability of a conductive material, and to increase the adhesion ability between a dielectric layer and the conductive layer, so as to avoid the generation of gaps. It is therefore possible to limit device errors caused by electron migration and increase the reliability of semiconductor devices. According to one of the preferred embodiments, the present invention provides an improved method for manufacturing a contact plug. A semiconductor substrate having a conductive region is provided, and a dielectric layer is formed on the entire substrate; the dielectric layer is etched to form a contact opening, wherein the conductive region is exposed in the contact opening. Use a pre-cleaning process to remove residues that would otherwise increase the contact resistance value. The contact opening is covered with first resistance
71201 w f 1 . p t d 第9頁 541659 _案號 91107694_年月日__ 五、發明說明（4) 火金屬層。接著，沉積第二耐火金屬層於該第一财火金屬 層上；接著，進行一第一電漿處理以將該第二耐火金屬層 轉換成一第一金屬氮化物阻障層。該第一電漿處理較好包 括：包含氮氣與氫氣之電漿氣體。進行一熱處理以觸發該 第一而寸火金屬層與該導電區中之該矽間之反應以形成一金 屬矽4匕物於該導電區上，而減少接觸阻抗值。接著，第三 耐火金屬層係沉積於該第一金屬氮化物阻障層上，且利用 相似於包含氮氣與氫氣之電漿氣體而處理，以從該第三耐 火金屬層移除雜質，並將該第三耐火金屬層轉換成第二金 屬氮4匕物阻障層；以及接著，沉積導體層以填滿該接觸開 導屬可 該金上發一質 觸成本 來形而 理以因 處應 ， 熱反值 行之抗 進間阻 以層低 法屬有 方金具 之火物 明耐化 發一碎 本第屬 用該金 利與該 ，碎為 解該因 了之。 要中物 區化 電碎 。成 度形 速著 作接 操並 之理 置處 裝熱 加行 增進 可以 上法 質方 本之 ，明 而發 因本 〇 用 值利 抗， 阻解 觸了 接要 少 減71201 w f 1. P t d p. 9 541659 _ case number 91107694 _ year month day __ 5. Description of the invention (4) Fire metal layer. Next, a second refractory metal layer is deposited on the first refractory metal layer; then, a first plasma treatment is performed to convert the second refractory metal layer into a first metal nitride barrier layer. The first plasma treatment preferably includes a plasma gas containing nitrogen and hydrogen. A heat treatment is performed to trigger a reaction between the first fire-resistant metal layer and the silicon in the conductive region to form a metal silicon substrate on the conductive region, thereby reducing the contact resistance value. Next, a third refractory metal layer is deposited on the first metal nitride barrier layer and treated with a plasma gas similar to nitrogen and hydrogen to remove impurities from the third refractory metal layer, and The third refractory metal layer is converted into a second metal nitrogen barrier layer; and then, a conductor layer is deposited to fill the contact encapsulation, which can be reasonably costly to the gold, The thermal resistance value of the resistance to the intervening resistance is lower than the level of the firearms with square gold fittings. It is a piece of material that uses the gold and the right, and the broken is the solution to the cause. To be neutralized and broken into pieces. The principle of speeding up and speeding up the operation and integration is to install heat and increase the bank. You can apply the method to the quality of the law. It is clear that the cost is used to resist the resistance, and the resistance is reduced.
屬導 金與 二層 第障 於阻 成物 形化 膜氮 物屬 化金 氧二 制第 限得 為使 係， 層上 障面 阻表 物之 化層 氛障 屬阻金物 二化 第II 填 隙氮 空屬 好金 良二 之第 層為 電因 導。 於度 利著 有附 以之 制間 限層 地電 效導 有與 可層 斥電 排介 之進 間促 層並 電滿 化 因， 排。層 有誤屬 會失金 不移火 將遷耐 間子一 其電第 ，免， 大避加 極地增 異效係 差有度 值而著 ta，附 zet: 之空間 層生層 電產電 導會導 與不與 層而層 障因電 阻，介 物斥為 為斷 因會 。不 免係 避層 效障 有阻 可物 也化 裂氮 斷屬 之金 層二 障第 阻與 物一 化第 氮 ’ 屬層 金屬 二金 第火 與耐 一 -第第It is a metal guide and the second layer of the barrier is formed by the barrier material. The nitrogen compound is the metal oxide of the second system. The limitation is to make the system. The barrier surface of the upper layer of the barrier layer is the metal barrier of the second barrier. Gap nitrogen is the second layer of Hao Jinliang II and is electrically conductive. By Yu Duli, there is a limited layer of ground electrical conductivity, and there is a layer between the layer and the layer to repel the electricity. The layer promotes the layer and the battery is full. If there is an error in the layer, it will lose gold and will not move the fire. It will be moved to the first place, so as to avoid the increase of the polar synergy effect. There is a degree value, with zet: The conductive and non-conductive layers are caused by electrical resistance, and the dielectrics are repelled by faults. It ’s inevitable that the avoidance layer is obstructive, but the material can also be broken. Nitrogen splitting is the second layer of barriers and the first layer of nitrogen.
7120t wf 1 . p t d 第10頁 541659 _案號91107694_年月日__ 五、發明說明（5) 裂或破裂，第一與第二金屬氮化物阻障層可有效地避免金 屬離子或原子擴張至介電層内部，而避免裝置之短路。因 為在接觸中之導電層之晶格結構未被破壞，且相鄰之第一 耐火金屬層，第一與第二金屬氮化物阻障層也未被破壞， 可避免因電子遷移所造成之空隙產生，因而可限制由電子 遷移所造成之裝置失誤。因而，裝置之可靠性可本質上增 力口 。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 標號說明： 1 00 :基底 102 : 導電區 104 : 介電層 1 0 6 : 光阻 1 0 8 : 接觸開口 110 :第一对火金屬層 112:第二耐火金屬層 1 1 4 :第一金屬氮化物阻障層 1 1 6 :金屬石夕化物薄膜 1 1 8 ··第三耐火金屬層 1 2 0 :第二金屬氮化物阻障層 1 2 5 :第一電漿處理 122 :導電金屬層 1 2 6 :熱處理7120t wf 1. Ptd page 10 541659 _ case number 91107694_ year month day __ 5. Description of the invention (5) cracking or cracking, the first and second metal nitride barrier layers can effectively avoid metal ions or atomic expansion To the inside of the dielectric layer to avoid shorting the device. Because the lattice structure of the conductive layer in contact is not damaged, and the adjacent first refractory metal layer, the first and second metal nitride barrier layers are also not damaged, and voids caused by electron migration can be avoided. This can limit device errors caused by electronic migration. Therefore, the reliability of the device can be substantially enhanced. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to describe in detail as follows: Reference number description: 1 00: substrate 102: conductive region 104: Dielectric layer 106: Photoresist 108: Contact opening 110: First pair of fire metal layers 112: Second refractory metal layer 1 1 4: First metal nitride barrier layer 1 1 6: Metal stone The oxide film 1 1 ··· The third refractory metal layer 1 2 0: the second metal nitride barrier layer 1 2 5: the first plasma treatment 122: the conductive metal layer 1 2 6: heat treatment
71 201 w f 1 . p t d 第11頁 541659 案號 91107694_年月日_ 五、發明說明 (6) 127 第 二 電 漿 處 理 1 50 接 觸 插 塞 200 基 底 202 導 電 區 204 介 電 層 208 接 觸 開 α 2 10 第 -- 而才 火 金 屬 層 2 14 多 層 金 屬 氮 化 物 阻障層 2 16 金 屬 矽 化 物 薄 膜 2 18 第 二 耐 火 金 屬 層 220 金 屬 氮 化 物 阻 障 層 222 導 電 金 屬 層 226 軌 處 理 227 電 漿 處 理 2 5 0 ： * 接 觸 插 塞 較佳 實施例 詳細參考本發明之較佳實施例，其範例係顯示於附圖 中。可能的話，相同參考符號係使用於圖示與描敘中以指 向相同或相似部份。 第1至9圖繪示根據本發明之第一較佳實施例之製造接 觸插塞步驟之剖面圖。 參考第1圖，係提供具有導電區102形成於其上之基底 100。由如S0P(spin-on-polymer)材質所組成之低介電常 數材質之介電層104係形成於基底100上。CMP製程係用以 移除多餘之介電層1 0 4以將介電層1 0 4平坦化來獲得如第171 201 wf 1. Ptd Page 11 541659 Case No. 91107694_Year_Year_V. Description of the invention (6) 127 Second plasma treatment 1 50 Contact plug 200 Substrate 202 Conductive region 204 Dielectric layer 208 10th-- And fire metal layer 2 14 Multi-layer metal nitride barrier layer 2 16 Metal silicide film 2 18 Second refractory metal layer 220 Metal nitride barrier layer 222 Conductive metal layer 226 Rail treatment 227 Plasma treatment 2 50: * The preferred embodiment of the contact plug is described in detail with reference to the preferred embodiment of the present invention, an example of which is shown in the accompanying drawings. Where possible, the same reference symbols are used in the drawings and descriptions to refer to the same or similar parts. Figures 1 to 9 are sectional views showing the steps of manufacturing a contact plug according to the first preferred embodiment of the present invention. Referring to FIG. 1, a substrate 100 having a conductive region 102 formed thereon is provided. A dielectric layer 104 made of a low dielectric constant material, such as a spin-on-polymer (SOP) material, is formed on the substrate 100. The CMP process is used to remove the excess dielectric layer 104 to planarize the dielectric layer 104 to obtain
7120twfl . ptd 第12頁 541659 __m , 91107694__^ 月 日 修正_ 五、發明說明（7) 圖所示之平坦表面。 參考第2圖’光阻層係沉積於介電層丨〇 4上。光阻層係 整形或圖樣化以形成如第2圖所示之接觸開口蝕刻罩幕 1 0 6。接著’接觸開口 1 〇 8被形成，其係利用接觸開口蝕刻 罩幕106露出之介電層1〇4直到導電區1〇2露出於接觸開口 1 0 8内。所用之敍刻製程係較好為高不等向性，且可能為 利用適當$聚氣體之反應離子蝕刻（R丨E )而進行。 參考第3圖’接著移除或剝落光阻1 0 6 ，此移除製程係 較好為利用氧電聚之乾餘刻製程或使用適當溶液之濕蝕刻 製程。預清洗步驟接著執行以從介電層丨〇4表面清洗殘餘 物’而更重要的是，從接觸開口之側壁與底部清洗殘餘 物1將增加接觸阻抗值。預清洗步驟包括濕蝕刻或乾 #刻製程二其中該預清洗步驟使用緩衝氧化劑。在乾蝕刻 製程中，最好使用由氬氣所形成之電漿氣體。薄層之第一 耐火金屬層1 1 0接著被形成並保角於介電層丨〇 4，接觸開口 1 0 8之側壁與底部上。第一耐火金屬層丨丨〇，比如，係由鈦 (T i )或组（T a )所形成。接著，第二耐火金屬層丨丨2係形成 於第一时火金屬層11〇上。第二耐火金屬層112係最好用 M0CVD方法沉積’其在約4 0 0〜4 5 0 °C之溫度下使用如 TDMAT(tetrakis〜dimethylamido-titanium)或 TDEAT(tetrakis-diethylamido - titanium)之前導物，且 車父佳厚度約1 2 0〜1 6 〇埃。第二财火金屬層1 1 2之材質係較好 由鈦或组組成。 參考第4圖’執行第一電漿處理125以移除附著於第二 而才火金屬層1 1 2之雜質，如碳或氧化物，接著，第二耐火7120twfl. Ptd Page 12 541659 __m, 91107694 __ ^ Month Day Revision_ V. Description of the invention (7) The flat surface shown in the figure. Referring to FIG. 2 ', a photoresist layer is deposited on the dielectric layer. The photoresist layer is shaped or patterned to form a contact opening etching mask 10 shown in FIG. 2. Next, a 'contact opening 108' is formed, which uses the contact opening to etch the dielectric layer 104 exposed by the mask 106 until the conductive region 102 is exposed within the contact opening 108. The engraving process used is preferably highly anisotropic, and may be performed using reactive ion etching (R 丨 E) using an appropriate poly-polymer gas. Referring to FIG. 3 ', the photoresist 10 6 is then removed or peeled off. This removal process is preferably a dry-etching process using oxygen electropolymerization or a wet etching process using a suitable solution. The pre-cleaning step is then performed to clean the residue 'from the surface of the dielectric layer 04 and more importantly, cleaning the residue 1 from the sidewall and bottom of the contact opening will increase the contact resistance value. The pre-cleaning step includes wet etching or dry #etching process two wherein the pre-cleaning step uses a buffered oxidant. In the dry etching process, a plasma gas formed of argon gas is preferably used. A thin first refractory metal layer 1 10 is then formed and conformed to the dielectric layer 04, contacting the sidewall and the bottom of the opening 108. The first refractory metal layer is formed of, for example, titanium (T i) or a group (T a). Next, a second refractory metal layer 2 is formed on the first tempering metal layer 11o. The second refractory metal layer 112 is preferably deposited by MOCVD method. It is used at a temperature of about 400 ~ 4 50 ° C, such as TDMAT (tetrakis ~ dimethylamido-titanium) or TDEAT (tetrakis-diethylamido-titanium). And the thickness of Che Fu Jia is about 120 to 16 Angstroms. The material of the second fire metal layer 1 12 is preferably composed of titanium or a group. Referring to FIG. 4 ', a first plasma treatment 125 is performed to remove impurities such as carbon or oxides attached to the second and only fire metal layer 1 1 2 and then, the second refractory
7120twfl.ptd 第13頁 541659 ___案號91107694_年月日__^_ 五、發明說明（8) 金屬層1 1 2係變成較薄之第一金屬氮化物阻障層丨丨4，厚度 減少至4 0 - 6 0埃。第一電漿處理1 2 5之較佳條件包括：包括 氮與氮之電漿氣體。第一金屬氮化物阻障層114具有相當 低之阻抗值。 參考第5圖，執行熱處理126以觸發在導電區1〇2上之 第一而才火金屬層1 1 〇部份與在導電區1 〇 2中之矽間之反應以 形成金屬石夕化物薄膜1 1 6。較好是，此熱製程包括快速熱 處理（R T P )。R τ P係較好執行於：氮氣中，在約5 5 0〜7 0 0 °C 下，持續約3 - 6 0秒。因為金屬矽化物薄臈1 1 6係具有低阻 抗之而寸火金屬，接觸阻抗值係減少。 參考第6圖，第三耐火金屬層118係形成於第一金屬氮 化物阻障層1 1 4上。第三耐火金屬層1 1 8之材質係本質上相 同於第二耐火金屬層丨1 2之材質。第三耐火金屬層丨1 8係較 好利用傳統沉積技術如Μ 0 C V D所沉積，較佳厚度約1 2 0 - 1 6 0 埃。 參考第7圖，相似地，執行第二電漿處理丨2 7以移除雜 質，並將第二耐火金屬層丨丨2轉變成較薄之第二金屬氮化 物阻障層120，厚度減少至40-60埃。第二電漿處理127之 較佳條件包括：包括氮與氫之電漿氣體。第二金屬氮化物 阻障層1 2 0具有相當低之阻抗值。 參考第8圖，導電金屬層1 2 2，比如為鎢，係利用傳統 如CVD 或電化沉積（eiectro-chemical deposition ， ECD) 方法而沉積於介電層丨0 4上以填滿接觸開口丨〇 8 。因為第二 金屬氮化物阻障層丨2 〇與導電金屬層1 2 2之z e t a值係相當不 同’所以不會彼此排斥，導致良好空隙填滿。因而，介電7120twfl.ptd Page 13 541659 ___Case No. 91107694_year month __ ^ _ V. Description of the invention (8) The metal layer 1 1 2 becomes a thinner first metal nitride barrier layer 丨 丨 4, thickness Reduced to 40-60 Angstroms. Preferred conditions for the first plasma treatment 1 2 5 include: a plasma gas including nitrogen and nitrogen. The first metal nitride barrier layer 114 has a relatively low resistance value. Referring to FIG. 5, a heat treatment 126 is performed to trigger a reaction between the first and second metal layer 110 on the conductive region 102 and the silicon in the conductive region 102 to form a metal oxide film. 1 1 6. Preferably, this thermal process includes rapid thermal processing (RTP). R τ P is better performed in nitrogen for about 3-60 seconds at about 550 ~ 700 ° C. Because the metal silicide thin 臈 1 6 series has low impedance, and the fire resistance metal, the contact resistance value is reduced. Referring to FIG. 6, a third refractory metal layer 118 is formed on the first metal nitride barrier layer 1 1 4. The material of the third refractory metal layer 1 1 8 is essentially the same as the material of the second refractory metal layer 12. The third refractory metal layer 18 is preferably deposited using a conventional deposition technique such as M 0 C V D, and preferably has a thickness of about 120 to 160 angstroms. Referring to FIG. 7, similarly, a second plasma treatment is performed to remove impurities, and the second refractory metal layer is transformed into a thinner second metal nitride barrier layer 120, and the thickness is reduced to 40-60 angstroms. Preferred conditions for the second plasma treatment 127 include a plasma gas including nitrogen and hydrogen. The second metal nitride barrier layer 120 has a relatively low resistance value. Referring to FIG. 8, the conductive metal layer 1 2 2, such as tungsten, is deposited on the dielectric layer using a conventional method such as CVD or eiectro-chemical deposition (ECD) to fill the contact openings. 8 . Because the z e t a values of the second metal nitride barrier layer 丨 2 0 and the conductive metal layer 1 2 2 are quite different ', they do not repel each other, resulting in good void filling. Thus, the dielectric
7120twfl.ptd 第14頁 541659 案號 91107694 a 修正 五、發明說明（9) 層1 〇 4與導電金屬層1 2 2間之附著度係增加，而有效地避免 阻障層之斷裂。 參考第9圖，執行化學機械研磨製程，用以移除導電 金屬層1 2 2 ，第二金屬氮化物阻障層1 2 0 ，第一金屬氮化物 阻障層1 1 4與第一耐火金屬層1 1 0之部份，直到露出介電層 1 0 4， 而形成接觸插塞1 5 0。 矛4用本發明之方式，進行RTP與接著形成第二金屬氮 化物阻障層1 2 0以限制氧化物膜形成於第二金屬氮化物阻 障層120表面上，而促進介電層104與導電金屬層122間之 良好附著。因為避免形成氧化物膜於第二金屬氮化物阻障 層120上，第二金屬氮化物阻障層120與導電金屬層122間 之zeta值可維持大差異，因而第二金屬氮化物阻障層120 與導電金屬層1 2 2間之排斥可被限制，因而此條件促進良 好空隙填滿。因此，可避免形成空隙，因而，可有效地限 制因為電子遷移造成之裝置失誤。因為第二金屬氮化物阻 障層120與導電金屬層122間之大zeta值差異，介電層104 與導電金屬層1 2 2間之附著度係增加，而有效地避免第一 耐火金屬層110 ，第一金屬氮化物阻障層114與第二金屬氮 化物阻障層120之斷裂。因為第一耐火金屬層110 ，第一金 屬氮4匕物阻障層1 1 4與第二金屬氮化物阻障層1 2 0係不會斷 裂或破裂，第一金屬氮化物阻障層1 1 4與第二金屬氮化物 阻障層12◦可有效地避免金屬離子或原子擴張至介電層104 内部，而避免裝置之短路。因為在接觸中之導電金屬層 1 2 2之晶格結構未被破壞，且第一耐火金屬層1 1 0 、第一與 第二金屬氮化物阻障層1 1 4與1 2 0也未被破壞，可避免因電7120twfl.ptd Page 14 541659 Case No. 91107694 a Amendment 5. Description of the invention (9) The adhesion between the layer 104 and the conductive metal layer 12 is increased, and the barrier layer is effectively prevented from breaking. Referring to FIG. 9, a chemical mechanical polishing process is performed to remove the conductive metal layer 1 2 2, the second metal nitride barrier layer 1 2 0, the first metal nitride barrier layer 1 1 4 and the first refractory metal. A portion of the layer 1 10 is formed until the dielectric layer 104 is exposed, and a contact plug 150 is formed. The spear 4 uses the method of the present invention to perform RTP and then form a second metal nitride barrier layer 120 to limit the formation of an oxide film on the surface of the second metal nitride barrier layer 120, and promote the dielectric layer 104 and Good adhesion between the conductive metal layers 122. Because the formation of an oxide film on the second metal nitride barrier layer 120 is avoided, the zeta value between the second metal nitride barrier layer 120 and the conductive metal layer 122 can maintain a large difference, so the second metal nitride barrier layer The repulsion between 120 and the conductive metal layer 12 can be limited, so this condition promotes good void filling. Therefore, the formation of voids can be avoided, and therefore, device errors due to electron migration can be effectively restricted. Because of the large zeta value difference between the second metal nitride barrier layer 120 and the conductive metal layer 122, the adhesion between the dielectric layer 104 and the conductive metal layer 12 is increased, and the first refractory metal layer 110 is effectively avoided. The first metal nitride barrier layer 114 and the second metal nitride barrier layer 120 are broken. Because the first refractory metal layer 110, the first metal nitrogen barrier layer 1 1 4 and the second metal nitride barrier layer 1 2 0 are not cracked or cracked, the first metal nitride barrier layer 1 1 4 and the second metal nitride barrier layer 12 can effectively prevent metal ions or atoms from expanding into the dielectric layer 104, and avoid short circuit of the device. Because the lattice structure of the conductive metal layer 1 2 2 in contact is not damaged, and the first refractory metal layer 1 1 0 and the first and second metal nitride barrier layers 1 1 4 and 1 2 0 are not damaged. Destroyed to avoid electricity
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71201 w f1.p t d 第15頁 541659 案號 91107694 曰 修正 五、發明說明（10) 子遷移所造成之空隙產生，因而可限制由電子遷移所造成 之裝置失誤。因而，裝置之可靠性可本質上增加。 ♦J用本發明之方式，執行RTP製程係引發導電區1 02之 矽與第一耐火金屬層1 1 0間之反應以形成金屬矽化物薄膜 1 1 6。因為金屬矽化物薄膜1 1 6係具低阻抗之耐火金屬，接 觸阻抗值可本質上減少，因而R C延遲時間可本質上減少。 因而，裝置之操作速度可本質上增加。 第1 0至1 4圖顯示根據本發明之第二較佳實施例之製造 接觸插塞之製程之剖面圖。 參考第10圖，係提供具有導電區202形成於其上之基 底200 。由如SOP(spin-on-polymer)材質所組成之低介電 常數材質之介電層2 0 4係形成於基底2 0 0上。微影與蝕刻製 程係用以形成接觸開口 2 0 8於介電層2 0 4中，直到導電區 2 0 2係露出於介電層2 0 4内。預清洗步驟係用以從介電層 2 0 4表面清洗殘餘物，而更重要的是，從接觸開口之側壁 與底部清洗殘餘物，否則將增加接觸阻抗值。預清洗步驟 包括濕蝕刻或乾蝕刻製程，其中該預清洗步驟使用緩衝氧 化劑。在乾钱刻製程中，較好使用由氬氣所形成之電漿氣 體。薄層之第一耐火金屬層210係形成並保角於介電層 2 0 4 ，接觸開口 2 0 8之側壁與底部上。第一耐火金屬層 2 1 0 ，比如，係由酞（T i )或钽（T a )所形成。接著，多層金 屬氮化物阻障層2 1 4係形成於第一耐火金屬層2 1 0上。多層 金屬氮化物阻障層2 1 4之形成係，比如，利用Μ 0 C V D製程而 沉積由約1 2 0 - 1 6 0埃厚度之鈦或钽所組成之第二耐火金屬 層，接著，用電漿氣體處理該第二耐火金屬層以將第二耐71201 w f1.p t d P.15 541659 Case No. 91107694 Revision V. Description of the invention (10) The generation of voids caused by sub-migration can limit device errors caused by electronic migration. Thus, the reliability of the device can be substantially increased. ♦ J In the manner of the present invention, performing the RTP process initiates a reaction between the silicon in the conductive region 102 and the first refractory metal layer 110 to form a metal silicide film 116. Since the metal silicide film 1 16 is a refractory metal with a low resistance, the contact resistance value can be substantially reduced, so the R C delay time can be substantially reduced. Thus, the operating speed of the device can be substantially increased. 10 to 14 show cross-sectional views of a process for manufacturing a contact plug according to a second preferred embodiment of the present invention. Referring to FIG. 10, a substrate 200 having a conductive region 202 formed thereon is provided. A dielectric layer 2 0 4 of a low dielectric constant material composed of a SOP (spin-on-polymer) material is formed on the substrate 2 0. The lithography and etching process is used to form a contact opening 208 in the dielectric layer 204 until the conductive region 202 is exposed in the dielectric layer 204. The pre-cleaning step is used to clean the residue from the surface of the dielectric layer 204, and more importantly, to clean the residue from the sidewall and bottom of the contact opening, otherwise the contact resistance value will be increased. The pre-cleaning step includes a wet or dry etching process, wherein the pre-cleaning step uses a buffered oxidizing agent. In the dry money engraving process, a plasma gas formed of argon gas is preferably used. The thin first refractory metal layer 210 is formed and conformed to the dielectric layer 2 0 4, and contacts the side wall and the bottom of the opening 2 0 8. The first refractory metal layer 2 1 0 is formed of, for example, phthalate (T i) or tantalum (T a). Next, a multilayer metal nitride barrier layer 2 1 4 is formed on the first refractory metal layer 2 1 0. The formation system of the multilayer metal nitride barrier layer 2 1 4 is, for example, a second refractory metal layer composed of titanium or tantalum having a thickness of about 120 to 160 angstroms is deposited by using a M 0 CVD process. Plasma gas treats the second refractory metal layer to convert the second refractory metal layer.
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7120twfl .ptd 第16頁 541659 _案號 91107694_年月日__ 五、發明說明（11) 火金屬層轉變成金屬氮化物阻障層。上述電漿處理較好包 括：包含氮氣與氫氣之電漿氣體。第二耐火金屬層之沉積 與電聚處理周期循環，比如1 - 3周期，直到形成所需厚度 多層金屬氮化物阻障層2 1 4。接著，執行熱處理2 2 6以觸發 在導電區202上之第一耐火金屬層210部份與在導電區202 中之石夕間之反應以形成金屬矽化物薄膜2 1 6。較好是，此 熱製程為快速熱處理（R T P )。R T P係較好執行於：氮氣中， 在約5 5 0〜7 0 0 °C下，持續約3 - 6 0秒。因為金屬矽化物薄膜 2 1 6係具有低阻抗之耐火金屬，接觸阻抗值係減少。 參考第1 1圖，第三耐火金屬層2 1 8，比如鈦或钽，係 形成於多層金屬氮化物阻障層214上。第三耐火金屬層218 係較好利用傳統沉積技術如Μ 0 C V D所沉積，較佳厚度約 1 2 0 - 1 6 0 埃 〇 參考第1 2圖，相似地，在第三耐火金屬層2 1 8上執行 電漿處理227以將第三耐火金屬層218轉變成較薄之金屬氮 化物阻障層2 2 0 ，厚度減少至4 0 - 6 0埃。 參考第1 3圖，導電金屬層2 2 2，比如為鎢，係利用傳 、统如 CVD 或電 4匕沉積（electro — chemical deposition ， E C D )方法而沉積於介電層2 0 4上以填滿接觸開口 2 0 8。因為 金屬氮化物阻障層220與導電金屬層222之zeta值係相當不 同，所以不會彼此排斥，導致良好空隙填滿。因而，介電 層2 0 4與導電金屬層2 2 2間之附著度係增加，而有效地避免 阻障層之斷裂。 參考第1 4圖，利用化學機械研磨製程以移除導電金屬 層2 2 2 ，金屬氮化物阻障層2 2 0 ，多層金屬氮化物阻障層7120twfl .ptd Page 16 541659 _Case No. 91107694_Year / Month__ V. Description of the invention (11) The fire metal layer is transformed into a metal nitride barrier layer. The above plasma treatment preferably includes a plasma gas containing nitrogen and hydrogen. The second refractory metal layer is cycled through a cycle of deposition and electropolymerization, such as 1 to 3 cycles, until a multilayer metal nitride barrier layer 2 1 4 of a desired thickness is formed. Next, a heat treatment 2 2 6 is performed to trigger a reaction between the first refractory metal layer 210 portion on the conductive region 202 and the stone in the conductive region 202 to form a metal silicide film 2 1 6. Preferably, this thermal process is rapid thermal processing (RTP). The R T P system is preferably performed in nitrogen for about 3 to 60 seconds at about 5500 to 700 ° C. Because the metal silicide film 2 1 6 is a refractory metal with low resistance, the contact resistance value is reduced. Referring to FIG. 11, a third refractory metal layer 2 1 8 such as titanium or tantalum is formed on the multilayer metal nitride barrier layer 214. The third refractory metal layer 218 is preferably deposited using a conventional deposition technique such as M 0 CVD, and the preferred thickness is about 120-1600 angstroms. Referring to FIG. 12, similarly, the third refractory metal layer 2 1 A plasma treatment 227 is performed on 8 to transform the third refractory metal layer 218 into a thinner metal nitride barrier layer 220, and the thickness is reduced to 40 to 60 angstroms. Referring to FIG. 13, the conductive metal layer 2 2 2, for example, tungsten, is deposited on the dielectric layer 2 0 4 by a conventional method such as CVD or electro-chemical deposition (ECD) to fill it. Full contact opening 2 0 8. Because the zeta values of the metal nitride barrier layer 220 and the conductive metal layer 222 are quite different, they do not repel each other, resulting in good void filling. Therefore, the adhesion between the dielectric layer 204 and the conductive metal layer 22 is increased, and the barrier layer is effectively prevented from being broken. Referring to FIG. 14, a chemical mechanical polishing process is used to remove the conductive metal layer 2 2 2, the metal nitride barrier layer 2 2 0, and the multilayer metal nitride barrier layer.
7120twf1.p t d 第17頁 541659 _案號 91107694_年月日_修正 _ 五、發明說明（12) 214與第一耐火金屬層210之部份，直到露出介電層204。 如此可形成接觸插塞2 5 0。 禾J用本發明之方式，進行RTP 22 6與接著形成金屬氮化 物阻障層2 2 0以限制氧化物膜形成於金屬氮化物阻障層2 2 0 表面上，以促進介電層204與導電金屬層222間之良好附 著。因為避免形成氧化物膜於金屬氮化物阻障層220上， 金屬氮化物阻障層2 2 0與導電金屬層2 2 2間之z e t a值可維持 大差異，因而金屬氮化物阻障層220與導電金屬層222間之 排斥可被限制，因而此條件促進良好空隙填滿。因此，可 避免形成空隙，因而，可有效地限制因為電子遷移造成之 裝置失誤。因為金屬氮化物阻障層2 2 0與導電金屬層2 2 2間 之大zeta值差異，介電層204與導電金屬層222間之附著度 係增力口，而有政地避免第一耐火金屬層2 1 0 ，多層金屬氮 化物阻障層2 1 4與金屬氮化物阻障層2 2 0之斷裂。因為第一 耐火金屬層210 ，多層金屬氮化物阻障層214與金屬氮化物 阻障層2 2 0係不會斷裂或破裂，多層金屬氮化物阻障層2 1 4 與金屬氮化物阻障層2 2 0可有效地避免金屬離子或原子擴 張至介電層204内部，而避免裝置之短路。因為在接觸中 之導電金屬層2 2 2之晶格結構未被破壞，且相鄰之第一耐 火金屬層210、多層金屬氮化物阻障層214與金屬氮化物阻 障層2 2 0也未被破壞，可避免因電子遷移所造成之空隙產 生，因而可限由電子遷移所造成之裝置失誤。因而，裝 置之可靠性可本質上增加。 利用本發明之方式，執行RTP製程2 2 6係引發導電區 2 ◦ 2之矽與第一耐火金屬層2 1 0間之反應以形成金屬矽化物7120twf1.p t d p. 17 541659 _ case number 91107694_ year month day _ amendment _ V. Description of the invention (12) 214 and part of the first refractory metal layer 210 until the dielectric layer 204 is exposed. In this way, a contact plug 2 50 can be formed. In the method of the present invention, RTP 22 6 is performed and then a metal nitride barrier layer 2 2 0 is formed to limit the formation of an oxide film on the surface of the metal nitride barrier layer 2 2 0 to promote the dielectric layer 204 and Good adhesion between the conductive metal layers 222. Because the formation of an oxide film on the metal nitride barrier layer 220 is avoided, the zeta value between the metal nitride barrier layer 220 and the conductive metal layer 22 can maintain a large difference, so the metal nitride barrier layer 220 and The repulsion between the conductive metal layers 222 can be limited, so this condition promotes good void filling. Therefore, the formation of voids can be avoided, and therefore, device errors due to electron migration can be effectively restricted. Because of the large zeta value difference between the metal nitride barrier layer 2 2 0 and the conductive metal layer 2 2 2, the adhesion between the dielectric layer 204 and the conductive metal layer 222 is a booster, and the first refractory is politically avoided The metal layer 2 1 0, the multilayer metal nitride barrier layer 2 1 4 and the metal nitride barrier layer 2 2 0 are broken. Because the first refractory metal layer 210, the multilayer metal nitride barrier layer 214 and the metal nitride barrier layer 2 2 0 are not broken or cracked, and the multilayer metal nitride barrier layer 2 1 4 and the metal nitride barrier layer 2 2 0 can effectively prevent metal ions or atoms from expanding into the dielectric layer 204 and avoid short circuit of the device. Because the lattice structure of the conductive metal layer 2 2 2 in contact is not damaged, and the adjacent first refractory metal layer 210, the multilayer metal nitride barrier layer 214, and the metal nitride barrier layer 2 2 0 are not damaged. The destruction can avoid the generation of voids caused by the electronic migration, and thus can limit the device errors caused by the electronic migration. Thus, the reliability of the device can be substantially increased. Using the method of the present invention, the RTP process 2 2 6 is performed to initiate a reaction between the conductive region 2 ◦ 2 and the first refractory metal layer 2 10 to form a metal silicide.
7120twfl.ptd 第18頁 541659 _案號 91107694_年月日__ 五、發明說明（13) 薄膜2 1 6。因為金屬矽化物薄膜2 1 6係具低阻抗之耐火金 屬，接觸阻抗值可本質上減少，因而R C延遲時間可本質上 減少。因而，裝置之操作速度可本質上增加。 甚至，雖然本發明之實施例指向製造接觸阻障金屬之 方法，習知此技者可了解，如單一 /雙刻紋（d a m a s c e n e )技 術之形成内連接之其他技術，或牽涉到利用如銅、鎢或鋁 之導電材質填滿開口之形成路由（via)或插塞之另外技 術，也可用以實施本發明。 綜上所述，雖然本發明已以較佳實施例揭露如上，然 其並用以限定本發明，任何熟習此技藝者，在不脫離本 發明之精神和範圍内，當可作各種之更動與潤飾，因此本 發明之保護範圍當視後附之申請專利範圍所界定者為準。7120twfl.ptd Page 18 541659 _Case No. 91107694_ Year Month__ V. Description of the invention (13) Film 2 1 6. Since the metal silicide film 2 1 6 is a refractory metal with a low resistance, the contact resistance value can be substantially reduced, so the R C delay time can be substantially reduced. Thus, the operating speed of the device can be substantially increased. Moreover, although the embodiments of the present invention are directed to a method for manufacturing a contact barrier metal, those skilled in the art will understand that other technologies such as single / double engraving (damascene) technology for forming internal connections, or involving the use of Another technique of filling the opening with a conductive material of tungsten or aluminum to form a via or a plug can also be used to implement the present invention. In summary, although the present invention has been disclosed in the preferred embodiment as above, it is also used to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application.
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| TW091107694A TW541659B (en) | 2002-04-16 | 2002-04-16 | Method of fabricating contact plug |
| US10/064,525 US6706626B2 (en) | 2002-04-16 | 2002-07-24 | Method of fabricating contact plug |
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| TW091107694A TW541659B (en) | 2002-04-16 | 2002-04-16 | Method of fabricating contact plug |
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| CN106206273A (en) * | 2015-06-01 | 2016-12-07 | 富士电机株式会社 | The manufacture method of semiconductor device |
| TWI809454B (en) * | 2021-07-19 | 2023-07-21 | 南亞科技股份有限公司 | Method of manufacturing semiconductor structure |
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| US7485577B2 (en) * | 2003-04-18 | 2009-02-03 | Dongbuanam Semiconductor, Inc. | Method of forming metal line stacking structure in semiconductor device |
| US7169704B2 (en) * | 2002-06-21 | 2007-01-30 | Samsung Electronics Co., Ltd. | Method of cleaning a surface of a water in connection with forming a barrier layer of a semiconductor device |
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| US7064056B2 (en) * | 2003-06-13 | 2006-06-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier layer stack to prevent Ti diffusion |
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| US6927162B1 (en) | 2004-02-23 | 2005-08-09 | Advanced Micro Devices, Inc. | Method of forming a contact in a semiconductor device with formation of silicide prior to plasma treatment |
| CA2558312A1 (en) | 2004-03-03 | 2005-09-15 | Caducys, L.L.C. | Interrogator and interrogation system employing the same |
| US7605469B2 (en) * | 2004-06-30 | 2009-10-20 | Intel Corporation | Atomic layer deposited tantalum containing adhesion layer |
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| KR100552857B1 (en) * | 2004-10-25 | 2006-02-22 | 동부아남반도체 주식회사 | Method for fabricating contact of semiconductor device |
| US7229918B2 (en) * | 2005-02-14 | 2007-06-12 | Infineon Technologies Ag | Nitrogen rich barrier layers and methods of fabrication thereof |
| US8308053B2 (en) * | 2005-08-31 | 2012-11-13 | Micron Technology, Inc. | Microfeature workpieces having alloyed conductive structures, and associated methods |
| US8039391B1 (en) | 2006-03-27 | 2011-10-18 | Spansion Llc | Method of forming a contact in a semiconductor device with engineered plasma treatment profile of barrier metal layer |
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| US10453747B2 (en) * | 2017-08-28 | 2019-10-22 | Globalfoundries Inc. | Double barrier layer sets for contacts in semiconductor device |
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| US11469139B2 (en) * | 2019-09-20 | 2022-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bottom-up formation of contact plugs |
| CN115132701A (en) * | 2021-03-25 | 2022-09-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| US6475912B1 (en) * | 1998-06-01 | 2002-11-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method and apparatus for fabricating the same while minimizing operating failures and optimizing yield |
| JP3175721B2 (en) * | 1999-02-05 | 2001-06-11 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| KR100379333B1 (en) * | 2000-08-16 | 2003-04-10 | 주식회사 하이닉스반도체 | Fabrication method for titanium silicide layer |
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2002
- 2002-04-16 TW TW091107694A patent/TW541659B/en not_active IP Right Cessation
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106206273A (en) * | 2015-06-01 | 2016-12-07 | 富士电机株式会社 | The manufacture method of semiconductor device |
| CN113436969A (en) * | 2015-06-01 | 2021-09-24 | 富士电机株式会社 | Method for manufacturing semiconductor device |
| TWI809454B (en) * | 2021-07-19 | 2023-07-21 | 南亞科技股份有限公司 | Method of manufacturing semiconductor structure |
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| US20030194859A1 (en) | 2003-10-16 |
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