TW457683B - Cu damascene processes preventing hillock on the surface - Google Patents

Abstract

The present invention discloses a manufacturing method for Cu damascene structure which includes the following steps: first, forming the dielectric on the semiconductor substrate; defining via pattern in the dielectric layer to expose the upper surface of part of the semiconductor substrate; then, depositing the copper layer on the semiconductor substrate to fill in the via pattern; conducting the first chemical mechanical polishing procedure on the semiconductor substrate to remove part of the copper layer on the upper surface of the dielectric layer; defining the copper damascene structure in the via pattern; then, conducting thermal annealing procedure on the semiconductor substrate to reduce the stress of the copper damascene structure, in which after the thermal annealing procedure, the hillock structure on the upper surface of the copper damascene structure is generated; then, conducting the second chemical mechanical polishing procedure on the semiconductor substrate to remove the hillock structure so as to produce a planarized upper surface for the copper damascene structure.

Description

457683 V. Description of the invention α) Field of the invention: The present invention relates to a method for making copper damasce-ne by the semiconductor industry, especially a method using thermal tempering to reduce the surface of the copper damascene structure. hillock). Background of the Invention: With the rapid development of the semiconductor industry, after entering the design specifications of ultra-large integrated circuits (ULSI), the design trend of high-density integrated circuits makes it possible to define a number of Millions of components, and electronic wiring structures that connect them. However, with the continuous shrinking of the size of integrated circuits, coupled with the limitations of lithographic resolution, errors in exposure and focus, and the accuracy of image transmission, all have encountered great difficulties in the production of various components and circuits. In addition, in order to effectively solve the above problems, we vigorously and spiritually bet on the development of da_Cene procesd "use" in order to improve the yield of processes and products in the lithography specification step. Beibu Jiang N. Calling back in general In the traditional gold, which has excellent conductivity and low cost for depositing and engraving, it is to become a semiconductor. However, in the integration of semiconductor components to make the connection structure, it also encountered the connection process. Cost and can be used as the most widely used wire material in the industry as the process requires. While rising, the use of aluminum is extremely problematic. For example, in high temperature environments

Page 4 4 5 7 6 8 3 V. Description of the invention (2) '--- In the aluminum atom, it is easy to cross-diffuse with the silicon substrate (1 discuss 61 · -diffusion) and cause "spike phenomenon", and In addition, when the size of the aluminum wire is reduced with the component, the atomic movement caused by M electromigration can easily cause a short circuit in the aluminum wiring structure. Therefore, in the current In the semiconductor industry, it is often tried to replace the traditionally used aluminum metal with a copper metal with a relatively conductive and low resistivity. In particular, copper metal has a low electromobility, and is a wiring structure applicable to semiconductor semiconductors. ~, Please refer to the first figure. In a typical method of manufacturing a steel mosaic structure, a dielectric layer 12 is first formed on a semiconductor substrate 10, and an opening pattern is defined on the dielectric layer 12 using a lithographic etching process. Then, a barrier layer 14 may be formed along the opening surface to prevent the copper damascene structure produced later from invading and spreading into the semiconductor substrate from the sidewall of the opening pattern. Subsequently, a copper electroplating (ECP) process may be used to form a copper layer 16 on the semiconductor substrate 10 and fill the opening pattern. The chemical mechanical polishing process (CMP) is used to polish the semiconductor substrate 10 to remove a portion of the copper layer 16 and the barrier layer 14 ′ on the upper surface of the semiconductor substrate 1Q to define a copper damascene structure 18, as As shown in the second figure. However, it is worth noting that the electroless plating process for the deposition of the copper layer 16 is often performed in an environment at room temperature. In addition, "in order to make the produced copper wires have better quality", the high temperature thermal tempering sequence of the semiconductor substrate 10 will not be performed during the entire process of manufacturing the copper damascene structure. So, in progress

Page 5 457683 ^ — —— "--__ V. Description of the invention (3) After the mechanical grinding process is learned, the defined copper mosaic structure 18 will have an uneven stress distribution and present extremely unstable material characteristics. Furthermore, on the copper damascene structure 18, because of the unstable state of the copper atoms, a rougher surface will be generated, and a slightly convex defect will be generated. Β To be specified, in order to meet the requirements of high accumulation degree The integrated circuit fabricated on the semiconductor substrate 10 will have a multi-layer structure. Therefore, after defining the metal pattern layer where the copper damascene structure 18 is located, a nitride layer 20 will be formed to cover the copper damascene structure 丨 8 and the dielectric layer 丨 2 to produce the effect of electrical isolation and prevent Improper money invasion was encountered in the subsequent etching process. Then, the intermetal dielectric layers 22 and 24 can be sequentially deposited on the silicon nitride layer 20 'and the above-mentioned lithography process and electroplating procedure are used to define the metal patterns between these film layers. However, 1 is because the deposition of the silicon nitride layer 20 or the subsequent intermetallic dielectric layers 2 2, 2 and 4 'are performed in a high temperature environment. Therefore, the copper atoms' in the copper buried structure 18 will be affected by this high temperature environment, and the phenomenon of grain growth will occur. At this time, the "copper atoms will have a large displacement due to the squeezing effect of each other" in order to release the unevenly distributed stress. Therefore, the slight protrusions originally on the upper surface of the copper damascene structure 18 will gradually become serious, and a protrusion structure 26 as shown in the third figure is formed. Moreover, the shape of these raised structures 26 is transmitted upward along the surfaces of the intermetal dielectric layers 22, 24, and exhibits a multiplier effect. In other words, this convex structure will also be produced on the upper surface of the intermetal dielectric layer 24, and its shape and distribution will be more shaped.

Page 6 457683 V. Description of the invention (4) Magnified and serious. In this way, the successively deposited dielectric layers will have poor flatness and easily cause the problem of disconnection of the connection due to the bridging effect when defining the metal connection pattern. Please refer to the fourth picture, 'The cross-section photos of the semiconductor substrate are used to make the dielectric layers 32 and 34 on top of the copper damascene structure. The dielectric layers 32 and 34 on this figure are on the surface of the dielectric layer 34. The characteristic of the convex defect ladder shape is more significant β Purpose and summary of the invention: In the film, it can be clearly seen that after the related process, the above-mentioned convex defect was found in the steel mosaic structure 30. In particular, it is composed of FSG material, so this material will reproduce the lower stage because of this material. The purpose of the present invention is to create a copper inlaying process that can prevent disconnection due to the arch bridge effect. Another method of the present invention. In order to provide a method for improving the flatness of the copper mosaic structure, another stress distribution of the present invention is to provide a method for effectively releasing the 6 'in the copper mosaic structure to generate convex defects on its surface. -A method for making steel mosaic structures. First, the present invention discloses-

Page 457683

Define the opening pattern in the dielectric layer. # 着 ， Copper layer can be deposited in the semi-conductor chemical-mechanical case. And the stomach substrate is advanced to remove the structure located on the upper surface of the dielectric layer:! Structure in the opening pattern. Subsequently, the semiconductor substrate is subjected to a thermal tempering procedure, in which the thermal tempering is 350 to a paste. . In the environment ', the second chemical mechanical polishing process is performed at a time of about 15 to 45 minutes, m ^ +, so that the copper structure has a flat upper surface. Detailed description of the invention: Please refer to the fifth figure, and first provide a single crystal silicon substrate 50 with a &lt; 100 &gt; crystal orientation. Generally speaking, other types of semiconductor materials, such as gallium arsenide, germanium, or silicon on insulator (SOI), can be used as the semiconductor substrate. In addition, 'because of the characteristics of the surface of the semiconductor substrate, the present invention does not cause any special influence', depending on its crystal orientation, you can also choose <丨 丨 〇 &gt; or &lt; 111 &gt; 〇 A dielectric layer 52 is formed on the material 50. It is explained here that before the formation of the dielectric layer 52, various active elements, passive elements, peripheral circuits, and the like required for integrated circuits have been fabricated on the semiconductor substrate 50. In other words, on the surface of this semiconductor substrate 50, there are already various required

Page 8 457683 V. Description of the invention (6) --- Functional layer and material layer "-In general, the dielectric layer 52 can be made of silicon oxide, non-doped silicon glass (USG), fluorine-doped silicon glass (FSG ), Low dielectric value (low κ value) material or other suitable insulating materials. For example, chemical vapor deposition (CVD) can be used with tetraethyl silicate (TEOS) at a temperature of about 600 to 800. C, the pressure is about 0.1 to i0torr to form silicon oxide; or thermal oxidation can also be used to make silicon oxide β In addition, tetraethyl silicate (TEOS) can also be used as a reaction material, and fluorine atoms are added Then, a chemical vapor deposition (LPCVD) method is used to form a fluorosilicate glass (FSG) as the above-mentioned intermediary 52. Then, an opening pattern can be defined on the dielectric layer 52 by conventional lithography and etching techniques to expose the upper surface of the semiconductor substrate 50. In a preferred embodiment, the above-mentioned opening pattern can be defined using a dry etching method such as plasma etching. When the material of the dielectric layer 52 is made of silicon oxide, the corresponding etchant can be selected from CHF3 / CF CiiF3 / 02, CH3CHF2, CF4 / 02. Next, a barrier layer 54 is formed on the side wall of the opening pattern and the exposed upper surface of the semiconductor substrate 50 to prevent the diffusion phenomenon between the copper layer and the dielectric layer 52 or the semiconductor substrate 50 produced in the subsequent process, resulting in a spike effect (叩 丨 to 叩 ef feet). In a preferred embodiment, the material of the barrier layer 54 can be selected from tantalum (Ta), nitride button (TaN), or any combination thereof. Generally speaking, a sputtering process can be performed first-depositing a tantalum layer on the upper surface of the opening pattern, and then placing the semiconductor substrate 50 in an environment of N2 or Dragon 3 'to form the required

457683

V. Description of the invention CO tantalum nitride. Alternatively, it is also possible to bombard the giant metal with plasma ions, and pass in argon and nitrogen, so that the tantalum atoms splashed by the bombardment can interact with the nitrogen atoms formed by the dissociation reaction (^ dissociation reactio). , React and form lithium nitride and deposit on the surface of the opening pattern and the semiconductor substrate 50. Seed layer (In the Cu seeding example, a copper seed layer such as physical vapor deposition sputtering or the like is immersed in a copper sulfate solution ical Plating; the top is filled with copper ion to which the seed layer 5 6 is electrically connected. After the barrier layer 54 is formed, a copper crystal iayer) 56 is formed on the upper surface of the barrier layer 54. The deposition in the preferred embodiment 5 can be formed using well-known related techniques, such as physical vapor deposition (PVD). Next, the semiconductor substrate 50 may be subjected to an Electrochemical Chem ECP reaction to form a copper layer 58 in the copper seed layer 56 pattern. In general, copper crystals can be used as the cathode of the power source to merge them in the copper sulfate solution; they can be deposited on the surface of the copper seed layer 56. Then "refer to the sixth figure" to perform a chemical polishing process (CMP) on the semiconductor substrate 50 to remove a portion of the copper sound 58, the copper seed layer 56 and the barrier layer 54 on the upper surface of the dielectric layer 52. To define the copper damascene structure 60 in a 3-port pattern. Among them, the formed copper inlaid structure 60 can be used as a connection (ν ia) or plug (ρ 1 ug) according to the integrated electrical design. The 'as mentioned above' due to the ECP procedure is to be specified The environment at room temperature proceeds so that the defined copper ballast structure 60 will have an uneven stress distribution_ and

457683 V. Description of the invention (8) Presents extremely unstable material characteristics. Also, on the surface of the copper damascene structure 18, a surface defect having a slight protrusion is generated due to the unstable state of the copper atom. Next, as shown in the seventh figure, the semiconductor substrate 50 may be subjected to a high-temperature thermal tempering process to reduce the structural stress of the copper damascene structure 60 and repair the defects therein. At this time, the copper atoms in the copper damascene structure 60 will also be affected by this south temperature tempering 'and cause the phenomenon of grain growth, causing the convex structure 62 on the upper surface of the copper damascene structure 60 to be more serious. In a preferred embodiment, this high-temperature tempering process can be performed in an environment filled with nitrogen and hydrogen 'at a temperature of about 350 to 4,000c' for about 15 to 45 minutes. As for the better system, it can be controlled to about 30 minutes, in order to fully and effectively release the stress between steel atoms. Eyes ,,,, and eighth, after the high temperature process is performed to drive the copper mosaic structure 60, after stabilization, the semiconductor substrate 50 may be subjected to a chemical mechanical polishing process to remove the protruding copper mosaic structure 6 The convex structure 62 on the upper surface makes the copper damascene structure 60 have a better planarization effect. Normal and ancient: The grinding process is only used to remove the raised contact. {The sequence time is only 10 to 30 seconds to achieve the desired effect. A cover layer 64 is formed on the copper mosaic structure. In addition to electrically isolating the steel mosaic, the cover layer 64 can also be used as a bottom. Next, please refer to the ninth figure, the shape 60 and the upper surface of the dielectric layer 62. Among them, 457683 is generated between the structure 60 and the subsequently deposited film layer. 5. Description of the invention (9) The protective layer of the lower dielectric layer 62 and the copper damascene structure 60 is used in order to prevent the dielectric layer in the subsequent etching process card. 62 and the copper damascene structure 60 are eroded by the etchant. In the preferred embodiment, the masking layer 64 may be made of a silicon nitride (Si N) or silicon carbide (Si C) material. Among them, when the silicon nitride material is selected, low pressure chemical vapor deposition (LpcvD), or plasma enhanced chemical vapor deposition (PECVD) can be used. At a temperature of about 400-800, its environment, It is formed by passing SiH4, NH3, N2, N20 or SiH2Cl2, NH3, N2, N20 and other reaction gases. After deposition on the cover layer 64. When it is better to etch in it, the dielectric layer 62 is made of an oxidizing material. Here, the stop layer 68, the cover layer 64, and then the upper surface are provided to provide a first choice in this embodiment. The difference in the properties of the cover layer 64 can be the same as the anti-material. The material, FSG, USG, or an intermetal dielectric layer 66 can effectively protect the intermetal dielectric that can form the first intermetal and the metal pattern layer. The layer 66 and the first intermetal dielectric low-K material to define the function of the film layer under the trench or the guard are used to form the upper surface of t, and the first intermetal dielectric layer 66 under the first etch is also formed. Dielectric layer 6 6 Insulation effect Cover layer 6 4 Connection pattern. It can be the same as the above-mentioned layer 66, and then 'repeat the above steps' on the first surface of the first etch stop layer = deposit a second gold-J dielectric layer 70 so as to define a desired metal pattern. Generally speaking, by performing a lithographic silver engraving process on the second intermetallic dielectric layer 70 and the dielectric layer 66, it is possible to define the required ^ in these two film layers. Subsequently, the Ecp process described above can be reused.

4 5768 ^ V. Description of the Invention (Double) A double-embedded structure or a single-depressed structure located in the first inter-metal dielectric layer 66 and the second inter-metal dielectric layer 70 is described. It is worth noting that, after the first grinding process, the copper damascene structure 60 has been subjected to a high-temperature thermal tempering process, and by performing the second grinding process, the generated convex structure 62 is removed. Therefore, the copper atoms in the copper damascene structure 60 already have relatively stable material properties. Therefore, in the subsequent process of depositing the cover layer 64, the first intermetallic dielectric layer 66, and the second intermetallic dielectric layer 70, the high temperature process environment will no longer cause convex defects on the surface of the copper damascene structure 60. . In this way, as shown in the ninth figure, the first intermetal dielectric layer 66 and the second intermetal dielectric layer 70 that are subsequently deposited will have a flat upper surface shape. By using the method of the present invention to make a copper damascene structure, copper atoms can have the effects of grain growth and stress release in the process of high temperature thermal tempering. And ’using an extra chemical-mechanical grinding process, the copper-embedded structure will have an extremely flat surface. In this way, in the subsequent deposition process, the generation of the raised structure can be effectively avoided, and the bridging effect can be prevented from causing the metal connection to be disconnected. Please refer to the tenth drawings A to C. This part of the drawings shows the top view from above the semiconductor substrate. In the tenth diagram A, after the chemical mechanical polishing process is performed, the thermal tempering process is not performed. 'The upper surface of the semiconductor substrate is used. After subsequent deposition of the intermetallic dielectric layer, its surface will have severe protrusions. Defects (black dots scattered in the picture). In contrast, in the tenth B diagram, after chemical mechanical grinding,

Page 13 457683 V. Description of the invention (ιυ The thermal tempering process is performed at a temperature of about 250 ° C. At this time, the raised defects on the semiconductor substrate have been shown to have been greatly reduced. Moreover, as shown in Figure 10C It is shown that after the chemical mechanical polishing, a thermal tempering process at a temperature of about 400 ° C, the raised defects on the semiconductor substrate will be greatly reduced. Although the present invention is explained above with a preferred example However, it is not intended to limit the spirit and the inventive entity of the present invention, but only to this embodiment. Therefore, all modifications made without departing from the spirit and scope of the present invention should be included in the scope of patent application described below. .

Page 457683 The diagram is briefly explained. By: the following detailed description in conjunction with the attached drawing #, the above advantages and many advantages of the invention will be obtained, among which: The first diagram is a cross-sectional view of a semiconductor wafer The step of copper layer on the semiconductor substrate; 'The industry's technology is not shown according to the purpose of the chemical mechanical research to show the subsequent deposition of metal. The second picture is a section of the semiconductor wafer grinding process to remove part of the copper layer; The picture shows the dielectric layer formed on the semiconductor wafer. It is formed on the copper embedded structure. Table = = The fourth picture is a cross-sectional view of the semiconductor wafer to observe the convex defects. The fifth picture is A cross-sectional view of a semiconductor wafer, showing the steps of depositing a copper layer on a semiconductor substrate according to the method provided by the present invention; a sixth view is a cross-sectional view of a semiconductor wafer, showing the order of chemical machinery according to the method provided by the present invention The grinding process to remove a portion of the copper layer; the seventh circle is a cross-sectional view of a half-body wafer, showing the steps of a high-temperature thermal tempering process according to the method provided by the present invention; the eighth circle A cross-sectional view of a semiconductor wafer, showing a step of performing a chemical mechanical polishing process to remove a raised structure according to the method provided by the present invention; a ninth step is a cross-sectional view of a semiconductor wafer, showing the sequential formation of metal according to the method of the present invention The steps of the inter-dielectric layer on the semiconductor substrate; and the tenth A to C are cross-sectional views of the semiconductor wafer, showing the differences between the traditional method and the method of the present invention when the copper mosaic structure is manufactured.

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Claims (1)

457683 VI. Application for Patent Scope 1. A method for manufacturing a copper damascene structure. The method includes at least the following steps: forming a dielectric layer on a semiconductor substrate; defining an opening pattern in the dielectric layer to expose a portion of the semiconductor The upper surface of the substrate; the copper deposit layer is deposited on the semiconductor substrate and is filled in the opening pattern; the first chemical mechanical polishing process is performed on the semiconductor substrate to shift two = on the upper surface of the dielectric layer Part of the copper layer, and define the copper inlay structure in the @ opening pattern; the structure of the semiconductor substrate is subjected to a thermal tempering process to reduce the copper inlay surface, 'wherein after the thermal tempering process' in The surface of the steel inlaid structure will produce a raised structure; and the semiconductor substrate is subjected to a second step and the removal of the convex palladium M... The copper mosaic structure has a flat top surface. Materials, (FSG) The above-mentioned dielectric layer, fluorine-doped silica glass, as in the method of patent application No. 1, which can choose oxide, undoped silica glass (USG), low dielectric material or any combination thereof. The method for depositing the above-mentioned copper, such as item 丨 of the patent application range, further includes the following steps: forming a barrier layer on the patterned surface; and forming a copper seed layer on the barrier layer 457683 VI. Applying for a patent Fangu uses the chemical method :: method == 30% of the method ’where the above copper layer is a bond path? The method of item 4 wherein the above mentioned chemical electricity is the copper seed layer electric ism! Copper sulfate solution, and the copper ions can be reduced and crystallized by the copper ion :::: copper sulfate solution "% The method of item 1, wherein the step of forming the dielectric further includes the step of forming various element or material layers on the semiconductor substrate. ^ ^ A method as described in item 1 of the scope of patent application, wherein The thermal tempering procedure 'is performed in an environment with a temperature of about 350 to 400 ° C for about 15 to 45 minutes to complete a 8'. The method of item 1 of the patent application park, wherein the second chemical mechanical grinding is performed The time of the program is about 10 to 30 seconds. 9. The method of item 1 of the patent application scope, wherein the above-mentioned thermal tempering program can make the copper atoms in the copper mosaic structure grow and stabilize. 457683 The method includes at least the following six, the scope of patent application 10.-a method of manufacturing a copper mosaic structure: a portion of the semiconductor bottom is exposed and filled in the open D pattern to form a dielectric layer on the semiconductor substrate; defining an opening pattern In the dielectric layer, the upper surface of the material; depositing a copper layer on the semiconductor substrate; in the semiconductor substrate; first dividing the semiconductor substrate in the opening pattern of a portion of the upper surface of the dielectric layer; The substrate is thermally tempered in an environment with a temperature of about 350 to 40 ° C; and the human chemical mechanical grinding process is used to remove the copper layer and define the copper mosaic structure in the fire process. In the heat tempering process, At about 15 to 45 minutes, a second chemical mechanical polishing process is performed on the semiconductor substrate so that the copper damascene structure has a flat upper surface. 11. The method according to item 10 of the scope of patent application, wherein the material of the above-mentioned dielectric layer is' selectable oxide, undoped silica glass (USG), fluorine-doped cullet (FSG), low dielectric material, or random combination. 12. The method according to item 10 of the patent application scope, wherein before depositing the copper layer, the method further comprises the following steps: forming a barrier layer on the surface of the opening pattern; and forming a copper seed layer on the barrier layer. On the surface. 457683 VI. Scope of patent application 13. The method of applying for the scope of patent application No. 12 wherein the above-mentioned copper layer is formed by chemical plating (ECP). 14. For the method of applying for the scope of item 13 of the patent, where the above-mentioned chemical plating procedure is to immerse the semiconductor substrate in a copper sulfate solution, the electronic method is to electrically connect the copper seed layer to the cathode wire so as to be located at The copper ions in the copper sulfate solution can be reduced and deposited on the surface of the copper seed layer. 15. The method according to item 10 of the scope of patent application, wherein before forming the dielectric layer, it further comprises the step of forming various elements or material layers on the semiconductor substrate. 16. For the method of applying for item 10 of the patent scope, wherein the above-mentioned thermal tempering procedure can reduce the stress of the copper mosaic structure and cause grain growth of copper atoms in the copper mosaic structure, resulting in the copper mosaic The upper surface of the structure produces a raised structure. 17. The method of claim 16 in the scope of patent application, wherein the second chemical mechanical polishing procedure described above can remove the raised structure so that the copper mosaic structure has a flat upper surface. m 1 8_ The method according to item 10 of the scope of patent application, wherein the time for performing the second chemical mechanical polishing process is about 10 to 30 seconds. Page 19