TW531841B - Fabrication method of inter metal dielectrics to avoid damaging the wafer - Google Patents

Abstract

The present invention disclosed a fabrication method of inter metal dielectrics by HDPCVD (high density plasma chemical vapor deposition) to avoid the generation of particle damaging and cracking; the process is mainly forming an oxide layer with high silicon concentration in situ by HDPCVD before depositing the inter metal dielectrics, and being in cooperation with gradual increase of the bias voltage, the damage to the wafer is reduced to the minimum.

Description

531841

V. Description of the invention (1) Field of the invention: The present invention relates to a method for making internal electrics. In the semiconductor substrate, the use of high-density voltage effect and wafer chipping] as the background of the invention: 'Metal dielectric layer (Inter-Metal) The present invention relates in particular to a plasma chemical vapor deposition and can avoid metal in the arc Method of the dielectric layer. With the development of semiconductor integrated circuit manufacturing technology, the number of elements in the wafer has been increasing, the size of components has been continuously reduced due to the increase in the degree of integration, the line width of metal interconnects and their structures The area between the metal interconnects is also getting smaller and smaller, and the smaller the area between the metal interconnect structures, the higher the gap fill requirements of the inner metal dielectric layer, so as to avoid leaving the gap fill incomplete. Lower hole 0 Compared with other chemical vapor deposition (hereinafter referred to as CVD), such as the inner metal intermediary formed by plasma enhanced chemical vapor deposition process (hereinafter referred to as PE4VD) Electrical layer, high density plasma chemical vapor deposition (hereinafter referred to as HDP-CVD) manufacturing process of the inner metal dielectric layer material, has excellent trench filling characteristics, It is especially suitable for the fabrication of sub-micron ultra-large integrated circuit (LSI) devices. The South Density Plasma Chemical Vapor Deposition process mainly uses its dual characteristics of deposition and sputtering to achieve a well-filled inner metal dielectric layer. High-density plasma chemical vapor deposition technology is mainly based on oxygen () and silane (s 丨 &)

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ί i) Plasma sputtering to remove part of the inner metal dielectric layer protrusion (QVerhang) located between the metal interconnects ^ edge = ditch to eliminate, build up obstacles, and improve the dielectric layer filling People trench effect. It can be formed by repeated deposition and sputtering processes-the number of times the internal metal dielectric is well filled in the trench depends on the line width and the degree of accumulation of the components, where the right line is narrow and the degree of accumulation is dense. The number of repetitions of deposition and sputtering can be increased. The inner metal dielectric layer formed by high-density plasma chemical vapor deposition includes Nanbundo Plasma Undoped Silica Glass (HDP_USG) and high-density plasma fluorosilicon. There are two types of glass (HDP-FSG). Next, the process of HDP-USG will be described with reference to Figures u ~ κ. First, referring to FIG. 1A, a substrate 100 including a semiconductor device is provided. Next, a metal layer 110 is formed on the substrate 100. Please refer to FIG. 1B. First, the lithography process and the etching step are used to define the metal layer 110 to form a metal interconnect with a specific pattern. Please refer to FIG. 1C. Using high-density plasma chemical vapor deposition, a metal dielectric layer 12 in undoped silica glass (USG) is formed to fill the area between the metal interconnect structures and cover the metal. Interconnection structure. H D P-C V D > In-product metal dielectric layer has excellent trench filling performance, which can form good isolation in ultra-large integrated circuits with narrow line width or high component density. After that, the portion to be used as a plug (ρ 1 ug) such as a tungsten plug can be removed by appropriate lithography technology in the formed inner metal dielectric layer, and the material constituting the plug base can be deposited. '以 回 # ( etchback) technology, such as chemical mechanical polishing (CMP), removes unwanted plugging material, which can be performed in the next process step

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In the case of m 丨 electric constant (dieiectrie ⑶nstant) is usually greater than 4.0 = inner metal dielectric layer, especially in recent semiconductor technology toward '18 .18, the development trend, the use of USG as the inner metal dielectric is easy to generate strings The problem of cross talk, and often left on the surface of tungsten residues or other metal residues difficult to remove, in the subsequent process to produce electrical arcing effect and cause damage to the wafer. In addition, the manufacturing process of the metal dielectric layer in hdp_usg is likely to cause structural fragmentation on the wafer, which is another problem to be solved. The dielectric constant of fluorosilicone glass (FSG) is about 3.5, which is smaller than that of the USG, and it is not easy to have the problem of cross talk. However, the doped ions contained in FSG are easy to diffuse outward, especially the inner metal dielectric layer is easily penetrated due to the infiltration of the underlying metal and components. Therefore, PE-CVD is usually used before forming the inner metal dielectric layer in FSG. Method to deposit a high silicon rich oxide (SR0) layer on the metal interconnect structure to prevent the ions in the FSG from diffusing outward. In some cases, a layer of SR0 is added to the upper layer of the FSG to prevent ions from diffusing upward. Next, the processes of HDP-FSG will be described with reference to Figures 2A to 2D. First, please refer to FIG. 2A to provide a substrate 200 including a semiconductor device. Next, a metal layer 210 is formed on the substrate 200. Referring to FIG. 2B, the metal layer 210 is first defined using a lithography process and an etching step to form a metal interconnect 212 with a specific pattern. Referring to FIG. 2C, a SR0 layer 220 is formed by PE-CVD to cover the surface of the wafer. Next, please refer to FIG. 2D, and use HDP-CVD to form a metal interposer in FSG.

531841 V. Description of the invention (4) The electric layer 2 3 0 fills the area between the metal interconnect structures and covers the metal interconnect structures. Finally, please refer to FIG. 2E. At this time, an upper layer of SRO 240 may be deposited by PE-CVD on the inner metal dielectric layer 230 as required. Next, the plug can be manufactured as described above, and the subsequent processes can be performed. SRO is traditionally formed by PE-CVD, which means that wafers must be placed in different reactors, which reduces the throughput of the entire process. Similar to HDP-USG, the metal dielectric layer in HDP-FSG often leaves tungsten residues or other metal residues that are not easy to remove on the wafer surface. 'The arc voltage effect is generated in subsequent processes and the wafer is damaged. The process also often causes the structure on the wafer to crack and reduce product yield. Object and summary of the invention: In order to improve the above problems, the inventor proposes a method of forming an SRO layer by HDP technology in situ, and simultaneously performing HDP-CVD of the inner metal dielectric layer with a step-wise enhanced bias (bias). . Next, a specific implementation of the present invention will be described with reference to an embodiment and FIGS. 3A to 3E '. Embodiment: According to the manufacturing method of the present invention, please refer to FIG. 3a, a semiconductor substrate 300, such as a stone evening substrate, on which any desired semiconductor element can be formed. For simplicity, only a flat surface is used here. The semiconductor substrate 300 indicates that a metal layer 310 is formed thereon. Please refer to FIG. 3B ′, first define the metal layer 310 using a lithography process and an etching step to form a metal interconnect gig with a specific pattern. Please refer to FIG. 3C for the synchronous high-density vapor deposition (HDp-CVD) pattern.

0503-6911TWF (N); TSMC2001-0668; Isabelle.ptd Page 8 531841 V. Description of the invention (5) A high silicon rich oxide (SRO) 32 0 is covered on the wafer surface . Among them, HDP-CVD uses oxygen (〇2) and silicon methane (Si H4) as reactants to deposit a dielectric layer on the surface of a substrate 300 containing metal interconnects 312, and at the same time, it is sprayed with argon (Ar) plasma. In order to remove part of the metal dielectric layer protrusions located on the edges of the metal interconnects 3 1 2 and between the trenches. This reaction is based on a pressure lower than 0.1 T 〇rr, preferably from 1 mt 〇rr to 10 mtorr, power greater than 3 0 0 W, more preferably 3 5 0 to 5 0 0 W, at about Performed at a temperature of 300 ° C (25 (PC ~ 350 ° C)), the formed SR0 layer 320 has a resistance of 1.52 +/- 0.015, and its thickness is preferably between 100 and 250A. Because The SR0 layer 32 0 is formed in a situ manner using HDP-CVD, so the wafer does not need to be placed back and forth between different reaction tanks to perform the process of the inner metal dielectric layer, which not only saves time, but also avoids The error and contamination that may occur due to the replacement of the reaction tank can effectively improve the yield. Next, referring to the 3D diagram, HDP-CVD is used to form a metal dielectric layer 2 3 0 in a fluorosilicon glass (FSG) to fill the metal. The area between the interconnect structures is overlaid on the SR0 layer 320. The HDP-CVD system prior to the deposition stepwise strengthens its bias voltage, preferably the high-density electrode of the inner metal dielectric layer. The bias voltage in the slurry vapor deposition process is divided into 2-8 stages to enhance it to the highest value, such as 0 W, 500 W, 1250 W, 2000 W The 2800 W method is strengthened to the required bias voltage, such as 3 100W. This step-wise bias enhancement method effectively avoids structural fragmentation on the wafer and the metal dielectric in the HDP-FSG formed by it Tungsten residues or other metal residues that are not easy to remove will not be left on the surface of the layer, which solves the problem that these residues cause arc voltage effects in subsequent processes and cause damage to the wafer.

0503-6911TWF (N); TSMC2001-0668; Isabelle.ptd Page 9 531841 V. Description of the invention (6) 'Finally, please refer to Figure 3E. At this time, if necessary, use PE- on the inner metal dielectric layer 230. An upper layer of SRO 240 is deposited by CVD. Then you can make the plug. In the formed metal dielectric layer, the material intended to be used as a plug, such as a tungsten plug, is removed by appropriate lithography technology. The material is removed by etch-back technology such as chemical mechanical polishing. Divide, you can proceed to the next process. The cores treated in the above examples were detected to be caused by crane metal residues or other metal residues: voltage; and the product yield was improved in some cases. Rich money in terms of not reducing productivity Although the present invention has been limited to the present invention by a preferred embodiment, 'any person skilled in the art is not intended to use it within the scope, and can be modified and retouched: away from the spirit of the present invention Defined by the scope of patent application.

0503-6911TWF (N); TSMC2001-0668; Isabelle.ptd Page 10 531841 Figures 1A to 1C are schematic cross-sectional views of the metal dielectric layer process in traditional HDP-USG; Figures 2A to 2E FIG. 3 is a schematic cross-sectional view of a conventional metal dielectric layer process in HDP-FSG; and FIGS. 3A to 3E are cross-sectional schematic views of a metal dielectric layer process in HDP-FSG according to an embodiment of the present invention. Explanation of symbols: 100, 2000, 300 ~ semiconductor substrate; 110, 210, 310 ~ metal layer; 112, 212, 312 ~ metal interconnect; 120 ~ HDP-USG; 220, 320 ~ SRO; 230, 330 ~ HDP-FSG; 240, 340 ~ upper SRO.

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Claims (1)

531841 VI. Scope of patent application 1. A method for manufacturing an inner metal dielectric layer is suitable for a semiconductor substrate. The semiconductor substrate has a metal interconnect structure with a pattern ^. The above method includes the following steps: Deposited on the semiconductor substrate to form a high silicon-containing oxide layer simultaneously, and the metal interconnect structure is not formed; and a high-density plasma vapor deposition is used to form an internal metal dielectric layer on the high silicon-containing oxide layer; And fill the area between the metal interconnect structures, where the bias voltage in the high-density plasma vapor deposition ^ = is enhanced in a progressive manner 0 2 · Inner metal intermediary as described in item 1 of the scope of patent application ^ The manufacturing method of the electric layer, wherein the high-density plasma vapor deposition of the high silicon-containing oxide layer is performed under a pressure of lmtorr to 10mtorr. 3. The manufacturing method of the inner metal dielectric layer as described in item 1 of the scope of the patent application, wherein the high-density plasma vapor deposition of the high silicon-containing oxide layer is performed at a power of 3500 to 5000W. 4. The method for manufacturing an inner metal dielectric layer as described in item 丨 of the patent application scope, wherein the high-density plasma vapor deposition of the high silicon-containing oxide layer is performed at a temperature of 250 ° C to 35 (TC) ' Method 5 · The producer of the inner metal dielectric layer as described in item 1 of the scope of patent application, wherein the thickness of the high silicon-containing oxide layer is 100 to 2500 t. Method for making the electric layer: The bias voltage in the high-density electrical equipment vapor deposition process of the inner metal dielectric layer is divided into 2 to 8 stages and further enhanced to the highest value. 7. If the scope of patent application is the first The manufacturer of the inner metal dielectric layer described in item 0503-6911TWF (N); TSMC2001-0668; Isabelle.ptd 531841 VI. Application for Patent Scope Law ′ Among them, the metal intermetallic lightning within 5 hours is up to a & 8. Such as the application ## ^ n two, " Ajiedu Plasma Fluorosilicon Glass. Law Cheng more packages :: When the production of the inner metal dielectric layer is described above, the upper layer containing ㈣If is redundantly formed on the inner metal dielectric layer, the method of making the 9 1/2 = layer is suitable for semiconductors The substrate method includes the following steps: Z, a metal interconnect structure that is described above, and the above-mentioned method is a high-density electrical number. The v- > d > phase is a phase that is accumulated on the semiconductor substrate. Simultaneous formation-same ": an emulsified layer and covering the metal interconnect structure; and a plasma deposited on the high silicon-containing oxide layer with rhenium plasma to form an internal gold f ^ electrical layer, and trench filling The area between the metal interconnect structures, in which the A-nanxicity plasma vapor deposition process is performed at a pressure of 1 mt 〇rr to 10 mt rr, an electric power of 350,000 to 50000W, and a temperature of 25 (The temperature is between TC ~ 350 ° C, and its bias is enhanced in a gradual manner. 1 0 · The method for manufacturing an inner metal dielectric layer as described in item 9 of the scope of patent application, wherein the inner metal dielectric The bias voltage in the high-density plasma vapor deposition process of the electric layer is divided into 2-8 stages to further enhance the highest value of i. 0503-6911TWF (N); TSMC2001-0668; Isabelle.ptd page 13