TW522517B - Method of forming copper damascene structure on semiconductor substrate - Google Patents

Abstract

A method of forming a copper damascene structure on a semiconductor substrate comprises: forming a dielectric layer on a semiconductor substrate; etching the dielectric layer to form an opening on the dielectric layer, in which the opening is used to expose the upper surface of the semiconductor substrate; forming a barrier layer on the sidewall of the opening and the exposed upper surface of the semiconductor substrate, in which the temperature in forming the barrier layer is higher than 250 DEG C to reduce the structural stress of the barrier layer; forming a copper crystal seed layer on the upper surface of the barrier layer; performing an electrochemical plating (ECP) reaction to form a copper layer on the upper surface of the copper crystal seed layer and filling the opening; performing a chemical mechanical polishing on the semiconductor substrate to remove a portion of the copper layer, the copper crystal seed layer and the barrier layer, on the upper surface of the dielectric layer, and defining a copper damascene structure in the opening.

Description

Field of the Invention: The copper damascene structure is particularly related to the effective reduction of the barrier metal layer. This invention relates to a semiconductor process. ^ A related process in the fabrication of copper damascene structure stress. Background of the invention: (ΙΙΤ τ semiconductor The industry continues to progress. In the trend of ultra-large integrated circuits, each I * is 7 in line with the design of high-density integrated circuits, which has been continuously reduced by 1, and the Shidao Gong has been reduced to sub-micron. When carrying out related semiconductor manufacturing processes, they often encounter industrial difficulties and the complexity of the process. One:: and the electronic connections used to connect these components 4 = Into: a specific function of the South. Therefore, the integrated circuit The performance depends on the performance and reliability of the parts: The electrical signals between countless precision metal inner bodies and Kushiro delivery components are required. Especially as the product shrinks, the current integrated circuit design has been Toward multiple, but in the process of multi-metal interconnection, due to the limitation of the resolution, the error of the exposure focus (J? Cuscus), the image; + accuracy and -Resolution (Resolution) and the available space enlargement / reduction of

522517 V. Description of the Invention (2) — The technology related to the damascene process has been widely developed and used. In addition, by using a single damascene or dual damascene 2 technology, multiple metal inter-connections can be manufactured more accurately and carefully. Generally speaking, the technology of the dual damascene structure can be used to synchronize the trench connection on the semiconductor substrate and the conductive plug connected to the semiconductor substrate. In this way, in addition to effectively improving the accuracy of defining the connection pattern of the integrated circuit, it can also greatly improve the reliability and yield of the integrated circuit. Therefore, the mosaic structure is widely used in the process of interconnecting large integrated circuits. In addition, it has excellent conductivity and is engraved with a structure that often forms a semiconductor element. It also encounters π spikes between atoms and the silicon substrate. ”As the element shrinks, it is easy to make the previous semiconductor Copper metal with low industry and copper metal have lower connection structure. In terms of traditional semiconductor manufacturing process, aluminum is cheaper to manufacture and can be arbitrarily considered as the industry ’s priority. The concentration of wires is increasing, and many metals are used. Difficulties. For example, inter-diffusion occurs in the material (inter-d and lead to poor contact of the I-Lu line. Hours, due to the "short-to-medium aluminum connection structure produced by electro-migration" often try to use conductivity instead of traditional The electromobility of heavily used aluminum and gold is settling with coping metal materials. However, Shao Lai is used as a high temperature environment if fus i on In addition, when the aluminum road is caused. It is therefore high and electrical. It is especially used for The semiconductor is due to its product and corrosion. As the connection is connected, aluminum), and the atomic shift of the aluminum wire, the apparent resistance ratio is due to the system process 522517.

Article No. of the Social Organization: The picture shows that the copper wire is made in the current technology. In the illustration, "Provided-Semiconductor Substrate 2: On the conductive substrate 10, there are layers and various elements that provide connections, forming a dielectric layer 12 on the semiconductor substrate, and using lithography = An opening is formed in the dielectric layer 12 to expose the upper region of the semiconductor substrate (not shown in the figure). Then, along the surface of the opening, the required: barrier layer 14 is formed. After the barrier layer 14 is formed, Forming—a copper seeding layer 15 is formed on the upper surface of the barrier layer 14. Then, a chemical plating (ECp) process can be used to form a copper layer on the semiconductor substrate 10, the dielectric layer 12, and Above the copper seed layer 15 and filled in the above-mentioned openings. Then, a chemical mechanical polishing (CMp) process is used to remove the barrier layer above the dielectric layer 12 and the copper seed layer 5 and The copper layer defines the copper damascene structure 16 located in the opening. It is worth noting that in the process of making this copper damascene structure 16, a large number of chemical reactions are used, such as chemical plating reaction and chemical mechanical polishing reaction. Is on the upper surface of the defined copper mosaic structure 16 Is often eroded by the chemical materials used, resulting in a corrosion phenomenon 18 as shown in the first figure. That is, the copper damascene structure 16 will be recessed and damaged. Surface. As a result, the yield and reliability of the connection components are greatly reduced when the Cu dual damascene structure is manufactured.

522517 V. Description of the invention (4) Purpose and summary of the invention: The main purpose of the body idi is to provide-a kind of copper inlay structure for semi-conductor akisaki. The purpose is to provide-a kind of copper inlaying process, which can have-inlay structure Related process of surface corrosion degree. Barriers ί ΐ2: One purpose is to provide a manufacturing method for effectively reducing the structural stress of the barrier layer in the copper mosaic structure. Then, the following "Methods for Manufacturing Copper Mosaic Structures on Semi-Substrates" includes the formation of the second electrical layer === the formation of a dielectric layer on a conductive substrate · 11. Then, the bottom layer is etched into the electrical layer, and the opening is used to expose the upper surface of the semiconductor conductor substrate. 1 middle protection into resistance two: the side wall of the opening and the exposed half. (: Used to lower the handle 2: The temperature of the conductive layer is about 250 ~ 40. "The structural stress of" ΪΓΓ !. In addition, ... form a barrier 丄 'to reduce the stress between barrier layers. Also, form a copper seed layer on Above the barrier layer: Layer: The temperature is lowered. Then the reaction is performed to form a copper layer on the copper seed / ° and chemical plating is performed. However, the upper surface of the rod Λ is formed on the semiconductor substrate and filled in the expulsion located at The upper part of the dielectric layer ::; Ding Hua :, mechanical polishing process: to define the copper mosaic structure in the opening. "5 said seed layer and barrier layer" and page 7 V. Description of the invention ( 5) Detailed description of the invention: The bottom of the body provides a new method for forming a copper mosaic structure in a semiconducting blind: L! In the mouth: Among them, by forming a barrier layer on the surface of the opening, the structural stress Γ L layer is thermally tempered Program, which can effectively reduce the intervening knots == the chemical machine used in the definition of the copper inlaid structure = grinding process, can effectively reduce the corrosion phenomenon due to excessive structural stress. In addition, you can also improve the production The temperature sound of the barrier layer reduces the effect of its structural stress. The details of the present invention are as follows: Please refer to the second figure as follows, first provide a material with a crystal orientation of &lt; 100 &gt;. In general, other types of semiconductor materials, such as gallium arsenide, germanium (ge) 〇ianium) or silicon on insulator (SOI) on the insulation layer can be used as semi-amplifier substrates. In addition, the characteristics of the surface of the semiconductor substrate will not cause a special influence on the present invention. It is also possible to choose <11 〇> based on its crystal orientation. Next, a dielectric layer 22 is formed on the semiconductor substrate 20 to produce an absolute. Here it is explained that before the dielectric layer 22 is formed, it has been fabricated halfway. Various active components, passive components, and peripheral circuits required for integrated circuits are described. In other words, on the surface of this semiconductor substrate 2 (), ^ /

The function and material layer of the fighter. In a preferred embodiment t ′, ... method (CVDh siliconized or siliconized). For example, a chemical vapor deposition force T ′ tetrahydrochloride (Li) can be used at a temperature of about ˜80 ° C. &gt; 敎: · to, ΐ〇ΓΓ to form silicon oxide. Or, you can also use two ways to make silicon oxide. As for silicon nitride can be formed in a furnace of about 400 to 'and the reaction in the process The gases are krypton, μ, and 3. In addition, '&gt; Tetraethylsilicate (TEOS) can be used as the reaction material 1 and oxygen atoms are added' to form fluorosilicon (FSG) by chemical vapor deposition (LpcvD). The dielectric layer 22 described above. Also, as the dielectric layer 22, undoped silica glass (USG) may be used. Then, the f-portion pattern 24 can be defined on the dielectric layer 22 by conventional lithography and etching techniques to expose the upper surface of the semiconductor substrate 20. Generally, a photoresist is first formed on the dielectric layer 22 to define an opening pattern, and an opening pattern 24 is defined on the dielectric layer 22 by performing lithography and #etching procedures. In a preferred embodiment, plasma etching can be used to define the opening pattern 24. Among them, the etchant used to remove silicon oxide can be selected from dagger, CHF3 / CF4, CHF3 / 02, CH3CHF2, cf4 / o2. As for the etchant used to remove silicon nitride, cf4 / h2, chf3 or CH3CHF2 can be selected. Still referring to the third figure, a barrier layer 26 is then formed on the sidewall of the opening pattern 2 4 and the upper surface of the exposed semiconductor substrate 20 to prevent diffusion of the copper layer and the dielectric layer 22 and the semiconductor substrate 20 produced later. Phenomenon, which produces a spiking effect. In the preferred embodiment, a barrier layer 26 is formed

522517 V. Description of the invention (7) The temperature is about 250 to 40 (). (: In order to effectively reduce the structural stress of the barrier layer 26. As for the material, a button (Ta), a nitride button (TaN), or any combination thereof can be selected. In addition, the preferred thickness of the barrier layer 26 is about It is 100 to 500 angstroms. Generally, a nitridation process can be used to form the required nitride button layer. A sputtering process is first performed to deposit a tantalum layer on the opening 24. The sidewall and the upper surface of the semiconductor substrate 20 are formed in a n2 * NH3 environment through a high temperature treatment to form the required nitride button layer. In addition, a reactive sputtering process can also be used to form the nitride button layer. By bombarding the group of metals with plasma ions and passing in argon and nitrogen, the button atoms that are splashed by bombardment can react with the nitrogen atoms formed through the dissociation reaction and form a nitride button. Deposited on the surface of the semiconductor substrate 20. After the barrier layer 26 is formed, the semiconductor substrate 20 can be transferred to a cooling reaction chamber under a vacuum environment to perform a cooling process. After the semiconductor substrate 20 is cooled, 'Can form a copper seed layer (Cu s eedifig layer) 2 8 is on the upper surface of the early barrier layer 26. Among them, in a preferred embodiment, the copper seed layer 28 can be used. Well-known techniques such as physical vapor deposition (PVD) are used. ), Sputtering and the like, and have a thickness of about 500 to 2500 angstroms. Next, referring to the third figure, immerse the semiconductor substrate 20 in a sulfuric acid

Page 10 522517 V. Description of the invention (8) In a copper solution, a chemical plating (ECP) reaction is performed to form a copper layer over the copper seed layer 28 and fill the opening pattern 24. In general, the copper seed layer 28 can be electrically connected to the cathode of a power source, and the copper ions' in the copper sulfate solution can be reduced and deposited on the surface of the copper seed layer 28. That is, the copper forging can be deposited on the surface of the copper seed layer 28 through the electric forging process to form a desired copper layer. Then, a chemical mechanical polishing (CMP) process may be performed on the semiconductor substrate 20 to remove a portion of the copper layer and the copper seed layer 28 m 26 ′ located on the upper surface of the dielectric layer 22 and define a copper damascene structure 30 at the opening. Pattern 24 is the same. In addition to being used as a dielectric layer (via), the formed copper damascene structure 30 can also be called as a copper conductive plug). Worth paying attention to! The temperature of the barrier layer 26 is relatively high, which is caused by the structural stress ^ It will reduce the copper mosaic structure by 3 ° in the CMP process. After the barrier layer 26 is manufactured to reduce the structural stress: "It's 袅, the degree of temperament is to reach the tempering (anneaU ^). The temperature of the thermal annealing process is about 250 to the effect of its structural stress S /, ", to 60 minutes, and the barrier layer 26 is reduced.

$ 11 pages 522517 V. Description of the invention (9) For the recipient, please refer to the fourth to sixth drawings. This part of the drawing does not show the use of the method of the present invention in a single mosaic process. First, as shown in the fourth figure, a semiconductor substrate 50 is provided, and a dielectric layer 52 is formed on the semiconductor substrate 50. Next, a conventional lithography process can be used to define the contact holes thereon 'and a conductive plug 54 can be formed in the contact holes by using a chemical vapor deposition method or a physical vapor deposition method such as a coin plating process. Subsequently, a silicon nitride layer or a silicon oxynitride layer is formed on the surface of the dielectric layer 52 to be used as a stop layer 56. A dielectric layer 58 and an anti-reflection layer (ARC) 60 are sequentially formed on the upper surface of the stop layer 56. Among them, the anti-reflection layer 60 may also use silicon nitride, silicon oxynitride, or any combination thereof as its material. After the anti-reflection layer 60 is formed, a photoresist layer 62 can be formed thereon to define the trench pattern 64. Then, the photoresist layer 62 can be used as an etching mask to perform an etching process on the anti-reflection layer 60 and the electric layer 58 until the stop layer 56 is reached. In this way, the trench pattern 64 can be transferred into the dielectric layer 58. Then, a part of the stop layer 56 exposed by the trench pattern may be removed, and the upper surface of the conductive plug 52 and the dielectric layer 52 may be exposed. 〃 Please refer to the fifth figure. After the photoresist layer 62 is removed, a barrier layer 66 and a copper seed layer 68 can be sequentially formed on the upper surface of the trench pattern. Among them, when the barrier layer 66 is formed, as in the aforementioned method, the process temperature thereof can be increased to 25˜400 ° C. to reduce its structural stress. Or after forming the barrier layer 66

Page 12 522517 V. Description of the invention (ίο)-* — A thermal tempering process with a temperature of about 25 to 40 ° C and a time of about 3 to 60 minutes to reduce its structural stress. Next, an electroless plating reaction (ECP) is performed to form a steel layer 70 on the upper surface of the copper seed layer 68 and into the trench pattern. ′ Then, as shown in the sixth figure, a part of the copper layer 70, the copper seed layer 68, the barrier layer “and the anti-reflection layer 60 on the surface of the electrical layer 58 may be removed using a chemical mechanical polishing method. In this way, the copper mosaic structure 72 can be defined in the trench pattern. This copper mosaic structure 72 is a single mosaic structure (singie damascene), and can be used as a trench connection according to the defined trench pattern. This copper damascene structure 72 can be electrically conductive plugs 54 and can be electrically connected to the components on the semiconductor substrate 50. Next, please refer to the seventh to ninth figures, this part of the figure shows the method using the present invention In a dual damascene process, as shown in the seventh figure, a dielectric layer 52, a stop layer 56, a dielectric layer 58 and an anti-reflection layer (ARC) can be sequentially formed on the semiconductor substrate 50 in this order. 60. Then, a photoresist layer 62 may be formed thereon to define the contact hole pattern 65. Then, by using a conventional lithography process, the photoresist layer 62 is used as an etching mask to resist the reflective layer 60 and the dielectric layer. 58. Stop layer 56 is etched with the dielectric layer to define contact 65 therein. After the photoresist layer 62 is removed, as shown in FIG. 8, a photoresist layer 67 is newly defined on the anti-reflection layer 60, and the photoresist layer 67 has a trench pattern. And use photoresist layer 67 as

Page 13 V. Description of the invention (11) The etching mask is used to perform an etching process on the anti-reflection layer 60 and the dielectric layer 58 until the stop layer 56 is reached. As such, the trench pattern 69 can be transferred into the dielectric layer 58. Then, the exposed portion of the trench pattern 69 can be removed and the upper surface of the dielectric layer 52 can be exposed. Say

Referring to the ninth figure, after the photoresist layer 67 is removed, a barrier layer 66 and a copper seed layer 68 can be sequentially formed on the upper surface of the trench pattern 69 and the contact hole 65. Among them, when the barrier layer 66 is formed, its process temperature is increased to 250-400 ° C to reduce its structural stress. Alternatively, after forming the barrier layer 66, a thermal tempering process at a temperature of about 250 to 400 t: and a time of about 3 to 60 minutes may be performed to reduce the structural stress. Next, a chemical plating reaction (ECP) is performed to form a steel layer on the surface of the copper seed layer 68 and fill the pattern 69 and the contact hole 65. Then, by using chemical mechanical polishing 1, the copper damascene structure can be defined after removing part of the copper layer and copper seed layer on the surface of the dielectric layer 58: the layer 66 and the antireflection layer 60. " In the figure and the contact hole 65. The copper damascene structure 73 is a dual damascene, including the part of the trench connection.少 surname ΐ t: has many advantages. First of all, by reducing the barrier layer produced, it can effectively reduce the chance of generating corrosion on the copper J embedded surface in the chemical mechanical polishing process, and reduce the gayalr ^ c effect caused by structural stress. . In addition, after making the barrier layer, the cold cooing process performed can also maintain the deposited copper seed layer, so that it has better and more uniform characteristics, and is effective. Avoid the formation of the copper seed layer, resulting in agglomeration and fracture effects. Although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the inventive substance of the present invention, but only to this embodiment. For those skilled in the art, modifications made without departing from the spirit and scope of the present invention should be included in the scope of patent application described below.

Page 522 517 Brief description of the drawings Brief description of the drawings. The drawings will be easily understood, of which: The following detailed description combines the above-mentioned content and many advantages of the invention. The first figure is a semiconductor wafer. Forming a copper damascene junction on a semiconductor substrate. The second figure shows the sequential formation of steps on a semiconductor substrate for semiconductor wafers; a plan view showing the steps of constructing according to traditional techniques; a plan view showing the technology according to the invention | Steps with copper seed layer in the opening. The second picture is a cut-off car of a semiconductor wafer. The figure from U WH 4 shows the + step of forming a copper mosaic structure on a hand conductor substrate according to the technology of the present invention. &lt; Figures 4 and 6 are top views of the wearing surface of a semiconductor wafer. '· shows the steps of making a Cu single damascene structure on a semiconductor substrate according to the first embodiment of the present invention; and seventh to seventh ~ Ninth figure is a cross-sectional view of a semiconductor wafer, showing the steps of fabricating a Cu dual damascene structure on a semiconductor substrate according to a second embodiment of the present invention.

Claims (1)

522517 6. Scope of patent application 1. A method of manufacturing a copper damascene structure on a semiconductor substrate 'The method includes at least the following steps: forming a dielectric layer on the semiconductor substrate; and etching the dielectric layer to form An opening is formed on the dielectric layer, wherein the opening is used to expose the upper surface of the semiconductor substrate; ii) a barrier layer is formed in the sidewall of the opening and the exposed upper surface of the semiconductor substrate; The temperature is greater than 25 ° C in order to reduce the structural stress of the barrier layer; a copper seed layer is formed on the upper surface of the barrier layer; a chemical electricity mine (ECP) reaction is performed to form a copper layer on the copper seed layer Surface, and filled in the opening; and performing a chemical mechanical polishing process on the semiconductor substrate to remove a portion of the copper layer, the copper seed layer, and the barrier layer located on the upper surface of the dielectric layer, and A copper damascene structure is defined in the opening. 2. The method according to item 1 of the patent application scope, wherein before forming the dielectric layer on the semiconductor substrate, it further comprises the step of forming various elements or material layers on the semiconductor substrate. 3. The method according to item 1 of the patent application range, wherein the above barrier layer can be selected from the group (Ta), the nitride group (TaN), or any combination thereof, and the temperature at which the barrier layer is formed is about 250 to 40 ° C. 4 · The method according to item 1 of the scope of patent application, wherein the above-mentioned copper seeds 522517 6. Scope of patent application The layer has a thickness of about 500 to 2500 Angstroms. 5. The method according to item 1 of the patent application range, wherein the thickness of the above barrier layer is about 100 to 500 Angstroms. 6. The method according to item 1 of the scope of patent application, wherein after the barrier layer is formed, the semiconductor substrate may be subjected to a cooling process. 7 · The method according to item 1 of the patent application range, wherein the above-mentioned chemical electroforging procedure is immersing the semiconductor substrate in a copper sulfate solution, and electrically connecting the copper seed layer to the cathode wire so as to be located at The copper ions in the copper sulfate solution can be reduced and deposited on the surface of the copper seed layer. 8. The method according to item 1 of the scope of patent application, wherein the copper damascene structure is a dielectric interlayer copper connection (v i a). 9 · The method according to item 1 of the scope of patent application, wherein the copper inlaid structure is a copper conductive plug (pi ug). 10. A method of manufacturing a copper damascene structure on a semiconductor substrate, the method including at least the following steps: forming a dielectric layer on the semiconductor substrate; etching the dielectric layer to form an opening in the dielectric Layer, wherein the opening exposes the upper surface of the semiconductor substrate; Page 18 522517 6. The scope of the patent application forms a barrier layer on the side wall of the opening and the exposed semiconductor substrate. The surface is subjected to a thermal tempering process. The thermal tempering process includes The temperature is about 250 to 400 ° C to reduce the structural force of the barrier layer. A copper seed layer is formed on the upper surface of the barrier layer. ~ 'Chemical plating (ECP) reaction is performed to form copper. Layer on the upper surface of the copper seed layer and filled in the opening; and said chemical mechanical polishing process is performed on the semiconductor substrate to remove a part of the copper layer and the copper seed on the upper surface of the dielectric layer Layer and the barrier layer, and define a copper damascene structure in the opening. π. The method of claim 10, wherein before forming the dielectric layer on the semiconductor substrate ', it further comprises the step of forming various elements or material layers on the semiconductor substrate. 9 12. The method according to item 10 of the patent application range, wherein the above barrier layer can be selected from a button (Ta), a nitride button (TaN), or any combination thereof. 13. The method as claimed in claim 10, wherein the copper seed layer described above has a thickness of about 500 to 2500 Angstroms. 14. A method as claimed in item 10 of the patent scope, wherein the thickness of said barrier layer is about 100 to 500 Angstroms. 522517 6. Scope of patent application 15. For the method of applying for patent item No. 10, the above-mentioned thermal tempering procedure lasts about 3 to 60 minutes. 16. The method of claim 10, wherein the above-mentioned chemical plating procedure is to immerse the semiconductor substrate in a copper sulfate solution, and electrically connect the copper seed layer to the cathode wire so as to be located at The copper ions in the copper sulfate solution can be reduced and deposited on the surface of the copper seed layer. 17. The method according to item 10 of the scope of patent application, wherein the copper-embedded structure described above is a dielectric interlayer copper connection (v i a). 18. The method of claim 10 in the scope of patent application, wherein the copper inlay structure is a copper conductive plug. Page 20