TW469588B - Method for enhancing electromigration resistance of metal wire - Google Patents

Abstract

There is provided a method for manufacturing a metal wire structure on a semiconductor substrate, which includes the steps of: first, forming a trench and/or contact/via in a dielectric layer; then, forming an un-doped metal layer on the dielectric layer and filling the metal layer in the trench and/or contact/via; then, forming a cover layer on the dielectric layer and on the un-doped metal layer; then, performing a photolithography procedure to form a photoresist layer on the cover layer for defining a wire pattern; then, using the photoresist layer as a mask to perform an ion implantation on the un-doped metal layer; and finally, removing the photoresist layer to form a doped metal wire structure.

Description

469588 V. Description of the invention (1) Field of the invention: The present invention relates to a process of a dielectric interlayer metal connection (v 1 a) or a metal conductive plug (p 丨 ug) in a semiconductor process, and particularly relates to a process having a southern reactance. Related processes of Electromigration Resistance (Electromigration Resistance) copper connection or steel conductive plug between dielectric layers. Background of the Invention: With the continuous advancement of semiconductor technology, the current integrated circuit design has developed towards multiple metal interconnects. In the related process of traditional multi-metal interconnects, aluminum metal materials have become the preferred wire materials in the industry because of their excellent electrical conductivity, low cost, and the ability to arbitrarily deposit and etch. However, with the increasing accumulation of semiconductor devices, the use of aluminum metal as a contact structure for wiring has also encountered many difficulties. For example, in a high-percent environment, aluminum atoms easily inter-diffusion with the silicon substrate, and 'spiking' occurs and causes poor contact of the aluminum wire. In addition, when the size of the aluminum wire changes with When the device is downsized, the aluminum atom movement caused by "electromigration (£ 1" 1; "0_11] 41 ^ 1; 1010)" will easily short-circuit the fabricated aluminum wiring structure. > Therefore 'In the current semiconductor industry, often try to use copper metal with higher conductivity, lower resistivity and lower electromobility to replace the aluminum metal used in the wiring structure of traditional semiconductor processes Or aluminum alloy

469588 5. Description of the invention (2) (for example: aluminum-silicon steel alloy or aluminum-copper alloy), in order to improve the operating speed of the component and the reliability of the component. Let's take the first figure as an example to briefly explain the current method of making a copper connection structure as follows. First, a dielectric layer 12 is formed on a semiconductor substrate 10, where the semiconductor substrate 10 has various layers and various components that provide connections. Then, a lithography process is used to form an opening in the dielectric layer 12 to expose the connection area on the semiconductor substrate 10 (not shown in the figure). Then, a barrier layer is sequentially formed along the opening surface. 14 on the surface of the dielectric layer 12 and a copper seeding layer 16 on the surface of the barrier layer 14. Then, an electrical chemical plating (ECP) process can be used to form a A steel layer is filled above the semiconductor substrate 10, the dielectric layer 12, the barrier layer 14 and the copper seed layer 16 'and is filled in the above openings. Then, the chemical mechanical polishing (CMP) process is used to remove the dielectric layer 12 The upper barrier layer 14, the copper seed layer 16 and the steel layer define the copper connection structure 18 in the opening. However, because the accumulation of semiconductor components continues to increase, the above-mentioned production of the steel connection structure The width of the copper wire obtained by this method will become narrower and narrower. At this time, the copper atom movement caused by electromigration will also cause the copper wire to have an open effect. Therefore, how to improve the metal wiring 1. resistance to electromigration (E1ectro-migration Resistance) has become an urgent problem in the industry. Purpose and summary of the invention:

469588 V. Description of the invention (3) The purpose of the present invention is to provide a method for making a metal wire with high resistance to electromigration on a semiconductor substrate. A method for making a metal wire with high resistance to electromigration on a semiconductor substrate includes the following steps. A dielectric layer is first formed on a semiconductor substrate, and then the dielectric layer is etched to form trenches and / or contact holes / dielectric holes on the dielectric layer, wherein the trenches and / or contact holes / dielectric layers are formed on the dielectric layer. The hole is used to expose the upper surface of the semiconductor substrate, and then a barrier layer is formed on the trench and / or the sidewall of the contact hole / via hole and the exposed upper surface of the semiconductor substrate, and then a seed layer is formed thereon. The upper surface of the barrier layer is then subjected to a chemical plating (ECP) reaction to form an undoped metal layer on the upper surface of the seed layer, and filled in the trench and / or contact hole / interlayer hole, and then using chemistry Mechanical grinding process to remove part of the undoped metal layer, seed layer and barrier layer located on the upper surface of the dielectric layer, and define the metal wiring structure in the trench and / or contact — contact hole / dielectric layer In the hole. Next, a cover layer is formed on the dielectric layer, the seed layer, the barrier layer and the undoped metal layer, and then a lithography process is performed to form a photoresist layer on the cover layer to define a connection pattern. Then, using the photoresist layer as a mask, ion implantation is performed on the undoped metal layer, and finally the photoresist layer is removed to form a doped metal connection structure.

469588 V. Description of the invention (4) Detailed description of the invention: The present invention provides a method for improving the electro-migration resistance of an interlayer metal connection (v 丨 a) or a conductive plug (Electro-migration Res i stance). Among them, the improvement of the anti-electrical transfer ability of the above-mentioned interlayer metal connection or conductive plug is achieved by ion implantation of the undoped metal connection. The present invention is described in detail as follows.... With reference to the second figure 'First, a semiconductor substrate 2 of various active components, passive components, peripheral circuits, etc. required for fabricating integrated circuits is provided. It can be a < 1 0 〇 > or < i 丨 丨〉 crystal-oriented single crystal silicon or other kinds of semiconductor materials, such as gallium arsenide (GaAs), germanium (Ge) or silicon on the insulating layer Substrate (siliconon insuiatr, SOI), etc. Then, a dielectric layer 22 is formed on the semiconductor substrate 20 to generate an insulating effect. The dielectric layer 22 includes silicon oxide or silicon nitride. The method for forming silicon oxide includes using chemical vapor deposition (CVD) with tetraethyl silicate (TEOS) at a temperature of about 600 to 800. c 'pressure is formed between about 0.1 to 10 torr. Alternatively, it can be produced by a thermal oxidation method. For silicon nitride, y is about 400 to 450. It is formed in the furnace of c, and the reaction gases in the process are SiH4, LO and NHs. In addition, as the dielectric layer 22, tetraethyl silicate (TE0s) can be used as a reaction material and Xiangyuan + is added to form a gas-silicon glass (fsg) by chemical vapor deposition (LPCVD). . or

Page 7 469588 5. Inventor (5) can also use undoped silica glass (USG) as the above-mentioned dielectric layer. 22 = Then, the traditional lithography and lithography techniques can be used on the dielectric layer. An opening (contact / via hoie or trench) 24 'is formed on 2 2 to expose the upper surface of the semiconductor substrate 20. Generally, a photoresist is first formed on the dielectric layer 22 to define an opening pattern, and an opening 24 is formed on the dielectric layer 22 by performing a lithography and etching process. In a preferred embodiment, plasma etching can be used to form the openings 2 4 = Among them, the etchant used to remove silicon oxide can be selected from CC12F2, CHF3 / CF4 'chf3 / o2, ch3chf2, cf4 / o2. As for the etchant used to remove silicon nitride, cf4 / h2, chf3 or ch3chf2 can be selected. Please refer to the third figure, and then form a barrier layer 2 6 on the side wall of the opening 2 4 and the exposed semiconductor substrate 20 Surface to prevent subsequent diffusion of the conductive layer, the dielectric layer 22, and the semiconductor substrate 20, resulting in a spiking effect. The material of the barrier layer 26 can be selected from one of the following clusters: Is (Ta), tantalum nitride (TaN), titanium nitride (T i N), tungsten titanium (T i W), titanium (Ti) or any combination thereof, and the temperature at which the barrier layer 26 is formed is about 25 to 400 ° C, and its preferred thickness is about 100 to 50 angstroms. Generally, a nitridation process can be used to form the desired tantalum nitride layer. A sputtering process is first performed to deposit a tantalum layer on

469 58 8 5 * Description of the invention (6) The sidewall of the opening 24 and the upper surface of the semiconductor substrate 20 are formed in a N-NH fishing environment through a high temperature treatment to form the required tantalum nitride layer. In addition, the reactivity can also be used An annihilation process is performed to form a tantalum nitride layer. By bombarding tantalum metal with plasma ions, and passing in argon and nitrogen, the tantalum atoms spattered by the bombardment can react with the nitrogen atoms formed by the dissociation reaction and form tantalum nitride. Deposited on the surface of the semiconductor substrate 20. Then, a seed layer 2 (seeding 1 ayer) 2 8 is formed on the sidewall of the opening 2 4 and the upper surface of the exposed semiconductor substrate 20 and on the upper surface of the barrier layer 26 to strengthen the adhesion β of the subsequent plating. In a preferred embodiment, the material of the seed layer 28 may be copper, copper alloy (such as copper aluminum alloy, copper magnesium alloy, steel tin alloy, copper nickel alloy, etc.), and it may use physical gas It is formed by similar processes such as physical vapor deposition (PVD), subtraction; bonding, and the like, and has a thickness of about 500 to 250 angstroms. The formation steps of the barrier layer 26 and the seed layer 28 may not be performed, or only the formation steps of the seed layer 28 may be performed. Next, referring to the third figure, the semiconductor substrate 20 is immersed in a sulfuric acid-copper solution to perform an Electrochemical Chemical (Plating; ECP) reaction to form a conductive layer over the seed layer 28. And filled in the openings 2 4. In this preferred embodiment, the material of the conductive layer may be copper, which can reduce and deposit copper ions in a copper sulfate solution by electrically connecting the seed layer 28 to a cathode of a power source. Seed layer

469588

And copper atoms are deposited on the surface of the invention (7) 28. That is, by performing the plating process, the seed layer 28 is formed and a desired copper layer is formed. Then, a chemical mechanical polishing (CMP) was performed on the abundance of the conductor substrate 20 to remove a part of the conductive layer layer 28 on the upper surface of the electric layer 22 2 located on the surface of the Jiuxian 99u main paper. And the barrier layer 26, and set μ to visit her, $ electricity increase, Japanese and Japanese unopped Jin Qu, check the order of opening 2 4, install Φ master, A ^ five genus The material of the wire 3 0 ′ and the undoped metal wire 30 is self-made. Generally speaking, the formed husband is private ... Trapped shells already contain copper. ^ ± He doped metal connection 3 0 can be used as a conductive metal plug (ν i a), but also y s s… a can be used as a conductive plug (plug). Then, please refer to the figure of Trq ^ ~~, this part shows the method for improving the anti-electrical transfer ability of the metal connection of the present invention. f First, a capping layer (capping: ^ layer 32 is formed on the undoped metal connection line 30 (as shown in the fourth figure), where the capping layer 32 includes a Sif siC or SiN / SiC composite layer 'is formed by a chemical method The vapor deposition method (Chemical vapor deposition; CVD) 'has a formation temperature of about 38-40 ° C and a thickness of about 300 ~ 100 Angstroms. Then, a conventional lithography process is used to form a The photoresist layer 34 is used to define a via pattern 37 on the cover layer 32, and the photoresist layer 34 is used as a mask for ion implantation to ion implant the undoped metal wiring 30. 36 to form a dopant metal connection 3 8 (as shown in the fifth figure). If the material of the undoped metal connection is copper ', the dopants of the above-mentioned ion implantation 36 can be selected from One of the following clusters Mg, Ab Pd, Zr, Sn, Cr 'Ta, Ni, Sn, Ti, and its concentration is about 1 0 15 ~ 1 0 17i on s / cm 2. 469 58 8 V. Invention Explanation (8) Finally, the photoresist layer 3 4 is removed, so that a doped metal wire 3 8 with better resistance to electromigration is obtained (as shown in the sixth figure). The metal wires 38 are protected by a cover layer 32, so the metal atoms in the doped metal wires 38 can be prevented from diffusing outward, and the doped metal wires 38 are prevented from being damaged by the lithography process described above. Of course Here, an inter-metal dielectric layer (IMD) can be formed on the doped metal wires 38 for subsequent fabrication of the wire structure. The advantage of the present invention is that the The metal wires are ion implanted to form a doped metal wire with better resistance to electromigration. In addition, since the doped metal wire formed is protected by a covering layer, doping can be prevented. The metal atoms in the high-quality metal connection are diffused outward, and the doped metal connection is prevented from being damaged by the above-mentioned lithography process. .If not all layers are covered, it will be covered and issued, and the cover will be covered. The protection has already been included in a warranty, but it is a mixed example. It must be performed, and it must be implemented. Please confirm it. The decorative layer of the cave layer is relatively ordinary. Jie Jin sees it as "," or "Wang Mingwei changes after the miscellaneous response"; "Whether it is treated as an independent change t or not, when the benefit is received, it is more exclusive or only for the structure. The conclusion is that the finish of the Shenchenggou Normal Line Shelter is linked to the security of the Shangming Institute. The quality of the fine gold for the pure gold is determined by sending the next layer of gold to determine the departure of the deities.

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11 m Page 11 469588 Brief description of the drawings Using the following descriptions with the following drawings will give a clearer understanding of the content and advantages of the present invention, where: The first diagram is a cross-sectional view of a semiconductor wafer, showing The step of forming a copper wiring structure on a semiconductor substrate by using technology. The second figure is a cross-sectional view of a semiconductor wafer, showing the steps of sequentially forming a barrier layer and a seed layer in an opening on a semiconductor substrate according to an embodiment of the present invention. _; The third figure is a cross-sectional view of a semiconductor wafer, showing a step of forming an undoped metal connection on a semiconductor substrate according to an embodiment of the present invention; the fourth figure is a cross-sectional view of a semiconductor wafer, showing one of the present invention The fifth embodiment is a step of forming a cover layer on an undoped metal connection; the fifth diagram is a cross-sectional view of a semiconductor wafer, showing the step of ion implanting the undoped metal connection according to an embodiment of the present invention; and The sixth figure is a cross-sectional view of a semiconductor wafer, showing a step of removing a photoresist layer to obtain a doped metal connection according to an embodiment of the present invention. Part number: semiconductor substrate 10; dielectric layer 12; barrier layer 14; copper seed fCu seeding layer 16;

Page 12 469588 Schematic illustration of copper wiring structure 18; semiconductor substrate 20; dielectric layer 22; opening 2 4; barrier layer 2 6; seeding layer 28; undoped Metal connection 30; capping layer 32; photoresist layer 3 4; ion implantation 3 6; via pattern 37; dopant metal connection 38 °

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Claims (1)

469588 6. Scope of patent application Patent scope: 1. A method for improving the anti-electrical migration ability of copper wiring in a semiconductor process, the method includes at least the following steps: forming a dielectric layer on a semiconductor substrate; etching the dielectric Layer to form a trench and / or contact hole / via hole on the dielectric layer, wherein the trench and / or contact hole / via hole is used to expose the upper surface of the semiconductor substrate; forming a barrier layer on the Sidewalls of trenches and / or contact holes / via holes and the exposed upper surface of the semiconductor substrate; forming a seed layer on the upper surface of the barrier layer; and performing an electroless plating (ECP) reaction to form an undoped copper layer On the upper surface of the seed layer and filling the trench and / or contact hole / interlayer hole; and performing a chemical mechanical polishing process on the semiconductor substrate to remove a portion of the upper surface of the dielectric layer. An undoped copper layer, the seed layer and the barrier layer, and defines a copper connection structure in the trench and / or contact hole / via hole; forming a cover layer on the dielectric layer, the crystal Over the seed layer, the barrier layer and the undoped copper layer; Performing a lithography process to form a photoresist layer on the cover layer to define a connection pattern; using the photoresist layer as a mask, ion implanting the undoped copper layer; and removing the photoresist layer, To form a doped copper connection structure. Page 14 469588 6. Application for Patent Scope 2. The method of the first scope of patent application, before forming the dielectric layer on the semiconductor substrate, it further includes forming various elements or material layers on the semiconductor substrate. step. 3. The method according to item 1 of the scope of patent application, wherein the material of the above barrier layer may be selected from one of the following clusters: tantalum (Ta), tantalum nitride (TaN), and titanium nitride (T i N) , Titanium Titanium (T i W), Titanium (T i), or any combination thereof. 4. The method according to item 1 of the patent application range, wherein the temperature at which the barrier layer is formed is about 25 to 400 ° C. 5. The method according to item 1 of the patent application range, wherein the seed layer described above has a thickness of about 500 to 2500 Angstroms. 6. The method according to item 1 of the patent application range, wherein the thickness of the above barrier layer is about 100 to 500 Angstroms. 7. The method according to item 1 of the patent application, wherein the above-mentioned chemical plating procedure is to immerse the semiconductor substrate in a copper sulfate solution, and electrically connect the seed layer to the cathode wire so as to be located in the copper sulfate solution. The copper ions can be reduced and deposited on the surface of the seed layer. Page 15 469588 6. Scope of patent application 8. For the method of the first scope of patent application, the above copper connection structure is a dielectric interlayer copper connection (via) or a copper conductive plug (plug). 9. The method according to item 1 of the scope of patent application, wherein the cover layer comprises a composite layer of SiN, SiC or SiN / SiC. 10. The method according to item 1 of the scope of patent application, wherein the thickness of the cover layer is about 300 to 100 angstroms. 11. The method according to item 1 of the patent application range, wherein the cover layer forming method includes a chemical vapor deposition (CVD) method. 12. The method according to item 1 of the scope of patent application, wherein the formation temperature of the cover layer is about 380-420 ° C. 1 3. The method according to item 1 of the scope of patent application, wherein the material of the seed layer comprises copper or a copper alloy. 14. The method according to item 1 of the scope of patent application, wherein the dopant of the above-mentioned ion implantation may be selected from one of the following clusters: Mg, A1Pd, Zr, Sn, Cr, Ta, Ni, Sn, Ti ° 1 5. The method according to item 13 of the patent application scope, wherein the above-mentioned copper alloy material Page 丨 6 4 6 9 5 8 8 6. Scope of patent application The quality can be selected from one of the following clusters: copper aluminum alloy, copper magnesium alloy, copper tin alloy, copper alloy or any combination thereof. 16. The method according to item I 4 of the scope of application for a patent, wherein the replacement concentration of the above-mentioned ion implantation is about 1015 ~ 100n s / cm2. 1 7. A method for improving the anti-electrical migration capability of a copper connection in a semiconductor process, the method includes at least the following steps: forming a trench and / or a contact hole / interlayer hole in a dielectric layer; forming a crystal A seed layer is on the upper surface of the dielectric layer, and is filled in the trench and / or the contact hole / via hole; performing an electroless plating (ECP) reaction to form an undoped copper layer on the upper surface of the seed layer, And filled in the trench and / or contact hole / via hole; performing a chemical mechanical polishing process to remove a portion of the undoped copper layer and the seed layer located on the surface of the dielectric layer; and Define a copper connection structure in the trench and / or contact hole / interlayer hole; form a cover layer on the dielectric layer, the seed layer and the undoped copper layer; perform a lithography process, Forming a photoresist layer on the cover layer to define a connection pattern; using the photoresist layer as a mask to ion implant the undoped copper layer; and removing the photoresist layer to form a doped layer Quality copper connection structure. Page 17 6. Scope of patent application 1 8. The method of item 17 of the scope of patent application, wherein the above copper connection structure is a dielectric wide copper connection (via) or a copper conductive plug (plug). 19. The method according to item 17 of the scope of patent application, wherein the cover layer comprises a SiN, SiC or SiN / SiC composite layer. 20. The method according to item 17 of the scope of patent application, wherein the method for forming the cover layer includes 4D chemical vapor deposition (CVD). 2 1. The method according to item 17 of the scope of patent application, wherein the material of the seed layer comprises copper or a copper alloy. 2 2. The method according to item 17 of the scope of patent application, wherein the quality of the above ion can be selected from one of the following clusters: Mg, Al, Pd, Zr, Sn, Cr, Ta, Ni, Sn, Tio 2 3. The method according to item 17 of the patent application scope, wherein before forming the seed layer, it further comprises forming a barrier layer on the upper surface of the dielectric layer, and filling the trench and / or contact hole / intermediate Layers of holes. 24. The method according to item 21 of the scope of patent application, wherein the material of the above copper alloy may be selected from one of the following clusters: copper aluminum alloy, copper magnesium alloy, copper tin alloy, copper nickel alloy or any combination thereof. 469588 VI. Application scope of patent 25. The method according to item 22 of the scope of patent application, wherein the dopant concentration of the above-mentioned ion implantation is about 1015 to 1017in s / cm2. 2 6. —A method for improving the anti-electrical migration capability of the copper connection in a semiconductor process, the method includes at least the following steps: forming a trench and / or a contact hole / interlayer hole in a dielectric layer; A doped copper layer on the dielectric layer and filled in the trench and / or contact hole / via hole; forming a cover layer on the dielectric layer and the undoped copper layer; lithography A program, forming a photoresist layer on the cover layer to define a connection pattern; using the photoresist layer as a mask, ion implanting the undoped copper layer; and removing the photoresist layer to form a Doped copper connection structure. 2 7. The method according to item 26 of the scope of patent application, wherein the above copper connection structure is a dielectric interlayer copper connection (via) or a copper conductive plug (plug). 2 8. The method according to item 26 of the scope of patent application, wherein the cover layer comprises a SiN, SiC or SiN / SiC composite layer. 2 9 · The method according to item 26 of the patent, wherein the method for forming the cover layer includes chemical vapor deposition; Page 19 6. Scope of Patent Application (CVD). 30. The method according to item 26 of the patent application scope, wherein before forming the undoped copper layer further comprises forming a seed layer on the upper surface of the dielectric layer, and filling the trench and / or contact hole. / Interstitial hole. -3 1. The method according to item 26 of the scope of patent application, wherein the dopant of the ion implantation can be selected from one of the following clusters: Mg, Al, Pd 'Zr, Sn, Cr, Ta, Ni, Sn Tio 3 2. The method according to item 30 of the patent application scope, wherein before forming the seed layer further comprises forming a barrier layer on the upper surface of the dielectric layer and filling the trench and / or contact hole / In the interstitial hole. 33. The method of claim 30, wherein the material of the seed layer comprises copper or a copper alloy. 34. The method according to item 31 of the scope of patent application, wherein the agronomic properties of the above-mentioned ion implants are about 1013 to 1017 ions / cm2. 35. The method of claim 33, wherein the material of the above copper alloy can be selected from one of the following clusters: copper aluminum alloy, copper magnesium alloy, copper tin alloy, copper nickel alloy, or any combination thereof. Page 20 4 b 9 5 B B________ VI. Scope of patent application 36. — A method for improving the resistance of the metal connection in the semiconductor process to electromigration, the method includes at least the following steps: forming a trench and / or a contact hole / A dielectric hole is formed in a dielectric layer; an undoped metal layer is formed on the dielectric layer and filled in the trench and / or contact hole / dielectric hole; a cover layer is formed in the dielectric layer And the undoped metal layer; a lithography process is performed to form a photoresist layer on the cover layer to define a connection pattern; the photoresist layer is used as a mask to ionize the undoped metal layer Implantation; and removing the photoresist layer to form a doped metal connection structure. 37. The method according to item 36 of the scope of patent application, wherein the metal connection structure is a dielectric interlayer metal connection (v i a) or a conductive plug (p 1 u g). 38. The method according to item 36 of the scope of patent application, wherein the cover layer comprises a SiN, SiC or SiN / SiC composite layer. 39. The method according to item 36 of the scope of patent application, wherein the cover layer forming method includes a chemical vapor deposition (CVD) method. 40. The method according to item 36 of the patent application scope, wherein before forming the undoped metal layer further comprises forming a seed layer on the upper surface of the dielectric layer, and I 4 6 9 5 B 8 6. Scope of patent application Fill in the trench and / or contact hole / via hole. 4 1. The method according to item 36 of the scope of patent application, wherein the material of the undoped metal layer includes copper. 4 2. The method according to item 40 of the patent application scope, wherein the seed layer is more wrapped before forming. It includes forming a barrier layer on the upper surface of the dielectric layer and filling the trench and / or contact hole / In the interstitial hole. 43. The method of claim 40, wherein the material of the seed layer includes copper or a copper alloy. 4 4. The method according to item 41 of the scope of patent application, wherein the dopant of the ion implantation can be selected from one of the following clusters: Mg, Al, Pd, Zr, Sn, Cr, Ta, Ni, Sn, Tio 45. The method according to item 43 of the scope of patent application, wherein the material of the copper alloy can be selected from one of the following clusters: copper aluminum alloy, copper magnesium alloy, copper tin alloy, copper nickel alloy, or any combination thereof. 46. If the method for applying item 4 to the scope of the application is applied, wherein the dopant range of the above-mentioned ion implantation is about 1015 to 10 " ions / cm2. Page 22