TWI286818B - Electroless plating of metal caps for chalcogenide-based memory devices - Google Patents

Electroless plating of metal caps for chalcogenide-based memory devices Download PDF

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TWI286818B
TWI286818B TW094138644A TW94138644A TWI286818B TW I286818 B TWI286818 B TW I286818B TW 094138644 A TW094138644 A TW 094138644A TW 94138644 A TW94138644 A TW 94138644A TW I286818 B TWI286818 B TW I286818B
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chalcogenide
conductive
conductive material
metal
opening
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TW094138644A
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Chinese (zh)
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TW200633131A (en
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Patricia C Elkins
John T Moore
Rita J Klein
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Micron Technology Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825—Selenides, e.g. GeSe

Abstract

A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming an opening in the insulating layer to expose at least a portion of the first conductive material, depositing a second conductive material over the insulating layer and within the opening, removing portions of the second conductive material to form a conductive area within the opening, recessing the conductive area within the opening to a level below an upper surface of the insulating layer, forming a cap of a third conductive material over the recessed conductive area within the opening, the third conductive material selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof, depositing a stack of a chalcogenide based memory cell material over the cap, and depositing a conductive material over the chalcogenide stack.

Description

I286818 九、發明說明： 【發明所屬之技術領域】 本發明係關於電化學沉積領域，且更特定言之係關於在 導電互連之上無電鍍一金屬覆蓋之方法，且係關於包含該 結構之以硫族化物為基礎之記憶體裝置。 【先前技術】 積體電路之性_徵及可#性6變得愈發偏來在積體I286818 IX. DESCRIPTION OF THE INVENTION: FIELD OF THE INVENTION The present invention relates to the field of electrochemical deposition, and more particularly to a method of electroless plating-metal coverage over a conductive interconnect, and relates to the inclusion of the structure A chalcogenide based memory device. [Prior Art] The nature of the integrated circuit _ 征和可# Sex 6 becomes more and more biased in the complex

電路或晶片上之半導體裝置之間載運電子訊號之通路及互 連的結構及屬性而定。積體電路製造之進展已引起密度、 在典型晶片上所含有之半導體裝置數量及速度增長。互連 結構及形成技術並未同樣快速發展，且愈發成為對於積體 電路之訊號速度的限制。 届如今，高性能積體電路通常具有多層金屬導線。該等金 :層藉由相對厚之例如二氧切之材料的絕緣層分開。通 等絕緣層製成以使該等金屬線路之間連接。經常 =#金屬導線盡可能保持於同一平面上以避免對於金 不當應力。經常使用鶴金屬检塞填充覆蓋第一金 屬塾或線路之絕緣層中之通路， 平i曰矣；^ L 使上覆膜仍在絕緣層之 卞一表面上。在無栓塞的情况 中以盥ΠΓ @姑 卜，上覆膜必將下沉至通路 T 乂與下層第一金屬接觸。 通#放置一盘下；紫一金凰 接觸之相荖/、0 屬觸之鈦(Ti)層作為隨後鎢 .安蜩之黏者層。接著該通路 (CVD)掣裎 > 拉 超话 ^吊、、，里由化學氣相沉積 >儿積之鎢金屬填充。卷丄 沉積製裎湘pq ^ 田向縱橫比通路待填充時， 氣私期間沉積於該通路侧辟 土上之鎢可夾緊開口，留下 105984.doc 1286818 一埋藏於通路内稱為"鎖孔，，之空隙。當通常使用化學機械 平坦化（CMP)製程除去來自CVD沉積製程之過量鎢時，可使 埋藏之”鎖孔”打開，在該等通路之頂部留下暴露之空隙。 該等空隙對隨後其它層之形成及層間之電連接有不利影 因此，此項技術仍需要提供金屬填充之高縱橫比通路之Depending on the path and interconnection structure and properties of the electronic devices carried on the circuit or wafer. Advances in the fabrication of integrated circuits have led to an increase in the density and number and speed of semiconductor devices contained on typical wafers. Interconnect structures and formation techniques have not developed as rapidly, and have become increasingly limited to the signal speed of integrated circuits. Today, high-performance integrated circuits typically have multiple layers of metal wires. The gold: layers are separated by an insulating layer of relatively thick material such as dioxo prior. An insulating layer is formed to connect the metal lines. Frequently =# metal wires are kept as close as possible on the same plane to avoid improper stress on gold. Frequently, a crane metal plug is used to fill the passage in the insulating layer covering the first metal or the line, and the upper film is still on the surface of the insulating layer. In the case of no plugging, the upper film will sink to the passage T 接触 in contact with the underlying first metal. Pass #Place a plate; Ziyi Jinhuang contact the phase 荖 /, 0 is the contact titanium (Ti) layer as the subsequent tungsten. Then the path (CVD) 掣裎 > pulls over the hang, and is filled with chemical vapor deposition > When the 丄 丄 裎 p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p Keyhole, the gap. When excess tungsten from the CVD deposition process is typically removed using a chemical mechanical planarization (CMP) process, the buried "keyholes" can be opened leaving exposed voids at the top of the vias. These voids have an adverse effect on the subsequent formation of other layers and the electrical connection between the layers. Therefore, the art still needs to provide a high aspect ratio path for metal filling.

方法，忒金屬填充之高縱橫比通路引起對用於半導體裝置 之製程之隨後層的良好電連接。 【發明内容】 更特定言之，根據本發明之一態樣 族化物為基礎之記憶體裝置中之一導 覆盍之方法，且包含在一基板上形成 且在該第一導電材料及該基板上沉積 層中形成一開口以暴露至少一部分第 絕緣層之上及該開口内沉積一第二導 導電材料除去以於該開口内形成一導 内之導電區域凹陷至一低於該絕緣層 本發明滿足該需要且提供—種在—導電栓塞、通路或互 連之上形成一金屬覆蓋之方法’該金屬覆蓋覆蓋或填充該 導電栓塞、通路或互連中之鎖孔且提供對於半導體裝置中 之隨後層的良好電接觸。該金屬覆蓋較佳由始、銀、銅、 金、鎳、纪'勤或其合金形成。金屬覆蓋較佳藉由在（例如） 鶴栓塞或互連之上無電鍍沉積金屬形成。本發明亦揭示使 用該金屬覆蓋構造之以硫族化物為基礎之記憶體裝置。 ，提供一種在一以硫 電互連上形成一金屬 一第一導電材料之層 一絕緣層。在該絕緣 一導電材料，且在該 電材料。使部分第二 電區域，且使該開口 之一上表面的水平。 105984.doc 1286818 =該開:敲凹陷導電區域之上形成—第三導電材料之覆 =°在該覆蓋上沉積—硫族化物材料，且在該硫族化物材 料之上沉積一導電材料以形成該記憶體裝置。 該第三導電材料係選自由下列各物組成之群：始、銀、 金:銅、錄、纪、麵及其合金。該第三導電材料之覆蓋較 佳错由無電鍍形成。在使用一無電鑛製程之處，無電鑛沉 積第一導電材料前可視情況活化該凹陷導電區域之表面。 • 在本發明之另一實施例中，提供一種在-以硫族化物為 基礎之記憶體裝置中之一導電互連之上形成一金屬覆蓋之 方法，且包含在一基板之上提供一絕緣層，該絕緣層其中 具有一開口且該開口暴露該基板上之至少一部分一第一導 電材料。一第二導電材料沉積於該絕緣層之上及在該開口 内。使部分第二導電材料除去以於該開口内形成一導電區 ^且使忒開口内之導電區域凹陷至一低於該絕緣層之一 ♦面的水平。—第二I電材料之覆蓋形成於該@ 口内之 _ w &導電區域之上。該第三導電材料較佳係選自由下列各 物、、且成之群·鈷、銀、金、銅、鎳、鈀、鉑及其合金。— 以硫族化物為基礎之記憶體單元材料之堆疊沉積於該覆蓋 之上且一導電材料沉積於該硫族化物堆疊之上。 在本發明之另一實施例中，提供一種在一以硫族化物為 基礎之記憶體裝置中之一導電互連之上形成一金屬覆蓋之 方法，且包含在一基板之上提供一絕緣層，該絕緣層其中 /、有開口且5亥開口暴露該基板上之至少一部分一第一導 包材料。一第二導電材料沉積於該絕緣層之上及在該開口 105984.doc 1286818 〇。使部分第二導電材料除去以於該開口内形成一導電區 /且使孩開口内之導電區域凹陷至一低於該絕緣層之一 上表面的水平。一鈷金屬之覆蓋形成於該凹陷導電區域之 ，二一以硫族化物為基礎之記憶體單元材料之堆疊沉積於 设蓋之上，且一導電材料沉積於該硫族化物堆疊之上。 在本發明之又-實施例中，提供—種在—以硫族化物為 基礎之記憶體裝置中之一鶊互連之上形成一金屬覆蓋之方 法:且包含形成-凹陷於一絕緣層之一開口内之鶴互連， ^稭由無電鍍沉積一金屬在該凹陷鎢層之上形成一金屬覆 盍。該金屬較佳係選自由下列各物組成之群：銘、銀、金、 鋼、鎳、鈀、鉑及其合金。 ，在本發明之又一實施例中，提供一種形成一用於半導體 =路之導電金屬互連之方法，且包含提供一具有形成於其 一 έ之半導體裝置的半導體結構，在該半導體結構之上形成 接、、、邑緣層，及在該絕緣層中形成—下至該半導體結構之溝 $ 4溝槽大體上用鎢填充，且該鶴凹陷至_低於該絕緣 表面的水平。一金屬覆蓋無電錢沉積於該凹陷鎢 =地’该金屬覆蓋較佳包含選自由下列各物組成之群 屬姑、銀、金、銅、錦、纪、4白及其合金。 本I月之又-貫施例中，提供一用於以硫族化物為基 2記憶體裝置之導電互連，且包含一在一半導體基板上 一二有開口之絕緣層’-在該開口中之凹陷鎢層，及 〆、烏層上之經無電錢沉積之金屬覆蓋。該金屬覆蓋較 匕括選自由下列各物組成之群之金U、銀、金、銅、 I05984.doc 1286818 鎳、鈀、鉑及苴人么 材 ’、σ、。一以硫族化物為基礎之記憶體單元 材枓之堆疊係在該霜雲 物堆疊之_^ 1之上，且一導電材料係在該硫族化In this way, the high aspect ratio via fill of the base metal causes a good electrical connection to subsequent layers of the process for the semiconductor device. More specifically, a method for guiding a germanium in a memory device based on one aspect of the present invention, comprising: forming on a substrate and on the first conductive material and the substrate Forming an opening in the upper deposited layer to expose at least a portion of the insulating layer and depositing a second conductive material in the opening to remove a conductive region formed in the opening to be recessed to a lower than the insulating layer. A method of satisfying this need and providing a metal cover over a conductive plug, via or interconnect. The metal cover covers or fills the keyhole in the conductive plug, via or interconnect and is provided for use in a semiconductor device Good electrical contact of the subsequent layers. The metal cover is preferably formed of the beginning, silver, copper, gold, nickel, Ji'er or its alloy. The metal cover is preferably formed by electroless deposition of a metal over, for example, a crane plug or interconnect. The present invention also discloses a chalcogenide-based memory device using the metal-covered construction. An insulating layer is provided which forms a metal-first conductive material on a sulfur interconnect. Insulating a conductive material, and in the electrical material. A portion of the second electrical region is made and the level of the upper surface of one of the openings is made. 105984.doc 1286818=The opening: forming a coating over the recessed conductive region - a coating of the third conductive material = depositing a chalcogenide material on the overlay, and depositing a conductive material over the chalcogenide material to form The memory device. The third electrically conductive material is selected from the group consisting of: beginning, silver, gold: copper, ruthenium, gems, faces, and alloys thereof. A better coverage of the third conductive material is formed by electroless plating. Where an electroless ore-free process is used, the surface of the recessed conductive region may be activated as it is before the first conductive material is deposited by the electroless ore. • In another embodiment of the invention, a method of forming a metal overlay over a conductive interconnect in a chalcogenide-based memory device is provided and includes providing an insulation over a substrate a layer having an opening therein and the opening exposing at least a portion of the first conductive material on the substrate. A second electrically conductive material is deposited over the insulating layer and within the opening. Part of the second conductive material is removed to form a conductive region in the opening and to recess the conductive region in the opening to a level lower than one of the faces of the insulating layer. - The coverage of the second I electrical material is formed over the _w & conductive area within the @口. The third conductive material is preferably selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof. - A stack of chalcogenide-based memory cell materials is deposited over the cover and a conductive material is deposited over the chalcogenide stack. In another embodiment of the present invention, a method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes providing an insulating layer over a substrate The insulating layer has an opening and a 5 hr opening exposing at least a portion of the first package material on the substrate. A second electrically conductive material is deposited over the insulating layer and at the opening 105984.doc 1286818. A portion of the second electrically conductive material is removed to form a conductive region within the opening and to recess the electrically conductive region within the opening to a level below an upper surface of the insulating layer. A cobalt metal coating is formed over the recessed conductive region, and a stack of chalcogenide-based memory cell materials is deposited over the cap and a conductive material is deposited over the chalcogenide stack. In still another embodiment of the present invention, there is provided a method of forming a metal capping on a germanium interconnect in a chalcogenide-based memory device: and comprising forming a recess in an insulating layer A crane in an opening is interconnected, and a metal is deposited on the depressed tungsten layer by electroless deposition of a metal. Preferably, the metal is selected from the group consisting of: silver, gold, steel, nickel, palladium, platinum, and alloys thereof. In still another embodiment of the present invention, a method of forming a conductive metal interconnection for a semiconductor=road is provided, and a semiconductor structure having a semiconductor device formed thereon is provided, in which the semiconductor structure is provided A trench, a germanium layer, and a drain layer formed in the insulating layer down to the semiconductor structure are substantially filled with tungsten, and the crane is recessed to a level lower than the insulating surface. A metal cover is deposited on the recessed tungsten = ground. The metal cover preferably comprises a group selected from the group consisting of: agglomerates, silver, gold, copper, brocade, 4, and alloys thereof. In a further embodiment of the present invention, a conductive interconnect for a chalcogenide-based 2 memory device is provided, and an insulating layer having an opening on a semiconductor substrate is included - at the opening The tungsten layer of the depression in the middle, and the metal on the enamel and the black layer are covered by the metal without electricity deposit. The metal cover includes gold, silver, gold, copper, I05984.doc 1286818 nickel, palladium, platinum, and ruthenium', σ, selected from the group consisting of the following. A chalcogenide-based memory cell stack is stacked on top of the frost cloud stack, and a conductive material is in the chalcogenization

在本發明之又-實施例中，提供—以處理器為基礎之系 美且包含一處理器及一與該處理器耦接之以硫族化物為 :礎之記憶體裝置。該以硫族化物為基礎之記憶體裝置包 在半導體基板上其中具有一開口之絕緣層，一在該 中之凹Pa鎢層’及一在該鎢層之上經無電鍍沉積之金 屬覆蓋。該金屬覆蓋較佳包含選自由下列各物組成之群之 土屬鈷、銀、金、銅、鎳、鈀'鉑及其合金。一以硫族 化物為基礎之記憶體單元材料之堆疊係在該覆蓋之上，且 一導電材料係在該硫族化物堆疊之上。 、b本如明之一特彳政係提供一種在一導電栓塞、通路 或互連之上形成一金屬覆蓋之方法，該金屬覆蓋保護該導 電栓塞、通路或互連且提供對於該半導體裝置中之隨後層 的良好電接觸。本發明之一特徵亦係提供一種使用該金屬 覆蓋構造之以硫族化物為基礎之記憶體裝置。自以下詳細 說明應顯而易見本發明之該等及其它特徵及優勢，該詳細 說明係結合說明本發明之例示性實施例之隨附圖式提供。 【實施方式】 應注意到：本文所述之製程步驟及結構並不形成製造積 體電路之完整製程流程。本發明之實施例可結合此項技術 中當w所使用之各種積體電路製造技術加以實踐。鑒於 此，僅當常規使用之製程步驟對於本發明之理解係必需 105984.doc -10- 1286818 時’彼等步驟才包含於本文之描述中。 本文使用之術語”其士 面之任何以半導體為二Γ具有一經暴露之半導體表 構：矽、咆緣，：’、▲之、構。該術語包含諸如下列結 ^雜半導^ 邦〇1)、藍寶石上邦〇s)、掺雜及無 二主道糟由一基礎半導體基底支撐之矽蠢晶層及其 匕、體結構。該半導體不需要㈣為基礎。該半導體可 為石夕錯或鍺。當本文提及I，基板，，時，可㈣先前之製程步 驟以在基礎半導體或基底中或基礎半導體或基底上 或接面。本文所使用之術語”之上"意謂形成於—下層表面 或基板表面之上。 現在參考圖式’其中相同之元件符號藉由相同參考數字 標明。圖1至圖9說明一種製造具有至少一個互連之以一硫 族化物為基礎之記憶體裝置之方法的—例示性實施例 裝置包含-金屬覆蓋。該製程開始於該積體電路結構_ 成之後。然而，該製程可應用於積體電路製造之任何階段。In still another embodiment of the present invention, a processor-based system is provided and includes a processor and a chalcogenide-based memory device coupled to the processor. The chalcogenide-based memory device comprises an insulating layer having an opening therein, a recessed Pa tungsten layer therein, and a metal overlying the tungsten layer by electroless deposition. The metal cover preferably comprises earth cobalt, silver, gold, copper, nickel, palladium 'platinum and alloys thereof selected from the group consisting of the following. A stack of chalcogenide-based memory cell materials is over the overlay and a conductive material is over the chalcogenide stack. The present invention provides a method of forming a metal covering over a conductive plug, via or interconnect that protects the conductive plug, via or interconnect and provides for the semiconductor device Good electrical contact of the subsequent layers. It is also a feature of the present invention to provide a chalcogenide-based memory device using the metal covering construction. The above and other features and advantages of the present invention will be apparent from the description of the appended claims. [Embodiment] It should be noted that the process steps and structures described herein do not form a complete process flow for manufacturing an integrated circuit. Embodiments of the present invention can be practiced in conjunction with various integrated circuit fabrication techniques used in the art. In view of this, only if the conventionally used process steps are necessary for the understanding of the present invention is 105984.doc -10- 1286818, the steps are included in the description herein. As used herein, the term "anything of a semiconductor surface is a semiconductor having an exposed semiconductor structure: 矽, 咆,: ', ▲, 。. The term encompasses the following semi-conducting ^ 〇 1 ), sapphire, s), doped, and sinusoidal doped crystals supported by a base semiconductor substrate and its 匕, body structure. The semiconductor does not need to be based on (4). Or 锗. When reference is made herein to I, the substrate, the fourth process steps may be used in the base semiconductor or substrate or on the base semiconductor or substrate or junction. The term "above" is used herein to mean On the underlying surface or on the surface of the substrate. Referring now to the drawings, wherein like reference numerals refer to the 1 through 9 illustrate a method of fabricating a thioate-based memory device having at least one interconnect - an exemplary embodiment apparatus comprising - metal cladding. The process begins after the integrated circuit structure. However, the process can be applied to any stage of integrated circuit fabrication.

出於簡化之㈣’本發明之實施例參考一上部金屬化層加 以描述。 圖1至圖9說明一經部分製造之積體電路結構1〇，其具有 一基板11及共同以13展示之複數個經製造之層。電連接以 下電路中之一或多個層或裝置的一系列導電區域21藉由習 知技術形成於遠電路結構上。儘管未展示，但是應瞭解積 體電路結構10可含有電晶體、電容器、字線、位元線、主 動區域或製造於基板1 1之上之層1 3中之類似元件。 如圖2所示，一絕緣層20提供於結構1〇之上。絕緣層2〇 l〇5984.do< 1286818 較佳包括矽酸四乙酯（TE0S)或例如硼磷矽玻璃（bpsg)、硼 矽玻璃（BSG)之其它介電材料或其它非導電性氧化物（摻雜 及無摻雜）、氮化物及氮氧化物。自身可由多層形成之絕緣 層20厚度較佳為約5,000埃至約2〇,〇〇〇埃。如圖3所示，至少 一些開口 22提供在互連將與在結構丨〇之最上面部分中提供 之導電區域2 1電通信之處。 再次參考圖3，在絕緣層20中使複數個例如互連溝槽之開 • 口 22圖案化且蝕刻。使開口 22對準以暴露部分導電區域 21如圖4所不，一視情況之黏著層24沉積於結構1〇之表面 上以使其保形覆蓋絕緣層2〇且將互連溝槽22排列成線。如 此項技術中所習知，可使用視情況之黏著層24以改良導電 區域21與隨後所沉積之導電材料之間之結合。視製造裝置 所用之材料而定，應存在不需要黏著層24的情況。 視情況之黏著層24較佳由一例如鈦（Ti)之難熔金屬形 成。如圖4所示，在一實施例巾，一視情況之^薄膜24可使 • ㈣理氣相沉積（PVD)、化學氣相沉積（⑽）或原子層沉積 (八1^0)來/儿積。然而，任何合適之材料皆可用於該黏著層， 例如氮化鎢、鈕化鎢、鈕矽氮化物或其它三元化合物。視 ί月况之黏著層24厚度較佳為約1〇〇埃至約5〇〇埃，且更佳為 約200埃。 見多考圖5 ’較佳包括鎢之導電互連材料形成於結構ί 〇 〇上及互連溝槽22中。該等導電互連川可使用此項技術中 白决之任何技術形成，該等技術包含（例如技 【ί兩種技術白引起溝槽22之保形填充。然而，視溝槽之 105984.doc 1286818 縱橫比及寬度而定，該等保形沉積技術可引起在該鎢栓塞 内形成鎖孔。通常，互連30應具有約！”^埃至約5,〇〇〇埃之 厚度，且較佳約2,000埃之厚度。現參考圖6，使來自導電 互連30之過量材料除去。通常，該材料使用此項技術中熟 知之化學機械平坦化（CMP)技術除去。理想地，導電互連刊 與絕緣層20之一上表面25大體在同一水平時，停止對過量 材料之除去。 現參考圖7,使導電互連30進一步平坦化或過度研磨以得 到一至絕緣層20之上表面25以下一合適距離的凹形或凹 陷。任何適於使互連材料凹陷之方法皆可使用。舉例而言， 導電互連30可經選擇性過度研磨、化學機械平坦化、濕式 蝕刻或乾式蝕刻使該互連材料凹陷於溝槽22内且低於絕緣 層20之表面。通常，較佳係約2〇〇埃至約5〇〇埃之凹陷。 在一實施例中，該互連材料30之凹陷表面可視情況經活 化以使該表面對於隨後之金屬電鍍呈現選擇性。然而，在 一些實施例中，熟習此項技術者將認識到該表面活化係並 2必需的。表面活化可使用各種技術達成。該表面較佳可 猎由暴露於例如氣化鈀溶液之無電鍍技術中已知之任何活 化溶液中來活化。視所選擇之特定活化溶液而定，用於表 面暴路之典型時框可為約1 〇秒至約2分鐘。 、見參考圖8，接著使用一無電鍍製程使金屬選擇性地沉積 於該等凹陷中。在該等凹陷中所形成之金屬層可包括與該 半導私結構中之相鄰材料相容之任何合適金屬。該等金屬 層車又k包括始、銀、金、銅、鎳、把、翻或其合金。該金 105984.doc 1286818 屬最佳包括始’因為姑容易得到且提供—精細顆粒結構， 對於後矣賣製程而言該精細顆粒結構促進達$ 一更平滑之表 面。 “較佳地，形成具有約200埃至約500埃厚度之金屬覆蓋。 藉由控制該等覆蓋之電鑛速率，可生成與絕緣層2〇之上表 面大體共平面之覆盍。在基板上電鍍過量金屬之處，可藉 由白知製程方法（例如圖8所示結構之平坦化方法）將過量金 屬除去，以使該金屬層分離為所示之單獨金屬覆蓋•圖8 之結構接著可經進一步處理以得到一功能電路。 如圖9所不，-記憶體裝置藉由沉積合適之硫族化物材料 堆疊5〇於絕緣層20及金屬覆蓋4〇上來形成。該硫族化物材 料由-硫族化玻璃（例如Ge3Se7〜山6)形成，該硫族化玻 离此夠在&用f壓存在下形成用於擴散玻璃中之例如銀 之金屬離子的㈣㈣。—第二導電電極60沉積於硫族化 物堆疊50之上以完成該記憶體裝置之形&。Μ—及㈤加 之美國專利第6,348,365號展示—非易失性記憶體之實例。 對於堆豎"，吾人意謂足以形成一記憶體單元之一或多層 包含擴散之金屬離子的硫族化物玻璃材料。 現參考圖1〇’展示一包含一積體電路448之典型的以硫族 化物為基礎之記憶體系統_。積體電路州使用—導電互 連及根據本發明之一或多個實施例所製造之以硫族化物為 基礎之記憶體。一處理器系也,丨丄 Λ 乐、、死（例如一電腦系統）通常包括一 中央處理單元（CPU)444,例如—微處理器…數位訊號處 理器或其它可程式化數位邏輯裝置，料央處理單元經一 105984.doc .14- 1286818 匯流排452與一輸入/輸出（I/O)裝置446相通信。積體電路 448中之以硫族化物為基礎之記憶體通常藉由一記憶體控 制器經匯流排452與該系統相通信。 在一電腦系統情況下，該系統可包含周邊裝置，例如一 軟碟驅動器454及一緊密光碟（CD)ROM驅動器456，該系統 亦經匯流排452與CPU 444相通信。積體電路448可包含一或 多個導電互連及以硫族化物為基礎之記憶體裝置。必要 時’在一單一積體電路中積體電路448可與例如CPU 444之 處理器组合。可包含以硫族化物為基礎之記憶體裝置之襞 置及系統的其它實例包含時鐘、電視、蜂巢式電話、汽車、 飛機及其類似物。 熟習該項技術者應瞭解在不背離本發明之範嘴下可進行 各種變化，不應認為本發明之範疇限於此說明書及圖式中 所描述之特定實施例，而其僅由隨附申請專利範圍之範疇 所限制。 【圖式簡單說明】 圖I為一根據本發明之一實施例之一部分經部分製造之 以硫族化物為基礎之記憶體裝置之實例的橫截面圖，該記 憶體裝置包含在一基板上之金屬層； 圖2為一部为經部分製造之以硫族化物為基礎之記憶體 裝置的橫截面圖，該記憶體裝置包含一在該基板表面之上 之絕緣層； Q 3為部分經部分製造之以硫族化物為基礎之記憶體 裘置的k截面圖，該記憶體裝置包含在該絕緣層中形成之 105984.doc 1286818 開口； 圖4為一部分經部分製造之以硫族化物為基礎之記憶體 裝置的橫截面圖，該記憶體裝置包含一視情況之保形黏著 層； 圖5為一部分經部分製造之以硫族化物為基礎之記憶體 裝置的橫載面圖，該記憶體裝置包含填充該絕緣層中之開 口之導電材料； 圖6為一部分經部分製造之以硫族化物為基礎之記憶體 裝置的橫截面圖，在該記憶體裝置中已除去過量導電材料； 圖7為一部分經部分製造之以硫族化物為基礎之記憶體 裝置的橫截面圖，在該記憶體裝置中該導電材料之表面已 凹陷至低於該絕緣層之上表面； 圖8為一部分經部分製造之以硫族化物為基礎之記憶體 裝置的橫截面圖，該記憶體裝置包含在填充開口之導電材 料上之一導電材料之覆蓋； 圖9為一部分經部分製造之以硫族化物為基礎之記憶體 裝置的橫截面圖，在該記憶體裝置中以硫族化物為基礎之 記憶體單元材料之堆疊位於該覆蓋之上，且一另外導電材 料之層位於該以硫族化物為基礎之記憶體單元 上；及 1 圖1 〇說明一根據本發明之並 八匕只轭例之具有一或多個以 硫族化物為基礎之記憶體裝置的處理器系統。 【主要元件符號說明】 10 積體電路結構 I05984.doc 1286818 π 基板 13 經製造之層 20 絕緣層 21 導電區域 22 開口 24 黏著層 25 絕緣層上表面 30For the sake of simplicity, the embodiment of the invention is described with reference to an upper metallization layer. 1 through 9 illustrate a partially fabricated integrated circuit structure 1 having a substrate 11 and a plurality of fabricated layers collectively shown at 13. A series of electrically conductive regions 21 electrically connected to one or more layers or devices in the following circuits are formed on the remote circuit structure by conventional techniques. Although not shown, it should be understood that the integrated circuit structure 10 can contain transistors, capacitors, word lines, bit lines, active regions, or similar elements in the layer 13 fabricated over the substrate 11. As shown in FIG. 2, an insulating layer 20 is provided over the structure 1A. The insulating layer 2〇l〇5984.do<1286818 preferably comprises tetraethyl phthalate (TEOS) or other dielectric materials such as borophosphon glass (bpsg), borosilicate glass (BSG) or other non-conductive oxides. (doped and undoped), nitrides and nitrogen oxides. The thickness of the insulating layer 20, which itself may be formed of a plurality of layers, is preferably from about 5,000 angstroms to about 2 angstroms. As shown in Figure 3, at least some of the openings 22 are provided where the interconnect will electrically communicate with the conductive regions 21 provided in the uppermost portion of the structure. Referring again to Figure 3, a plurality of openings 22, such as interconnect trenches, are patterned and etched in insulating layer 20. The opening 22 is aligned to expose a portion of the conductive region 21 as shown in FIG. 4. The adhesive layer 24 is deposited on the surface of the structure 1A to conform to the insulating layer 2 and to align the interconnect trenches 22. Into the line. As is known in the art, an optional adhesive layer 24 can be used to improve the bond between the conductive region 21 and the subsequently deposited conductive material. Depending on the materials used in the manufacturing process, there should be no need for the adhesive layer 24. The adhesive layer 24 as the case may be preferably formed of a refractory metal such as titanium (Ti). As shown in FIG. 4, in an embodiment of the towel, a film 24 can be used to: (4) vapor deposition (PVD), chemical vapor deposition ((10)) or atomic layer deposition (eight 1^0). product. However, any suitable material can be used for the adhesive layer, such as tungsten nitride, tungsten nitride, button nitride or other ternary compounds. The thickness of the adhesive layer 24 is preferably from about 1 angstrom to about 5 angstroms, and more preferably about 200 angstroms. See Figure 5'. A conductive interconnect material, preferably comprising tungsten, is formed over the structure and interconnect trenches 22. The conductive interconnects can be formed using any of the techniques of the art, including (for example, the two techniques white to cause conformal filling of the trenches 22. However, the trenches are 105984.doc 1286818 Depending on the aspect ratio and width, the conformal deposition techniques can cause a keyhole to be formed in the tungsten plug. Typically, the interconnect 30 should have a thickness of about ” ” to about 5 Å, and Preferably, the thickness of about 2,000 angstroms is removed. Referring now to Figure 6, excess material from conductive interconnect 30 is removed. Typically, the material is removed using chemical mechanical planarization (CMP) techniques well known in the art. Ideally, conductive interconnects When the upper surface 25 of the insulating layer 20 is substantially at the same level, the removal of excess material is stopped. Referring now to Figure 7, the conductive interconnect 30 is further planarized or over-polished to obtain a surface 25 below the insulating layer 20. A suitable distance of the recess or depression. Any method suitable for recessing the interconnect material can be used. For example, the conductive interconnect 30 can be selectively over-polished, chemical mechanically planarized, wet etched, or dry etched. The The interconnect material is recessed within the trench 22 and below the surface of the insulating layer 20. Typically, a recess of about 2 angstroms to about 5 angstroms is preferred. In one embodiment, the recessed surface of the interconnect material 30 It may optionally be activated to render the surface selective for subsequent metal plating. However, in some embodiments, those skilled in the art will recognize that the surface activation system is necessary. Surface activation can be achieved using a variety of techniques. Preferably, the surface is activated by exposure to any activation solution known in electroless plating techniques such as vaporized palladium solutions. Depending on the particular activation solution selected, a typical time frame for surface storms may be 1 〇 second to about 2 minutes. See Figure 8, and then an electroless plating process is used to selectively deposit metal in the depressions. The metal layer formed in the depressions may include the semi-conducting private structure. Any suitable metal in which the adjacent materials are compatible. The metal layers include k, silver, gold, copper, nickel, handle, turn or alloys thereof. The gold 105984.doc 1286818 is the best including the beginning 'because Easy to get Providing a fine grain structure that promotes a smoother surface for a post-sale process. "Preferably, a metal coating having a thickness of from about 200 angstroms to about 500 angstroms is formed. By controlling such The coverage rate of the electric ore can be substantially coplanar with the surface above the insulating layer 2 盍. Where the excess metal is plated on the substrate, the method of planarization can be formed by the method (for example, the planarization method of the structure shown in FIG. 8) Excess metal is removed to separate the metal layer into a separate metal coating as shown. The structure of Figure 8 can then be further processed to obtain a functional circuit. As shown in Figure 9, the memory device is suitably deposited by deposition. The chalcogenide material stack 5 is formed on the insulating layer 20 and the metal covering layer 4. The chalcogenide material is formed of - chalcogenized glass (for example, Ge3Se7~Mountain 6), which is sufficient for & (4) (4) for forming a metal ion such as silver in the diffusion glass in the presence of a f-pressure. - A second conductive electrode 60 is deposited over the chalcogenide stack 50 to complete the shape & U.S.--(5) plus U.S. Patent No. 6,348,365 - an example of non-volatile memory. For stacking, we mean a chalcogenide glass material that is sufficient to form one or more layers of a memory cell containing diffused metal ions. Referring now to Figure 1A, a typical chalcogenide-based memory system _ comprising an integrated circuit 448 is shown. The integrated circuit state uses - a conductive interconnect and a chalcogenide based memory fabricated in accordance with one or more embodiments of the present invention. A processor system, for example, a computer system typically includes a central processing unit (CPU) 444, such as a microprocessor... digital signal processor or other programmable digital logic device. The central processing unit communicates with an input/output (I/O) device 446 via a 105984.doc .14-1286818 bus 452. The chalcogenide-based memory in integrated circuit 448 is typically in communication with the system via a bus 452 via a memory controller. In the case of a computer system, the system can include peripheral devices, such as a floppy disk drive 454 and a compact disk (CD) ROM drive 456, which is also in communication with the CPU 444 via the bus bar 452. Integrated circuit 448 can include one or more conductive interconnects and a chalcogenide based memory device. The integrated circuit 448 can be combined with a processor such as the CPU 444 as necessary in a single integrated circuit. Other examples of devices and systems that may include chalcogenide-based memory devices include clocks, televisions, cellular phones, automobiles, aircraft, and the like. A person skilled in the art will appreciate that various changes can be made without departing from the scope of the invention, and the scope of the invention should not be construed as limited to the specific embodiments described in the specification and drawings. The scope of the scope is limited. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing an example of a partially fabricated chalcogenide-based memory device according to an embodiment of the present invention, the memory device being included on a substrate Figure 2 is a cross-sectional view of a partially fabricated chalcogenide-based memory device including an insulating layer over the surface of the substrate; Q 3 is a portion of the portion A k-sectional view of a chalcogenide-based memory device fabricated, the memory device comprising an opening of 105984.doc 1286818 formed in the insulating layer; and Figure 4 is a portion of the partially fabricated chalcogenide based A cross-sectional view of a memory device including a conformal conformal adhesive layer; FIG. 5 is a cross-sectional view of a partially fabricated chalcogenide-based memory device, the memory The device comprises a conductive material filling an opening in the insulating layer; Figure 6 is a cross-sectional view of a portion of a partially fabricated chalcogenide-based memory device in which the device has been Figure 7 is a cross-sectional view of a partially fabricated chalcogenide-based memory device in which the surface of the conductive material has been recessed below the surface of the insulating layer Figure 8 is a cross-sectional view of a portion of a partially fabricated chalcogenide-based memory device including a conductive material over a conductive material filling the opening; Figure 9 is a partially fabricated portion A cross-sectional view of a chalcogenide-based memory device in which a stack of chalcogenide-based memory cell materials is placed over the overlay and a layer of additional conductive material is located On a chalcogenide-based memory cell; and FIG. 1A illustrates a processor system having one or more chalcogenide-based memory devices in accordance with the present invention and a conjugated yoke. [Main component symbol description] 10 Integrated circuit structure I05984.doc 1286818 π Substrate 13 Fabricated layer 20 Insulation layer 21 Conductive area 22 Opening 24 Adhesive layer 25 Upper surface of insulating layer 30

50 60 400 444 446 448 導電互連 金屬覆蓋 硫族化物堆疊 第二導電電極 以硫族化物為基礎之記憶體系統 中央處理單元（CPU) 輸入/輸出（I/O)裝置 積體電路50 60 400 444 446 448 Conductive Interconnect Metal Covered Chalcogenide Stack Second Conductive Electrode Chalcogenide Based Memory System Central Processing Unit (CPU) Input/Output (I/O) Device Integrated Circuit

452 454 456 匯流排 軟碟驅動器 緊密光碟（CD)ROM驅動器 105984.doc452 454 456 Bus floppy disk drive compact disk (CD) ROM drive 105984.doc

Claims (1)

1286818 十、申請專利範圍： 在一以硫族化物為基礎之記憶體裝置中之一導電互 彡成-金屬覆蓋之方法， 说 ^ ^ _ /、匕祜·在一基板之上形 成一第一導電材料之一層； ^ 曰在δ亥第一導電材料及該基板 之上〉儿積一絕緣層；在 第-導電材料之至少—邻八士開口以暴露該 至乂 刀，在該絕緣層之上及該開口 内％積一第二導電材料；除 /、去忒第一導電材料之部分以 於该開口内形成一導 叫M s 守电匕硃，使该開口内之該導電區域 ::至-低於該絕緣層之—上表面的水平；在該開口内 士二凹陷導電區域之上形成—第三導電材料之—覆蓋， ^弟二導電材料係選自由下列各物組成之群：始、銀、 ::鋼、錦、紀、翻及其合金；在該覆蓋之上沉積一以 4化物為基礎之記憶體單元材料之—堆疊，及在該硫 矢化物堆疊之上沉積一導電材料。 口月求項1之方法’其中藉由無電鍍形成該第三導電材料 之覆蓋。 其包含活化該凹陷導電區域之該4 3·如請求項2之方法 面。 其中該第三導電材料包括始。 其t該第二導電材料包括鎢。 ^ 其包含在沉積該第二導電材料前， 該開D Φn Τ >儿積一難熔金屬層或難熔金屬氮化物芦 4.如請求項1之方法 5·如請求項1之方法 6·如請求項1之方法； 月农項6之方法，其甲該難熔金屬包括鈦 105984.doc 1286818 •如睛求項6之方法，其中該難熔金屬氮化物包括氮化鈦。 •如清求項1之方法，其包含除去部分該覆蓋以使該覆蓋平 垣化〇 如明求項1之方法，使該覆蓋形成為具有約200埃至約500 埃之厚度。 •如w求項1之方法，其中該絕緣層係選自由下列各物組成 之群··硼磷矽玻璃、矽酸四乙酯玻璃及氮化矽。 12. 一種用於一以硫族化物為基礎之記憶體裝置之導電互 連’其包括：一在一半導體基板上之絕緣層，該絕緣層 具有一開口； 一在該開口中之凹陷鎢層；一在該鎢層上 之無電鍍沉積金屬覆蓋，該金屬覆蓋包括選自由下列各 物組成之群之金屬：鈷、銀、金、銅、鎳、鈀、鉑及其 合金；在該覆蓋之上之一以硫族化物為基礎之記憶體單 凡材料之一堆疊；及一在該硫族化物堆疊之上之導電材 料。 13·如請求項12之導電互連，其中該金屬包括鈷。 14·如請求項12之導電互連，其中該金屬覆蓋經平坦化以與 該絕緣層之一上表面共平面。 15. —種以處理器為基礎之系統，其組合包括—處理器及一 與該處理器耦接之以硫族化物為基礎之記憶體裝置，該 以硫族化物為基礎之記憶體裝置包括一在一半導體基板 上之其中具有-開口之絕緣層；一在該開口中之凹陷鎢 層；-在該鎢層之上之無電鍍沉積金屬覆蓋，該金屬覆 蓋包括選自由下列各物組成之群之金屬：鈷、銀、金、 105984.doc 1286818 銅、鎳、鈀、鉑及其合金；在該覆蓋之上之一以硫族化 物為基礎之記憶體單元材料之一堆疊；及一在該硫族化 物堆疊之上之導電材料。 16.如請求項15之系統，其中該金屬包括鈷。 1 7.如請求項1 5之系統，其中該金屬覆蓋經平坦化以與該絕 緣層之一上表面共平面。1286818 X. Patent application scope: A method of conductive mutual-forming-metal covering in a chalcogenide-based memory device, said ^ ^ _ /, 匕祜 · forming a first on a substrate a layer of conductive material; ^ 曰 δ 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 δ δ δ δ Between the upper and the opening, a second conductive material is accumulated; a portion of the first conductive material is removed and removed to form a conductive M s in the opening, so that the conductive region in the opening: Up to below the level of the upper surface of the insulating layer; forming a covering of the third conductive material over the conductive region of the opening of the second recess: the second conductive material is selected from the group consisting of: First, silver, :: steel, brocade, kiln, tumbling and alloying thereof; depositing a stack of 4 memory-based memory cell materials over the cover, and depositing a conductive layer over the sulfur-deposited stack material. The method of claim 1 wherein the covering of the third conductive material is formed by electroless plating. It comprises the method of activating the recessed conductive region, such as the method of claim 2. Wherein the third conductive material comprises an initial. The second conductive material includes tungsten. ^ It comprises, before depositing the second conductive material, the opening D Φn Τ > a refractory metal layer or a refractory metal nitride reed. 4. The method of claim 1 5. The method 6 of claim 1 The method of claim 1, wherein the refractory metal comprises titanium 105984.doc 1286818. The method of claim 6, wherein the refractory metal nitride comprises titanium nitride. The method of claim 1, which comprises removing a portion of the cover to planarize the cover, such as the method of claim 1, such that the cover is formed to have a thickness of from about 200 angstroms to about 500 angstroms. The method of claim 1, wherein the insulating layer is selected from the group consisting of borophosphonium silicate glass, tetraethyl citrate glass, and tantalum nitride. 12. A conductive interconnect for a chalcogenide-based memory device comprising: an insulating layer on a semiconductor substrate, the insulating layer having an opening; and a recessed tungsten layer in the opening An electroless deposition metal coating on the tungsten layer, the metal covering comprising a metal selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof; One of the upper ones of the chalcogenide-based memory material is stacked; and a conductive material over the chalcogenide stack. 13. The conductive interconnect of claim 12, wherein the metal comprises cobalt. 14. The conductive interconnect of claim 12, wherein the metal cover is planarized to be coplanar with an upper surface of the insulating layer. 15. A processor-based system, the combination comprising: a processor and a chalcogenide-based memory device coupled to the processor, the chalcogenide-based memory device comprising An insulating layer having an opening therein on a semiconductor substrate; a recessed tungsten layer in the opening; - an electroless deposition metal covering over the tungsten layer, the metal covering comprising a component selected from the group consisting of Group of metals: cobalt, silver, gold, 105984.doc 1286818 copper, nickel, palladium, platinum and their alloys; one of the chalcogenide-based memory unit materials on top of the overlay; A conductive material over the chalcogenide stack. 16. The system of claim 15 wherein the metal comprises cobalt. The system of claim 15, wherein the metal cover is planarized to be coplanar with an upper surface of the insulating layer. 105984.doc105984.doc
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