KR20010094954A - Capacitor structure and method of making same - Google Patents

Abstract

PURPOSE: To provide a highly reliable chip-on-capacitor. CONSTITUTION: The capacitor (94) in a semiconductor device (20) has a lower copper plate (30) in a damascene/trench (22), barrier layers (56, 180a) disposed above the lower plate, a dielectric layer (60) disposed above the barrier layers and an upper plate (96) above the dielectric layer. Another embodiment of this invention is capacitors (296, 396) in a semiconductor device, which has two lower plates (230, 231, 330, 331) mutually separated, dielectric layers (260, 360) above the lower plate and upper plates (296, 396) above the dielectric layer which covers the lower plate, extends preferably across it. This invention further includes a method for manufacturing the capacitor of such a constitution.

Description

Capacitor in semiconductor device and manufacturing method therefor {CAPACITOR STRUCTURE AND METHOD OF MAKING SAME}

The present invention relates to a capacitor structure in a semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to three-plate capacitors and methods of making the same, and stacked-plate capacitors in which the bottom plate (s) are copper damascene structures. ) And a method for producing the same.

Various integrated circuit solutions now require mixed signal designs with digital and analog circuits sharing the same chip. Typically, digital circuits dominate, but there are a few analog circuits that play some important roles that cannot be digitized immediately. Analog circuits typically require one or more types of passive circuit elements, such as capacitors. Typically, these capacitors need to be very linear in frequency and voltage. Because large area capacitance values may be required, on-chip capacitors can be utilized using back-end-of-the-line (BEOL) wiring levels rather than silicon substrate polysilicon, metal, and diffusion. ) May be desirable. Additionally, it may also be desirable to place the on-chip capacitors as physically as possible away from the substrate or as close as possible to chip-to-package connections. In addition, these passive devices typically need to be manufactured at "precise ratios". For this reason, metal-insulator-metal capacitors may be preferred over poly-insulator-inverting, metal-insulator-diffusion, or other such capacitor structures. In applications where power consumption is very important, capacitors are preferred over resistors to form passive devices because these circuits exhibit lower losses.

Some applications require high performance precision capacitors at any cost. However, various mixed signal applications are very cost sensitive. Therefore, the manufacturing process used to manufacture these components should be as simple as possible. Therefore, adding additional masks and associated photo-patterning to create the desired capacitor structure can be a very expensive semiconductor chip for certain applications, particularly in the consumer product domain. This is especially true for active devices such as capacitors that are very sparingly used throughout the chip.

As part of improving the performance of semiconductor chips and reducing the minimum feature size, copper is now used for a variety of wiring and interconnect structures. In the use of copper and silicon together in semiconductor chips, the separation of copper and silicon Because of the challenges, such as the need to provide a barrier layer, existing capacitor fabrication techniques cannot be applied where copper metallurgy is used. Thus, there is a need for precision capacitors, decoupling capacitors and other capacitor structures that can be fabricated in semiconductor manufacturing processes that pattern copper metal.

The main problem of metal-insulator-metal (MIM) capacitors is that when the capacitor plates are manufactured to be coplanar, there is a significant leakage current path at the interface between the metal layer and the intervening capacitor dielectric layer due to metal residues. leakage current paths may exist. For example, as shown in FIG. 7A, the prior art MIM capacitor 10a has a lower metal plate 12a, a dielectric layer 14a and an upper metal plate 16a. These plates have a flat interface 18a through which a current leakage path can develop. 7B shows a prior art capacitor 10b manufactured by a subtractive-etch process. The flat interface 18b is the site of leakage current between the plates 12b and 16b and the dielectric layer 140b. Therefore, there is a need to remove the flat MIM interface of the MIM capacitor.

Summary of the Invention

A first aspect of the invention is a capacitor in a semiconductor device comprising a trench and a first layer having a bottom plate positioned in the trench. The bottom plate is made from a conductive material. The barrier layer covers the bottom plate and the dielectric layer is positioned over the barrier layer. An upper plate made from a conductive material is placed over the dielectric layer.

Another aspect of the invention relates to a method of manufacturing a capacitor in a semiconductor device. The first step of the method includes providing a layer having a first trench. Next, a conductive material is deposited in the first trench of the capacitor to form the bottom plate of the capacitor. Thereafter, a barrier layer is provided on top of the conductive material. A dielectric material layer is then provided on top of the barrier layer. The final step includes providing a conductive top plate of the capacitor on top of the dielectric material.

Another aspect of the invention is the presence of a capacitor in a semiconductor device comprising a first plate having an outer edge and a second plate having an outer edge. The second plate is spaced from the first plate and the first and second plates lie on a common horizontal plane. The dielectric layer is located above the first plate and the second plate, and the third plate is located above the first plate and the second plate.

Another aspect of the invention relates to a method of manufacturing a capacitor in a semiconductor device. The method begins with providing a first plate and a second plate spaced apart from the first plate and located on a substantially same horizontal plane as the first plate. The first plate has a first outer edge and the second plate has a second outer edge. Next, a dielectric layer is provided over the first plate and the second plate. Finally, the third plate is provided over the dielectric layer overlying at least some of the first plate and the second plate.

1A-1G are schematic diagrams of a portion of a semiconductor device illustrating process steps used to fabricate a planar capacitor having a copper damascene bottom plate according to a first embodiment of the present invention. Cross-section,

2A-2E are schematic cross-sectional views of a portion of a semiconductor device illustrating process steps used to fabricate a planar capacitor having a copper damascene base plate in accordance with another embodiment of the present invention;

3A-3D are schematic cross-sectional views of a portion of a semiconductor device illustrating the process steps used to fabricate a planar capacitor having a copper damascene base plate according to another embodiment according to the present invention;

4A-4F are schematic cross-sectional views of a portion of a semiconductor device illustrating process steps used to fabricate a planar capacitor having a copper damascene base plate in accordance with another embodiment of the present invention;

5A-5E are schematics of a portion of a semiconductor device illustrating the process steps used to fabricate a three-plate capacitor having two damascene base plates manufactured using another embodiment of the present invention. Cross-section,

6A-6G are schematics of a portion of a semiconductor device illustrating the process steps used to fabricate a three-plate capacitor with two base plates fabricated using subtractive etch in accordance with another embodiment of the present invention. Cross-section,

7A and 7B are schematic cross-sectional views of prior art MIM capacitors fabricated using the damascene and subtractive-etch process respectively.

Explanation of symbols for the main parts of the drawings

20: trench 24: insulator layer

30: lower plate 32: wire structure

34: wiring level 40: passivation layer

44 nitride layer 46 oxide layer

48 nitride layer 50 photoresist layer

52: opening 52: opening

56 barrier layer 60 capacitor dielectric layer

62 barrier layer 68 photoresist

70: opening 72: diffusion barrier layer

74: conductor 76: layer

78 photoresist layer 84 photoresist portion

88,90,92: opening 94: capacitor

96: upper plate 120: trench

122: wire structure 126: opening portion

128, 130, 132: opening 136: extension

1A-1G, a first aspect of the invention relates to a stacked-plate capacitor in a metal layer, typically a metal upper layer, in a semiconductor device 20 fabricated using a damascene copper wiring manufacturing process. It relates to a method of manufacturing). Although not shown in the figures, it should be understood that the active device has been fabricated at the lowest level of device 20 in advance and other metal and via layers exist below the levels shown in the figure.

This method begins by forming one or more damascene or double damascene wires and via conductors within the wiring level 34 using techniques well known in the art. More specifically, at the final (upper) level of damabling wiring, trenches 22 are formed in insulator layer 24, for example an oxide layer. Typically, but not necessarily, oxide layer 24 includes a top wiring level for semiconductor device 20. Optionally, second trench 26 may be formed in insulator layer 24 adjacent to trench 22. As illustrated, trenches 22 and 26 and other trenches used with the damascene metal deposition process described below typically extend only partially through insulator layer 24. The trench 22 is then filled with any conductor, such as copper or aluminum, known in the art to form the bottom plate 30 of the capacitor. If provided, trench 26 is also filled with a conductor to form wire structure 32. Most low resistance metals, such as copper or aluminum, typically require a refractory metal liner (not shown) on the trench sidewalls and bottom as is known in the art. If copper is deposited in trenches 22 and 26, conventional damascene copper deposition processes may be used. This process typically involves electroplating copper in the trenches after sputtering or depositing a copper thin seed layer on the surface on which copper is to be deposited.

Referring to FIG. 1B, passivation layer 40 is subsequently deposited on top of oxide layer 24, lower plate 30, and wire structure 32. The passivation layer 40 is formed of a nitride layer 44, for example 50 nm of SiN _x H _y , an oxide layer 46 on top of the layer 44, for example 500 nm of SiO ₂ and a top of layer 46. The nitride layer 48 of the phase may include, for example, 500 nm of SiN _x H _y . Next, photoresist layer 50 is deposited on layer 48 and photo-patterned to form openings 52. The opening is located above the bottom plate 30 and is typically wider than the bottom plate 30.

As shown in FIG. 1C later, the opening 52 extends through the passivation layer 40 in the direction of the bottom plate 30 to cover standard perfluorocarbons (PFCs) and hydrogen psiocarbons well known in the art. The opening 54 is formed using a conventional anisotropic etching process such as reactive ion etching (RIE) with a standard chemical such as (HFC). More specifically, nitride layer 48 is etched first and oxide layer 46 is then etched, with the use of selective chemicals suspended on nitride layer 44. Finally, nitride layer 44 is etched to expose lower capacitor plate 30. It should be noted that the nitride layer 44 is required when the capacitor plate 30 is made of copper wiring level, but not required when the capacitor plate 30 is made of another metal such as AlCu. At this point, assuming that the capacitor plate 30 is made of copper, the exposed copper surface must be modified so that it serves as the lower capacitor electrode substantially without copper surface interaction with the capacitor dielectric. Three potential copper surface modification processes may be used to form the barrier layer 56. The first method is a 50-1000 sccm SiH ₄ or GeH ₄ flow that reacts the capacitor plate 30 with the copper surface to form a thin silicided or germainided copper layer. Exposing to. With this first method, the wafer is maintained at approximately 400 ° C. As will be used later, copper germanide is a copper alloy formed using a flow of GeH ₄ or other Ge-based gas. The second method deposits a blanket film of a metal, such as tin (Sn), indium (In), aluminum (Al), and zinc (Zn) and, for example, CuSn, on exposed copper. The exposed capacitor plate 30 top surface is converted to a copper alloy layer by annealing the wafer at approximately 400 ° C. for 1 hour to form a copper alloy and selectively etching off unreacted Sn. . This leaves the copper alloy on the capacitor plate 30 in a self-aligned process. Metals that can react with copper to form alloys can be used in a similar manner. The third method provides a thin TaN layer on top of the bottom plate 30 before the passivation layer 40 is formed. This is accomplished by first depositing a photoresist on the insulator layer 24 and patterning it to expose the lower capacitor plate 30. Next, when the bottom plate 30 is made of copper, approximately top 50-100 nm of the bottom plate 30 is etched using a suitable etchant such as dilute sulfuric acid to produce a trench. After the photoresist is removed, a 100-200 nm layer of TaN is deposited on the wafer using physical vapor deposition (PVD). Finally, TaN is machined into the top of the trench using chemical mechanical polishing (CMP).

Referring to FIG. 1D, the capacitor dielectric layer 60 is then conformally deposited on the layer 48 and on the opening 54, including the top of the bottom plate 30. As will be described later, layer 60 forms a capacitor dielectric and has a relative dielectric constant K, which is preferably at least 4, but is typically at least 7. Suitable materials for the dielectric layer 60 vary depending on the material used, but may include plasma enhanced vapor deposition (PECVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and spin-on processes. For example, Ta ₂ O ₅ , Si ₃ N ₄ , Si ₃ O _2, and BaSrTiO ₃ may be deposited using a known technique including a thickness of 1-100 nm, preferably 10-50 nm. Thereafter, the copper diffusion barrier layer 62 is preferably deposited on top of the dielectric layer 60. Suitable materials for barrier layer 62 may include refractory metals such as Ta, TaN, TaN / Ta, TiN / Ti, TiN, WN, etc. alone or in combination. In certain cases, it may be desirable to omit the barrier layer 62.

Thereafter, a photoresist layer 66 is deposited on the barrier layer 62. Next, openings 68 are formed in the photoresist layer using known photo-patterning processes. Both of these steps are illustrated in FIG. 1D.

Referring next to FIG. 1E, when the wire structure 32 is provided, the opening 68 is etched through the barrier layer 62, the dielectric layer 60 and the passivation layer 40 and stopped on the wire structure to open the opening. Form 70. An etching process suitable for etching the opening 70 of the layer 62 includes a SF ₆ , BCl ₃ , Cl ₂ -based RIE etchant or a wet etch consisting of hydrogen peroxide or hydrogen sulfate peroxide. Dielectric layers 60, 48, 46, 44 may be etched for opening 54 as described above. Preferably, dielectric layer 60 and nitride layer 48 are etched, after which dielectric layer 46 is etched using optional chemicals such that the etch stops on layer 44. Next, photoresist 68 is removed and finally nitride layer 44 is etched to expose wire structure 32. As described above, suitable etching processes include PFC or HFC processes that are well known in the art. Another diffusion barrier layer 72, eg, TaN deposited to a thickness of 1-50 nm, preferably approximately 10 nm, in case the copper diffusion from the wire structure 32 in the conductor 74 needs to be protected. Silver may be provided on top of barrier layer 62 and in opening 70. Wire structure 32 and metal layer 74 are barrier layers (when conventional Al or AlCu alloys (generally deposited by PVD, ionized physical vapor deposition (IPVD) or CVD processes). 72) is generally not necessary. In contrast, metal layers 32 and 74 typically include sputtered deposition of a copper seed layer, after which most of the copper is deposited by electroplating-a layer of copper deposited by a known damascene copper deposition process. Can be. Preferably, TiN layer 76 is deposited on top of metal layer 74 to a thickness of approximately 1-50 nm, preferably approximately 10 nm.

Referring to FIG. 1F, a photoresist layer 78 is subsequently deposited on layer 76 and removes most of the photoresist layer, but extends slightly over and overlays the bottom plate 30. And photo patterned to leave photoresist portion 86 extending and overlying slightly beyond trench 70. This creates an opening 88 between the portions 84, 86, an opening 90 to the left of the portion 84, and an opening 92 to the right of the portion 86. The openings 88, 90, 92 then extend to the top of layer 48 by conventional RIE processes based on SF ₆ , BCl ₃ , Cl ₂ and similar chemicals well known in the art.

Referring to FIG. 1G, the photoresist layer 78 is subsequently removed. This leaves the finished capacitor 94 with contacts 98 with the upper plate 96 and the lower plate 30. Capacitor 94 is isolated from contact 98 as a result of the etching process extending downward from opening 88 to layer 48. A contact is then made to the top plate 96 of the capacitor 94 using metal interconnects, wire bonds or solder bumps, not shown.

Referring next to FIGS. 2A-2E, the embodiment of the present invention illustrated in these figures is provided with a strap connecting the top plate 96 and the wire interconnect line at the same ironing level as the bottom plate 30. Is distinguished from the embodiment illustrated in FIGS. 1A-1G. As illustrated in FIG. 2A, this process is described above in FIG. 1B except that an additional trench 120 is formed in the insulating layer 24 and filled with copper or other metal to form the wire structure 122. Same as the illustrated process.

The process steps illustrated in FIGS. 2A and 2B are the same as the process steps illustrated in FIGS. 1B and 1C described above. The process steps illustrated in FIG. 2C are identical to the process steps illustrated in FIG. 1D described above with one exception. Opening 126 is formed in photoresist layer 66 over wire structure 122. As the formation of contacts 98 is not illustrated in FIGS. 2A-2E, openings 68 in photoresist layer 66 are also not shown in FIGS. 2C. However, it should be understood that if desired, contact 98 is formed within the embodiment illustrated in FIGS. 2A-2E, as contact 98 may be omitted from the embodiment illustrated in FIGS. 1A-1E.

Referring to FIG. 2D, the opening 126 then extends to the wire structure 122 to form the opening 128. The opening 128 is formed using the etching process described above to form the opening 70. Barrier layer 72 is deposited in opening 128 and on the other regions shown in FIG. 1E. Metal layer 74 is deposited such that it fills opening 128 and forms a continuous connection with a portion of the metal layer in opening 54. The photoresist layer 78 is formed by it covering portions of the metal layer 74 in the openings 54, 128 and openings 130 are created directly over and directly to the openings 54 and openings 132 over the openings 128 and Patterned to be created just to the left of it.

Finally, as illustrated in FIG. 2E, openings 130 and 132 extend under layer 48 using the etching process described above in FIG. 1F to separate capacitor 94 from adjacent structures. As a result of the final step, a capacitor 94 is formed with an extension 134 that contacts the wire structure 122. This allows the lower plate 30 and the upper plate 96 to be connected with the wiring under the capacitor 94 of the same wire level. Alternatively, extension 134 may be manufactured using other methods known in the art, such as tungsten studs.

An important advantage of the capacitor 94 formed in accordance with the process illustrated in FIGS. 1A-1G and 2A-2E is that it can be readily integrated into a damascene copper wire structure process. Only one additional mask step is required, which allows this process to be used in cost-sensitive semiconductor chip manufacturing.

The process described in connection with FIGS. 1A-1G and 2A-2G includes forming a capacitor dielectric layer 60 and bottom plate 96 using a subtractive etching process. The present invention also achieves the formation of the capacitor dielectric layer 60 and the bottom plate 96 using the damascene process illustrated in FIGS. 3A-3D.

In accordance with the initial process illustrated in connection with FIGS. 1A, 1B and 2A, the bottom plate 30 and the wire structures 32, 122 are formed in the insulator layer 24. Wire and via structures 32 and 122 are optional in the embodiments of FIGS. 3A-3D, which should only be provided if it is desirable to provide contact 98 and extension 134, respectively. One difference in the process illustrated in FIG. 3A with respect to the process illustrated in FIGS. 1B and 2A is that no nitride layer 48 is required. In addition, the opening 52 and thus the opening 54 are not as wide as the bottom plate 30. In contrast, in the embodiment illustrated in FIGS. 1B and 2A, the opening 54 is as wide as the bottom plate 30. However, the present invention also provides an opening 54 of the embodiment of FIGS. 1A-1G and 2A-2B of a narrower width than the bottom plate 30 and of the embodiment of FIGS. 3A-3D that is wider than the bottom plate 30. It also includes providing an opening 54.

Next, in FIG. 3B, the same process steps are performed as described above with respect to FIG. 1C. Thereafter, as shown in FIG. 3C, a dielectric layer 60 is deposited, a copper diffusion barrier layer 62 is deposited on the dielectric layer and a metal layer 74 is deposited on the barrier layer. As described above, the metal layer 74 may be copper, aluminum or an aluminum copper alloy. In the case where the metal layer 74 is aluminum-based, the barrier layer 62 may be omitted. These steps are the same as those described above in FIG. 1E.

Thereafter, as illustrated in FIG. 3D, the semiconductor device 20 is placed under a planarization process, such as a conventional chemical-mechanical polishing process, to produce a flat top surface 150. The portion of the metal layer 74 remaining in the opening 54 after planarization forms the top plate 96 of the capacitor 94. Top plate 96 and diffusion layer 60 are formed entirely in passivation layer 40. Although not illustrated in FIG. 3D, an upper plate 96 is formed, at the same time an extension 134 to the wire structure 122 (see FIG. 2E) and a contact 98 to the wire structure 32 (FIG. 1g) may be formed.

Various embodiments of the present invention described above include the formation of a copper alloy diffusion barrier layer 56 on the top surface of the bottom plate 30. Another approach comprising depositing a copper diffusion barrier layer is described in connection with the embodiment of the invention illustrated in FIGS. 4A-4F.

The first steps of this embodiment illustrated in FIG. 4A are the same as the steps of the embodiment illustrated in FIGS. 1A-1C and 2A-2B. Also, as shown in FIG. 4B, the opening 54 is wider than the bottom plate 30. Unlike the process illustrated in FIGS. 1C, 2B and 3B, a copper alloy diffusion barrier is not formed on top of the bottom plate 30. Instead, a non-conformal copper diffusion barrier layer 180 is deposited on the nitride layer 48 and in the opening 54 by a PVD, IPVD or CVD process. As discussed above, layer 180 may include any other material used for barrier layer 62 except that these materials are non-conformantly deposited, as illustrated in FIG. 4C. Is preferably deposited from Ta, TaN, TaN / Ta, Ti, TiN, W, WN and similar materials to a thickness of 1 to 100 nm, preferably approximately 50 nm. The layer 180 should be non-compatible to facilitate the isotropic etching process described below (ie, the sidewall thickness divided by the bottom layer should be less than 1, preferably less than 0.5).

Next, as shown in FIG. 4D, the barrier layer 180 is isotropically etched back using a peroxide-based wet etching or standard RIE chemistry, SF ₆ , BCl ₃ , Cl ₂ and similar materials. This removes the vertically extending portion of barrier layer 180, that is, the portion on the sidewall of opening 54. The barrier layer portion 180a also overlying the bottom plate 30 is typically slightly etched back from the sidewall of the opening 54. It is important that this etching process is controlled so that a portion of the lower plate 30 is exposed, that is, the portion 180a is not etched back from the sidewall of the opening 54 such that the portion 180a entirely covers the lower plate. .

Thereafter, as illustrated in FIG. 4E, a capacitor dielectric layer 60 and a copper diffusion barrier layer 62 are deposited as described with respect to FIG. 3C. Thereafter, a metal layer 74 is also deposited as described above with respect to FIG. 3C.

Finally, as shown in FIG. 4F, the semiconductor device 20 is planarized as described above with respect to FIG. 3D. As a result, a capacitor 94 is formed in which the top plate 96 and the capacitor dielectric layer 60 are formed in the passivation layer 40. Although not illustrated in FIG. 4F, an upper plate 96 is formed, while an extension 134 to the wire structure 122 (see FIG. 2E) and a contact 98 to the wire structure 32 are required. If so, it can be formed.

Another aspect of the invention relates to a three-plate capacitor having two bottom plates and one top plate formed using a damascene metal deposition process and a method of manufacturing such capacitors. Referring now to FIGS. 5A-5E, this embodiment of the present invention forms a left trench 222 and a right trench 223 in an insulator layer 224, eg, an oxide layer of a semiconductor device 220. It starts by Optionally, third trench 226 and / or fourth trench 228 are formed in insulator layer 224.

The trenches 222 and 223 and the trenches 226 and 228 (if provided) are preferably filled with copper in such a way that the trench 22 is filled with copper as described above with respect to FIGS. 1A and 1B. . As a result, the lower left plate 230 and the right lower plate 231 are formed in the trench 222. Further, by preferably filling the trenches with copper using the process described above, wire structure 232 is formed in trench 226 and wire structure 233 is formed in trench 228. The trenches 222, 223, 226, 228 are preferably formed such that the plates 230, 231 and the wire structures 232, 233 are made of the same wiring level, ie they lie on a common horizontal plane or on a nearly common horizontal plane. Although copper is the preferred material for the bottom plates 230 and 232 and the wire structures 232 and 233, the present invention also includes the use of Al and AlCu alloys for these plates and structures. Al or AlCu alloys are deposited in trenches 222, 223, 226, 228 using known deposition processes such as PVD, IPVD, CVD, and the like. Barrier layer 56 is then formed on the top surfaces of plates 230 and 231 using the process described above with respect to FIG. 1C.

Passivation layer 240 is provided on top of insulator layer 224 that includes nitride layer 244, oxide layer 246, and nitride layer 248. These layers are the same as the layers 44, 46, 48 described above.

Thereafter, passivation layer 250 is deposited on nitride layer 248. Passivation layer 250 is then photo-patterned to form openings 252 over left bottom plate 230 and right bottom plate 231.

Next, referring to FIG. 5B, the opening 252 extends through the passivation layer 240 onto the top of the insulator layer 224 and above the plates 230 and 232. As a result, openings 254 are formed in the passivation layer 240 on the bottom plates 230, 231. The etching process used to form the openings 54 in the passivation layer 40 described above can be used to form the openings 254, 255.

Next, as shown in FIG. 5C, a high K dielectric layer 260 is deposited in openings 254 and 255 and on passivation layer 240. Materials and processes used to form dielectric layer 60 as described above may be used to form dielectric layer 260. Thereafter, conductive layer 262 is preferably deposited on dielectric layer 260. Conductive layer 262 is a low resistance conductor compatible with the etchant described below used to etch opening 289. In the case where the AlCu-based metal layer is used for the conductive layer 262, a 10 nm / 500 nm / 10 nm film stack of TiN / AlCu / TiN may be used to form the conductive layer. In the case where a refractory metal-based stack is used as the conductive layer 262, a 10 nm / 500 nm TiN / W stack may be used. It should be noted that the thicknesses given herein are for illustrative purposes only and any conductor thickness that can be etched using chemicals known in the art can be included in the present invention.

Referring next to FIG. 5D, insulator layer 273 is deposited on conductor layer 262. Insulator layer 273 fills openings 254 and 255 and spins on barrier layer 262 to achieve a thickness of approximately 1 to 30 microns, preferably approximately 5 microns, on top of the conductor layer. It is preferred to be prepared from on) polyimide. Other materials suitable for the insulator layer 273 include photo-sensitive polyimide and benzocyclobutene (BCB). Thereafter, photoresist layer 278 is applied to insulator layer 273 and photo-patterned to form openings 288 over wire structure 232. Preferably, opening 288 extends laterally beyond the margins of wire structure 232. If photosensitive polyimide is used, then the photoresist does not require patterning the polyimide. In cases where it is desirable to contact the wire structure 233, an opening (not shown) is made over the wire structure photoresist layer 278 at the same time that the opening 288 is formed.

Next, as shown in FIG. 5E, the semiconductor device 220 is placed under an etching process such that the opening 288 extends under the wire structure 232 to form the opening 289. First, conductor layer 262 is etched. As described above, where the conductor layer 262 is TiN / W, standard SF-based or chlorine (eg Cl ₂ or BCl ₃ ) based chemicals well known in the art are then used. In the case where the conductor layer 262 is TiN / AlCu / TiN, standard chlorine-based chemistries described above and well known in the art are used. Alternatively, where conductor layer 262 is another metal, such as electroplated copper, deposited on an adhesive layer, such as Cr, sulfuric acid and peroxide based wet chemical etching may be used thereafter. After conductor layer 262 is removed from opening 288, dielectric layer 260 is etched using standard PFC or HFC-based RIE chemistry described above well known in the art to form wire structure 232. Expose Thus, wire structure 232 is exposed to enable wire bond connections (not shown) to such a structure.

As illustrated in FIG. 5E, the top plate 296 of the capacitor 294 preferably extends beyond the outer edges of the left bottom plate 230 and the right bottom plate 232, ie beyond the edges. Although not necessary for the present invention, this overhanging construction is preferred because it eliminates potential areas of weakness present in the capacitor dielectric of the corner 298.

The tri-plate capacitor embodiment of the present invention illustrated in FIGS. 5A-5E and described above forms a bottom plate 230, 232 and wire structures 232, 233 in the trench using a known deposition process. The invention also fabricates a three-plate capacitor 294 using a subtractive etching process to form lower plates and other wire structures on the same wiring level illustrated in FIGS. 6A-6G. In subsequent detailed descriptions of this embodiment of the present invention, the material and structural layers common to the embodiments of the present invention described and illustrated in FIGS. 5A-5G have a 200 series prefix changed to 300 series, i.e., the lower left of FIG. 5A Plate 230 is identified by the same reference numeral except that it is identified as left lower plate 330 of FIG. 6C.

Referring to FIG. 6A, this aspect of the invention is disclosed as a semiconductor device 310 having an insulator layer 312 on which wire lines 314 and vias 316 are formed. Next, as illustrated in FIG. 6B, the barrier layer 318 made from a material of the type used for the barrier layer 318 having 5 to 100 nm, preferably approximately 10 nm, as described above, may be an insulator layer ( 312). Next, metal layer 320 is blanket deposited on barrier layer 318 (and any other barrier layer provided). A refractory metal such as tungsten is preferred because of its high corrosion resistance, but the metal layer 320 may be formed from Al, AlCu alloy, refractory metal copper or any low resistance metal. If copper is used, it will typically be desirable to provide a second barrier layer of TaN, TaN / Ta or other material for barrier layer 62 on top of layer 318 as described above. will be. Metal layer 320 is deposited using any standard PVD, IPVD, CVD plating, or the like, which may be comprised of a plurality of metal layers.

Next, as shown in FIG. 6B, a photoresist layer 322 is deposited on the metal layer 320. Thereafter, photoresist layer 322 is photo-patterned to create openings 324a, 324b, 324c, 324d, 324e.

Subsequently, as shown in FIG. 6C, the semiconductor device 310 is anisotropic such as chlorine-based RIE etching well known in the art to extend the openings 324a-e to the top surface of the insulator layer 312. It is placed under etching. After removing the photoresist layer 322, the remaining metal layer 320 portion constitutes the left bottom plate 330, the right bottom plate 331, the wire structure 332 and the wire structure 333. Referring next to FIG. 6D, a dielectric layer 341 made of SiO ₂ having a thickness of 0.1 to 10 microns, preferably approximately 0.5 microns, includes an insulator layer 312, bottom plates 330 and 331, and wire structures 332 and 333. Is deposited on. Alternatively, any passivation dielectric film stack well known in the art may be used. Next, silicon nitride layer 343 is deposited on dielectric layer 343 to a thickness of 0.1 to 10 microns, preferably approximately 0.5. Next, photoresist layer 350 is photo-patterned to form openings 352a, 352b, and 353.

Subsequently, the semiconductor device 310 may be formed such that the openings 352a, 352b, and 353 extend through the layer 343 to the left lower full rate 330, the right lower plate 331, and the wire structure 332, respectively. For example, it is placed under anisotropic etching, such as RIE etching. This forms openings 354a, 354b, 355 in the layers 343, 341. This forms a structure similar to that illustrated in FIG. 5B. The semiconductor device 310 is then placed under a process step in which the semiconductor device 220 illustrated in FIG. 5B is placed, as described above and illustrated in FIGS. 5C-5E. This causes the formation of the 3-plate capacitor 394 illustrated in FIGS. 6E-6G. According to the three-plate capacitor 294, the upper plate 396 of the three-plate capacitor 394 preferably, but not necessarily, extends beyond the outer edges of the lower plates 330, 331, ie protrudes.

The three-plate capacitors 294 and 394 have approximately half the capacitance of a two-plate stacked capacitor of similar footprint, but this is a disadvantage in terms of the "real area" of the chip required to manufacture the capacitor. . On the other hand, fabrication of capacitors 294 and 394 can be readily integrated into existing semiconductor fabrication processes, including damascene copper processes, typically with the addition of only one additional mask, resulting in lower fabrication costs rather than achieving maximum capacitor density. Where achieving is more important, it is a very attractive choice. This compromise is particularly acceptable in mixed signal applications where relatively sparse capacitor densities exist. As noted above, capacitor 94 and further capacitors 294 and 394 are formed at the upper wiring level of the semiconductor device. This has the advantage that the top region of the wiring metal layer is naturally isolated from the substrate bounce and can be more easily isolated from the interwiring capacitance by design. In addition, the top region of the wiring metal layer is not under the temperature and material constraints of the lower level wiring and the device.

Although capacitors 94, 294, and 394 are intended to be manufactured with precision ratioed capacitors that will typically be used as intra-stage circuit elements, the present invention is not so limited. For example, capacitors 94, 294, and 394 can be used in mixed signal applications that provide power decoupling to analog circuits that are preferably associated with their "noisy" digital circuits.

In the three-plate capacitors 294 and 394 described above and illustrated in FIGS. 5A-5E and 6A-6G, respectively, the upper capacitor plates 296 and 396 can be shared between all capacitors fabricated on the substrate. If this is not desirable, i.e., the upper capacitor plates 296, 396 are to be isolated from each other, additional masking and etching steps are added to pattern and etch the upper capacitor to achieve this isolation.

An important advantage of the present invention is the avoidance of flat MIM interfaces, such as the interfaces 18a and 18b illustrated in FIGS. 7A and 7B, respectively. This eliminates the possibility of leakage currents from the residual metal through the MIM interface.

While the present invention has been described in connection with the preferred embodiment, it should be understood that it is not limited thereto. On the contrary, the invention includes all alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined in the appended claims.

The present invention relates to three-plate capacitors and a method of manufacturing the same, stacked-plate capacitors and a method of manufacturing the lower plate (s) of copper damascene structure. This has the effect of improving the performance of the semiconductor chip and reducing the minimum feature size.

Claims (44)

a. A first layer having a trench, b. A low plate located in the trench and made from a conductive material, c. A barrier layer covering said lower plate, d. A dielectric layer over said barrier layer, e. An upper plate made from a conductive material on the dielectric layer A capacitor in a semiconductor device comprising. The method of claim 1, The lower plate has a top surface and the barrier layer is a metal alloy provided on the top surface. The method of claim 1, And the bottom plate is comprised of copper. The method of claim 3, wherein And the metal alloy is a copper alloy. The method of claim 4, wherein And the copper alloy is one of copper silicide or copper germanide. The method of claim 2, And the metal alloy is comprised of one or more of the group consisting of aluminum, indium, tin, and zinc. The method of claim 1, And the bottom plate consists of one or more metal layers. The method of claim 1, And a wire line, wherein the top plate includes an extension connected to the wiring line. The method of claim 1, And a trench in the layer of material over the bottom plate, wherein the dielectric layer and the top plate are located only within the trench. The method of claim 9, And the material layer has a planarized top surface. The method of claim 1, And the top plate has a flattened top surface. The method of claim 1, And further including a second trench in the first layer, the second trench being separated by the first layer portion and a second lower plate located in the trench, the second plate being made of a conductive material. Capacitor within. In the method of manufacturing a capacitor in a semiconductor device, a. Providing a layer having a first trench, b. Depositing a conductive material in the trench to form a bottom plate of the capacitor; c. Providing a barrier layer on top of the conductive material; d. Providing a layer of dielectric material on top of the barrier layer; e. Providing a conductive top plate of the capacitor on top of the dielectric material Capacitor manufacturing method comprising a. The method of claim 13, Wherein the conductive material deposited in step b is copper and step c includes forming one of copper silicide or copper germanide on a top surface of the copper. The method of claim 13, Wherein the conductive material deposited in step b is copper and step c comprises forming one of copper silicide or copper germanide on the top surface of the copper. The method of claim 13, The first trench provided in step a includes an extension contacting a wiring line in the semiconductor device and step b includes depositing the conductive material in the extension such that the wiring line contacts. Manufacturing method. The method of claim 13, Said step c comprising depositing a barrier layer comprised of a conductive material. The method of claim 13, Said step c comprising depositing a barrier layer comprised of an insulating material. The method of claim 13, And said step c comprises depositing a barrier layer comprised of at least one member consisting of a group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten and tungsten nitride. The method of claim 12, Wherein said barrier layer is comprised of at least one member of a group consisting of refractory metal, refractory metal nitride, and refractory metal silicide. The method of claim 13, The layer provided in step a includes a second trench spaced apart from, but very close to, the first trench, and step b includes depositing the conductive material in the first and second trenches; Step c includes providing the barrier layer on top of the conductive material in the first and second trenches, and step d includes the barrier over the conductive material in the first and second trenches. Providing the dielectric material layer on top of the layer, wherein step e provides the top plate such that the top plate covers at least a portion of the conductive material in the first and second trenches. Capacitor manufacturing method comprising a. The method of claim 13, Step e is i. Depositing a metal layer, ii. Performing a subtractive etch to remove portions of the metal layer and leave the top plate Capacitor manufacturing method comprising a. The method of claim 20, Said step e further comprising providing said top plate such that it extends beyond said conductive material in said first and said second trenches. The method of claim 13, Step e is i. Depositing a metal layer ii. Forming an upper trench in the metal layer, the upper trench having a bottom and sidewalls; iii. Providing the top plate in the top trench Capacitor manufacturing method comprising a. The method of claim 24, The step c is performed after the step e (ii) but before the step e (iii). The method of claim 24, Step c is i. Depositing the barrier layer on the bottom and the sidewalls of the lower trench; ii. Isotropically etching the barrier layer such that the barrier layer is removed from the sidewalls Capacitor manufacturing method further comprising. The method of claim 13, And the upper plate provided in step e and the upper plate provided in step e comprise copper. a. A first plate having an outer edge, b. A second plate having an outer foot edge, the second plate being spaced apart from the first plate and the first and second plates located on a common horizontal plane; c. A dielectric layer on the first plate and the second plate; d. A third plate on the first plate and the second plate Capacitor in a semiconductor device comprising a. The method of claim 27, And the third plate extends horizontally beyond the first outer edge and the second outer edge. The method of claim 28, Further comprising a material layer having a first trench and a second trench, both of which extend only partially through the material layer, wherein the first plate is deposited in the trench and the second plate is in the second trench. Capacitor in the semiconductor device being deposited. The method of claim 28, And a layer of material having a top surface, wherein said first and said second plates are positioned on said top surface. The method of claim 28, and (b) a first barrier layer between the first and second plates and (b) the dielectric layer. The method of claim 28, And a second barrier layer between the dielectric layer and the third plate. The method of claim 28, Said step c comprising depositing a barrier layer comprised of at least one of a group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten and tungsten nitride. The method of claim 27, And the barrier layer is comprised of at least one member of a group consisting of refractory metal, refractory metal nitride, and refractory metal silicide. The method of claim 28, The third plate is composed of one or more metal layers. In the method of manufacturing a capacitor in a semiconductor device, a. Providing a first plate and a second plate spaced apart from the first plate and positioned on a horizontal plane substantially the same as the first plate, the first plate having a first outer foot edge and the second plate; The plate has a second outer edge— b. Providing a dielectric layer over the first plate and the second plate; c. Providing a third plate over the dielectric layer overlying at least a portion of the first plate and the second plate Capacitor manufacturing method comprising a. The method of claim 37, And said step c includes providing said third plate such that said third plate extends horizontally beyond said first outer edge and said second outer edge. The method of claim 37, Prior to step a, further comprising providing a layer of material having a first trench and a second trench, wherein the first trench is spaced but very close to the second trench, and subsequently the step a Depositing the first plate in the first trench and the second plate in the second trench Capacitor manufacturing method comprising a. The method of claim 37, Prior to step a, further comprising providing a layer of material having a top surface, wherein step a includes providing the first plate and the second plate on the top surface. The method of claim 37, And the first and second plates provided in step a comprise copper. The method of claim 37, Wherein the first and second plates provided in step a comprise one or more aluminum or aluminum copper alloys. The method of claim 37, And providing a barrier layer on top of the first and second plates after step a and before step b. The method of claim 37, And the third plate provided in step c is comprised of one or more layers of conductive material.