479310 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（） 發明領缒： 本發明係關於在半導體元件中的電容器結構及其製 造方法。更特定說來，本發明係關於一三電極電容器藝其 其製造方法及堆疊板電容器暨其製造方法，其中丁板為銅 鑲後結構。 發明背景： 目前許多集積電路的解決方法是採用數位電路和線 性電路位於同一晶片的混合設計。一般而言，數位電路為 主，搭配較小數目的線性電路來執行一些決定性且不能數 位化的部分。線性電路通常需要一或多型態的被動電路元 件，例如電容器。一般而言電容器在關於頻率和電壓方面 需要高的線性。因為需要大面積的電容值，在晶片上的電 容器的設計多是利用導線後端（BEOL)層，而非於石夕基底多 晶石夕層、金屬層和擴散層。另外’晶片上的電容器實體位 置是設計盡可能的遠離基底和盡可能接近晶片和封裝的 連接位置。更進一步而言，被動元件在製造尚需再一精確 比例（precise ratio)之内。因此，金屬層-絕緣層-金屬層 (MIM)電容器較多晶矽層-絕緣層-反轉層、金屬層-絕緣層_ 擴散層或其它形式結構的電容器為佳。在應用上電力的消 耗是高重要性的，在此點上電容器相較於電阻為一較佳的 被動元件，因為這樣的電路消耗功率較低。 在一些應用上不惜代彳貝需要南效率精密電容器。但 是，很多混合訊號的設計對價格很敏感。例如，應用在數 第2頁 本紙張尺度適用中國國家標準（CNS)A4規ίΓ(21〇 x 297公釐） ' * ------ ------------------^^-------— (請先閱讀背面之注意事項再填寫本頁) 479310 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 位無線·電話和行動電話上的電子元件就對價格極端敏 感。依此’適用於生產這樣元件的製程就要越簡單越好。 因此，增加額外的一道光阻或光阻蝕刻製程來生產所設計 應用在晶片上的電容器對某些使用者而言將會太昂貴，特 別是是在那些消費者產品領域。對於例如像是電容器這樣 的被動元件稀疏的遍及整個晶片更是如此。 在增進半導體晶片的效益和減少其尺寸的努力，銅被 使用於不同的導線和内連線結構。因為在半導體晶片上併 用銅和矽的挑戰，包括需要一阻障層來分隔銅和矽，習知 的技術無法在使用銅冶金處製造電容器β因此，需要一個 能在具有鋼冶金處製造精密、去隸合和其它電容器結構的 半導體製程。 金屬層-絕緣層-金屬層電容器的一個主要的問題在於 依此製造的電容器板是共平面的，會有一個實質漏電流路 徑因為金屬的污染而存在於金屬層和介於之間的電容器 介電層的平面介面上。例如，如第7a圖所示，習知镶嵌ΜΙΜ 型電容器10a，具有一下板12a —介電層14a和一上金屬板 16a。這些板具有平面介面18a在此會發生漏電流。第了匕圖 係繪示習知已移除-蝕刻製程形成的電容器1 〇b。平面介面 18b位於板12b和16b間的介電層14b為一漏電流位置。因 此，必須消除MIM形電容器内的MIM平面介面。 發明目的及概述： 本發明的一樣態是一半導體元件電容器，包括一具有 第3頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------—r—訂---------線 (請先閱讀背面之注意事項再填寫本頁) 479310 A7479310 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the Invention () Invention Guide: This invention relates to the capacitor structure in semiconductor components and its manufacturing method. More specifically, the present invention relates to a three-electrode capacitor, a method for manufacturing the same, and a stacked-plate capacitor and a method for manufacturing the same, in which the slab is a copper-inlaid structure. BACKGROUND OF THE INVENTION: Many current integrated circuit solutions are based on a hybrid design where digital circuits and linear circuits are located on the same chip. In general, digital circuits are the mainstay, with a small number of linear circuits to perform some decisive and non-digitizable parts. Linear circuits usually require one or more types of passive circuit elements, such as capacitors. Generally, capacitors require high linearity with respect to frequency and voltage. Because a large area of capacitance is required, capacitors on the wafer are mostly designed using the back end of the wire (BEOL) layer rather than the polycrystalline stone layer, metal layer, and diffusion layer on the substrate. In addition, the physical location of the capacitor on the wafer is designed to be as far away from the substrate as possible and as close as possible to where the wafer and package are connected. Furthermore, passive components need to be manufactured within a precise ratio. Therefore, metal layer-insulation layer-metal layer (MIM) capacitors are more crystalline silicon layer-insulation layer-inversion layer, metal layer-insulation layer_ diffusion layer or other forms of capacitors are preferred. Power consumption is of high importance in applications. At this point capacitors are a better passive component than resistors because such circuits consume less power. In some applications, we need precision capacitors with high efficiency. However, many mixed-signal designs are price sensitive. For example, applied to the second page of this paper, the paper size applies the Chinese National Standard (CNS) A4 Rule Γ (21〇x 297 mm) '* ------ ------------- ----- ^^ -------— (Please read the notes on the back before filling out this page) 479310 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Wireless Electronic components on telephones and mobile phones are extremely price sensitive. In this way, the simpler the process suitable for producing such components, the better. Therefore, adding an additional photoresist or photoresist etching process to produce capacitors designed for use on wafers would be too expensive for some users, especially in those consumer products. This is especially true for passive components such as capacitors that are sparse throughout the entire wafer. In an effort to increase the efficiency of semiconductor wafers and reduce their size, copper is used in different conductor and interconnect structures. Because of the challenges of using copper and silicon on semiconductor wafers, including the need for a barrier layer to separate copper and silicon, conventional techniques cannot make capacitors in copper metallurgy. Therefore, it is necessary to have a precision, De-bonding and other capacitor manufacturing semiconductor processes. One of the main problems of metal layer-insulation layer-metal layer capacitors is that the capacitor board manufactured according to this is coplanar, and there will be a substantial leakage current path between the metal layer and the capacitor between the capacitor layer due to metal pollution. The plane interface of the electrical layer. For example, as shown in FIG. 7a, the conventional MIM-type capacitor 10a has a lower plate 12a-a dielectric layer 14a and an upper metal plate 16a. These boards have a flat interface 18a where leakage currents occur. The first figure shows a capacitor 10b formed by a conventional removal-etching process. The dielectric layer 14b of the planar interface 18b between the plates 12b and 16b is a leakage current location. Therefore, the MIM planar interface in the MIM-shaped capacitor must be eliminated. Purpose and summary of the invention: The same aspect of the present invention is a semiconductor element capacitor, including a sheet of paper on page 3 which applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --------- ----— r—order --------- line (please read the precautions on the back before filling this page) 479310 A7
經濟部智慧財產局員工消費合作社印製 五、發明說明（） 溝渠之第一層及一下板位於溝渠内。形成下板的物質為導 電性物質。一阻障層覆蓋下板及一介電層位於阻障層之 上。一上板，形成上板的物質為導電性物質’上板位於介 電層之上。 本發明的另一樣態是一半導體元件電容器的製造方 法，方法的第一步包括提供一第一溝渠。接著，一導電性 物質沉積於第一溝渠之内形成電容器之下振。然後’提供 一阻障層於導電性物質的頂端。然後提供/介電物質層於 阻障層的頂端。最後一步提供一導電材質上板位於介電材 質的頂端。 本發明的又一樣態是一半導體元件電容器包括一第 一板具有一外緣及一第二板具有一外緣。〆第一板與一第 二板間有一空間且第一及第二板位於同一水平面上° 一介 電層位於第一及第二板之上以及一第三板位於介電層之 上。 本發明的再一樣態是一半導體元件電谷器的製造方 法。方法的第一步包括提供一第一板與一第二板間有一空 間且第一及第二板位於同一水平面上當作该第一板。第一 板具有一外緣及一第二板具有一外緣。然壤提供一介電層 於第一板和第二板之上。最後，提供一第彡板位於介電層 之上且至少覆蓋部分第一板和第二板。 圖式簡鞏說明： 第la圖至第1 g圖係一半導體元件的剖面示意圖’係依本發 第4頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------f i [丨丨丨訂--------線· (請先閱讀背面之注意事項再填寫本頁) 479310 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 明一實施例所繪示一具有銅鑲嵌下板的平面電容 器的製程步驟； 第2a,第2e圖係一半導體元件的剖面示意圖，係依本發 另一實施例所繪示一具有銅鑲嵌下板的平面電 第3 a圖Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention () The first floor and the lower board of the ditch are located in the ditch. The substance forming the lower plate is a conductive substance. A barrier layer covers the lower plate and a dielectric layer is on the barrier layer. On the upper plate, the material forming the upper plate is a conductive material. The upper plate is located on the dielectric layer. Another aspect of the present invention is a method of manufacturing a semiconductor element capacitor. The first step of the method includes providing a first trench. Next, a conductive material is deposited in the first trench to form a capacitor. Then, a barrier layer is provided on top of the conductive material. A layer of dielectric material is then provided on top of the barrier layer. The last step is to provide a top plate of conductive material on top of the dielectric material. Another aspect of the present invention is that a semiconductor element capacitor includes a first plate having an outer edge and a second plate having an outer edge.有 一 There is a space between the first plate and a second plate and the first and second plates are on the same horizontal plane. A dielectric layer is on the first and second plates and a third plate is on the dielectric layer. Another aspect of the present invention is a method for manufacturing a semiconductor element valley device. The first step of the method includes providing a space between a first plate and a second plate and the first and second plates being on the same horizontal plane as the first plate. The first plate has an outer edge and a second plate has an outer edge. However, a dielectric layer is provided on the first and second plates. Finally, a second plate is provided on the dielectric layer and covers at least part of the first plate and the second plate. Brief description of the drawings: Figures la to 1g are cross-sectional schematic diagrams of a semiconductor element. 'The paper size on page 4 of this issue applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)- -------- fi [丨 丨 丨 Order -------- line · (Please read the precautions on the back before filling in this page) 479310 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the Invention (The process steps of a planar capacitor with a copper-embedded lower plate are shown in the first embodiment; Figures 2a and 2e are schematic cross-sectional views of a semiconductor device, and are shown according to another embodiment of the present invention. Planar electricity with a copper-embedded lower plate Figure 3a
器的製程步驟； 3 d圖係一半導體元件的剖面示意圖，係依本發 明又一實施例所繪示一具有銅鑲嵌下板的平面電 的製程步驟； 第4a圖4f圖係一半導體元件的剖面示意圖，係依本發 一實施例所繪示一具有銅鑲嵌下板的平面電 的製程步驟； 第5 a圖篇e圖係一半導體元件的剖面示意圖，係依本發 明一實施例所繪示一具有二銅鑲嵌的三板電容器 的製驟； 第6a圖至第係一半導體元件的剖面示意圖，係依本發 明再實施例所繪示一以移除蝕刻製造之具有 二銅三板的平面電容器的製程步驟；以及 第7a圖至第係繪示習知已鑲嵌極移除蝕刻製造的 MIM電容器的剖面示意圖。3d is a schematic cross-sectional view of a semiconductor device, and is a drawing of a planar electrical process with a copper-embedded lower plate according to another embodiment of the present invention; FIGS. 4a and 4f are drawings of a semiconductor device. The schematic cross-sectional view shows the manufacturing steps of a plane electrical device with a copper-embedded lower plate according to an embodiment of the present invention; FIG. 5a and FIG. E are cross-sectional schematic views of a semiconductor device and are drawn according to an embodiment of the present invention. A manufacturing process of a three-plate capacitor with two copper inlays is shown; Figs. 6a to 1 are cross-sectional schematic diagrams of a semiconductor element, and a planar capacitor with two copper and three plates manufactured by removing etching according to another embodiment of the present invention is shown Process steps; and FIG. 7a to FIG. 7 are schematic cross-sectional views of conventional MIM capacitors fabricated by removing tessellation.
圖號對照說明： 10a,10b 電容器 14a, 14b 介電層 18a,18b 平面介面 12a,12b 下板 1 6a, 1 6b 上板 20 半導體元件 第5頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------MW —l·! 丨訂---------線 Φ <請先閱讀背面之注意事項再填寫本頁) 479310 A7 B7 五、發明說明（） 經濟部智慧財產局員工消費合作社印製 22 溝渠 24 絕緣層 26 溝渠 30 下板 32 導線結構 34 導線層 40 被動層 44 氮化矽層 46 氧化矽層 48 氮化矽層 50 光阻層 52 開口 54 開口 56 阻障層 60 介電層 62 阻障層 66 光阻層 68 開口開口 70 開口 72 阻障層 74 導體 76 氮化la層 78 光阻層 84 部分光阻 86 部分光阻 88 開口 90 開口 92 開口 94 電容器 96 上板 98 接觸栓 120 溝渠 122 導線結構 126 開口 128 開口 130 開口 132 開口 134 延伸部 150 平面 180 阻障層 180a 部分阻障層 220 半導體元件 222 溝渠 223 溝渠 226 溝渠 228 溝渠 224 絕緣層 230 下板 第6頁 -----------------r---t---------^ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 479310 A7 B7 五、發明說明（） 23 1 下板 232 導線結構 233 導線結構 240 被動層 244 氮化硬層 246 氧化矽層 248 氮化矽層 250 光阻層 254 開口 255 開口 262 導體層 278 光阻層 273 絕緣層 288 開口 289 開口· 294 電容器 296 上板 298 電容器角落 3 16 介層窗 3 10 半導體元件 3 14 導線層 3 12 絕緣層 318 阻障層 320 金屬層 322 光阻層 324a，324b，324c，324d，324e 開口 330 下板 33 1 下板 332 導線結構 333 導線結構 341 介電層 343 氮化矽層 3 52a,352b 開口 353 開口 3 54a,3 54b 開口 355 開口 394 電容器 396 上板 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 發明詳細說明： 請參照第1 a圖至第1 g圖，本發明的特徵是提供一方法 再以銅鑲嵌導線製成的半導體元件20之一金屬層中，一般 第7頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 479310 A7 B7 經濟部智慧財產局員工消费合作社印製 五、發明說明（ 是金屬層的頂端，一堆疊式板的製造方法。雖未繪示於圖 中，但主動元件已經先被製造位於元件20的最下層，其它 金屬層及介層窗層則位於圖示的下方。 此方法以習之的技術在導線層34之内形成一或數層 鑲嵌或雙鑲嵌導線或介層導體。特別的是在最上一層鑲嵌 導線一溝渠22形成於絕緣層24之中，如可形成於一氧化發 層中。一般說來，氧化矽層24必須包覆半導體元件20最上 層的導線。一第二溝渠26緊鄰溝渠22任意形成於氧化矽層 24之内。如圖所示，溝渠22和26，如同其它溝渠以下述的 使用金屬鑲嵌沉積製程，一般僅部分延伸穿透絕緣層24， 然後溝渠2 2填滿習知的導電材質（例如銅或鋁）已形成電容 器的下板30，而溝渠26(若存在的話）亦依樣填滿導體形成 導線結構32。大部分低電阻金屬（例如銅和鋁）一般需要以 習知方法將耐熱金屬薄層（未繪示於圖上）形成於溝渠的側 邊和底部。如果在溝渠22和26沉積銅，則使用傳統的銅鑲 嵌沉積製程《這樣的製程包括在鑲嵌溝渠電鍍銅，一般在 沉積鋼的位置先以濺鍍或其它沉積法先形成一銅晶種 層。 請參照第1 b圖。圖中一被動層40沉積於絕緣層24、下 板30和導線結構32的頂端。被動層4〇可包括一氮化矽層 44(如50奈米的氮氫化矽）；一氧化矽層46(如5〇〇奈米的二 氧化矽）於該氮化矽層44之上；及一氮化矽層48(如5〇〇奈米 的氮氫化矽），其位於氧化矽層46之上。接著，塗佈一光 阻層50於氮化矽層48之上和圖案化光阻層形成一開口 第8頁 I ·1 H ^1 ϋ ϋ I I I I I · aMmm ·1 ί ϋ *ϋ ϋ 一δ- · im— a— n an >1· n ^aemm I 2¾先閱磧背面之注意事項再填寫本頁) 479310 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 5 2，其中開口 5 2 —般都位於下板3 〇的上方。 接著清參閱第1 c圖。以傳統非均向蝕刻（如反應性離 子蝕刻）沿開口 52向下蝕穿被動層4〇至下板3〇形成開口 54，此蝕刻使用習知的標準的化學品，％氟碳化物或氫氟 碳化物等。特別的是，先蝕刻者為氮化矽層48，而後蝕刻 者為氧化矽層46，較佳的適用選擇性蝕刻則停在氮化矽層 4 4。最後，蚀穿氮化矽層4 4並曝露下方的下板3 〇。值得注 意的是，若下板30為銅，那麼必須有氮化矽層44的存在； 若為其它金屬（如鋁銅合金）則不需要該層44的存在。由此 觀之，假設下板3 0的材質是銅，曝露出的銅表面必須加以 修飾，以能做為電容器下板，且不會使實質的銅表面和介 電層作用。目前較具競爭力的銅表面修飾法有三，使用之 可形成阻障層56。第一種方法是曝露下板3〇於5〇 seem至 1 000 seem的矽烷或鍺烷流之下而在銅表面形成一銅金屬 矽化物或銅金屬鍺化物。使用此方法時，晶圓片必須保持 在攝氏400度之下。以在此處所用者而言，錯化銅是銅合 金在鍺烷或其它含鍺氣體下形成的。第二種方法是將下板 曝露出的頂端表面藉由沉積一其它金屬薄膜（例如錫、 銦、鋁和鋅）、並讓晶圓片在攝氏400度下回火1小時而轉 化成銅合金（例如錫銅合金），再以選擇性蝕刻移除未反應 的錫。利用依自我對準的製程將合金留在愛容器板3 〇的表 面，而任何可與銅形成合金之金屬皆可利用該方式形成銅 合金。第三種方法包括在形成被動層40之前在下板30的表 面形成一氮化钽層、在絕緣層24上沉積一光阻並圖案化此 第9頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----1.II1-----——l·! 訂---------線· (請先閱讀背面之注意事項再填寫本頁) 479310 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ :阻’以曝露出電容器的下板3〇。然後，以一適當的蚀刻 W (例如當下板3〇的材質為銅時則使用稀硫酸蚀刻）蚀刻 50至1〇〇奈米的深度而形成一溝渠。㈣光阻之後，以物 理氣：沉積法沉積一 100至2〇〇奈米的氮化…圓片之 上取後’以化學機械研磨在溝渠中形成氮化-鑲嵌。 明參羔第1 d圖，電容器介電層6〇同形沉積在氮化矽層 48上和開口 54之内，也包括下板30的頂端之上。介電層60 形成了電容器介電層（以下將有描述），而介電材質的介電 係數較佳是大於4，一般是大於7。適用於介電層60的材質 (例如包括五氧化二銓、四氮化三矽·二氧化矽和三氧化鈦 鳃鋇）沉積至1至1〇〇奈米的厚度，並以1〇至5〇奈米為較 佳。當使用之材質不同時，所使用的習知方法也隨之不 同’這些方法包括電漿增強化學氣相沉積（PECVD)、物理 氣相沉積（PVD)、化學氣相沉積（Cvd)和旋塗製程等。然 後’銅金屬擴散阻障層6 2沉積在介電層6 〇的頂端之上。適 用於阻障層62的材質包括耐熱金屬（可單獨或混合使用）， 例如叙、氮化妲、氮化钽/姮、氮化鈕/鈦、氮化鈦、氮化 鎢和其它金屬。沉積之厚度為1至50奈米，並以10奈米為 佳。此外，在某些例子中，阻障層62不一定需要使用。 然後沉積一光阻層66於阻障層62之上。接著，以習知 的技術圖案化光阻層。這兩步驟均纟會示於第1 d圖。 請繼續參照第1 e圖，當提供一導線結構3 2之後，由開 口 68蝕刻穿過阻障層62、介電層60和被動層40和停在倒現 結構之上形成開口 70。適用於在阻障層62形成開口 70製程 第10頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — — — — — — — — — — — — - — 111· — — ! ^ « — — — — — — I— (請先閱讀背面之注意事項再填寫本頁) 479310 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 包括SF6、BC13、含氯的反應性離子蝕刻或其它包含過氧 化氣或硫叙過氧*化氩的濕式蚀刻。介電層6 0、4 8、4 6和4 4 如前述被蝕刻而形成開口 54。較佳的是，介電層6〇和氮化 矽層48被蝕刻之後再以選擇性蝕刻介電層44為蝕刻終止 層蝕刻介電層46。接著，剥離光阻68然後蝕刻介電層44 , 曝露出導線結構32。適合的蝕刻如前所述為習知的pFC或 HFC製程。另提供一擴散阻障層72(例如氮化鈕），沉積之 尽度為1至5〇奈米’並以約為1〇奈米為佳。之後，於阻障 層62的頂端和開口 70之内，以防止銅由導線結構32擴散入 導體74 ;隨後金屬層74並沉積於阻障層72之上。當導線結 構3 2和金屬層7 4均是傳統鋁或鋁銅合金時（一般由物理氣 相沉積、離子化物理氣相沉積或化學氣相沉積製程沉積而 得），阻障層72不是必要的。相對地，金屬層3 2和74可能 是由銅金屬鑲嵌製程沉積的銅金屬層，一般會包括一由賤 鍍沉積而得的銅晶種層，主要的銅材質部分是由電鍍而 得。較佳的是，之後再將一氮化钽層76沉積在金屬層74的 頂端上’厚度約為1至5 〇奈米，並以約為丨〇奈米為佳。請 參照第If圖，光阻78沉積在氮化钽層76之上，圖案化光阻 78以移除大部分光阻，只留下部分光阻科位於下板3〇的上 方，並稍微延伸超過下板30 ;而部分光阻86位於溝渠7〇的 上方，並稍微延伸超過溝渠70。這產生了一開口 88位於部 分光阻84和86之間，一開口 90位於部分光阻科的左側，一 開口 92位於部分光阻86的右側。接著以傳統的選擇性離予 蝕刻製程以St、BC13、Ch和其它化學物質沿開口 88、9〇 第11頁 本紐尺度適用中國國家標準（CNS)A4規格⑽X 297公爱)' --- -----------------r---訂---------線 (請先閱讀背面之注意事項再填寫本頁) 479310 經濟部智慧財產局員工消费合作社印製 A7 B7 五、發明說明（） 和92向下蚀刻至介電廣48。 請參照第1 g圖，剝離光阻78之後，留下者為一完整的 電容器94，其具有上板96及和下板30接觸的接觸栓98。因 為由開口 88向下的蚀刻延伸至介電層48，所以電容器94和 接觸栓9 8是互相隔離的；然後再以金屬内連線、導線接點 或銲錫接點（圖中未示）和電容器94的上板96接觸。 請參照第2 a至2 e圖。第2 a至2 e圖係繪示者為本發明異 於第1 a至1 g圖所繪示之實施例的實施例，其是在和下板3 〇 同一導線層提供一上板9 6的金屬内連線的連接。如第2 a圖 所示，此製程類似第1 b圖所示之製程除了在絕緣層24上形 成額外的溝渠120，並在其中填入銅或其金屬。第2a和2b 圖所示的製程步驟和第1 b及1 c圖所示的製程步驟相同。第 2c圖所示之製程步驟和前述第1 d圖所示之製程步驟相 似，只有一點不同，不同之處為在導線結構1 22上之光阻 層66形成一開口 126。第2c圖未繪示出光阻層66上的開口 68，形成接觸检98亦未緣示於第2a至2e圖。因此，若基於 設計上之需要’接觸检98可形成於第2a至2e圖所纟會示之實 施例中，就如接觸栓98可以由第1 a至1 g圖所繪示之實施例 中移除一般。續請參照第Id圖，開口 126繼續向下延伸至 導線結構1 22而形成開口 1 28，形成開口 1 28的方法則與前 述形成開口 7 0之方法相同。阻障層7 2沉積於開口 1 2 8之内 及如第1 e圖所示其它區域之上。沉積金屬層74填滿開口 1 2 8並和開口 5 4内的金屬層形成連續的連接。圖案化光阻 層7 8覆蓋部分位於開口 54和128之上的金屬層74，並立刻 _ _第12貫 _ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------------r—訂—------線 4P (請先閱讀背面之注意事項再填寫本頁) 479310 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 在開口 5 4的右上邊產生一開口 1 3 0及在開口 1 2 8的左上邊 產生一開口 1 3 2。 最後，如第2 e圖所示，開口 1 3 0和1 3 2已如第1 f圖所描 述之蝕刻製程向下延伸至層48以分隔電容器94與其它的 結構。最後一步的結果，電容器94形成一延伸部1 34，該 延伸部與導線結構122接觸。這使得下板30和上板96可以 和位於電容器94之下同一導線層的導線連接。相對地，延 伸部1 3 4可以習知的其它方法來製造，例如鎢金屬鑲嵌製 程等。 依第la至lg圖及第2a至2e圖所繪示的製程所製造的 電容器94有一重要的優點，那就是可以很快的加入銅鑲嵌 導線製造的製程。僅需多一道光罩，這使得採用此製程的 半導體晶片製造克服了明顯的價格壓力。 第la至lg圖及第2a至2e圖所繪示的製程包括了一電 容器介電層60和上板96使用限縮的蚀刻製程。本發明亦包 含一電容器介電層60和上板96使用鑲嵌製程，如第3&至3 d 圖所示。 如前第la及lb圖及第2a圖所繪述的起始製程步驟，下 板3 0和導線結構32和122形成於絕緣層24之内。在第3&至 3 d圖中的導線和介層窗結構3 2和1 22是選擇性的，只有在 設計上提供接觸栓98和延伸134時才需要提供。第3a圖所 繪示的製程和第丨b圖及第2a圖所繪示的差異只在於其不 需要氮化矽層48。增加的開口 52及54和下板3〇一樣的寬。 相反地，第lb及2a圖所示之實施例中之開口 54較下板3〇還 -----------------r---訂---------線 (請先閱讀背面之注意事項再填寫本頁)Drawing number comparison description: 10a, 10b capacitors 14a, 14b dielectric layers 18a, 18b flat interface 12a, 12b lower board 1 6a, 1 6b upper board 20 semiconductor components page 5 This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) ------------ MW —l ·! 丨 Order --------- Line Φ < Please read the notes on the back before filling in this page ) 479310 A7 B7 V. Description of the invention () Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 22 Ditch 24 Insulating layer 26 Ditch 30 Lower plate 32 Wire structure 34 Wire layer 40 Passive layer 44 Silicon nitride layer 46 Silicon oxide layer 48 Nitrogen Silicone layer 50 Photoresist layer 52 Opening 54 Opening 56 Barrier layer 60 Dielectric layer 62 Barrier layer 66 Photoresist layer 68 Opening opening 70 Opening 72 Barrier layer 74 Conductor 76 Nitride layer 78 Photoresist layer 84 Partial light Resistance 86 Part photoresistance 88 Opening 90 Opening 92 Opening 94 Capacitor 96 Upper plate 98 Contact plug 120 Ditch 122 Wire structure 126 Opening 128 Opening 130 Opening 132 Opening 134 Extension 150 Plane 180 Barrier layer 180a Partial barrier layer 220 Semiconductor element 222 Ditch 223 Ditch 226 Channel 228 Channel 224 Insulation layer 230 Lower board Page 6 ----------------- r --- t --------- ^ (Please read the Note: Please fill in this page again) This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 479310 A7 B7 V. Description of the invention () 23 1 Lower plate 232 Wire structure 233 Wire structure 240 Passive layer 244 Nitrogen Hardened layer 246 Silicon oxide layer 248 Silicon nitride layer 250 Photoresist layer 254 Opening 255 Opening 262 Conductor layer 278 Photoresistive layer 273 Insulating layer 288 Opening 289 Opening 294 Capacitor 296 Upper board 298 Capacitor corner 3 16 Intermediate window 3 10 Semiconductor element 3 14 Wire layer 3 12 Insulation layer 318 Barrier layer 320 Metal layer 322 Photoresist layer 324a, 324b, 324c, 324d, 324e Opening 330 Lower plate 33 1 Lower plate 332 Wire structure 333 Wire structure 341 Dielectric layer 343 Nitrogen Silicone layer 3 52a, 352b Opening 353 Opening 3 54a, 3 54b Opening 355 Opening 394 Capacitor 396 Top plate (Please read the precautions on the back before filling out this page) Intellectual Property Bureau, Ministry of Economic Affairs, Employee Consumer Cooperative Co., Ltd. Printed invention detailed description: Please refer to Figure 1a to Figure Figure 1g, the present invention is characterized in that it provides a method for the metal layer of one of the semiconductor elements 20 made of copper-inlaid wires. Generally, the paper size on page 7 applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). (%) 479310 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (It is the top of the metal layer, a manufacturing method of stacked plates. Although not shown in the figure, the active device has been manufactured at the bottom layer of the device 20, and other metal layers and interlayer window layers are located below the figure. This method uses conventional techniques to form one or more layers of inlaid or double-inlaid wires or interlayer conductors within the wire layer 34. In particular, a trench 22 is embedded in the uppermost layer of the conductive wire and a trench 22 is formed in the insulating layer 24, if it can be formed in an oxide layer. In general, the silicon oxide layer 24 must cover the uppermost wiring of the semiconductor device 20. A second trench 26 is arbitrarily formed in the silicon oxide layer 24 adjacent to the trench 22. As shown in the figure, trenches 22 and 26, like other trenches, use the metal damascene deposition process described below, which generally only partially penetrates through the insulating layer 24, and then trenches 22 are filled with conventional conductive materials (such as copper or aluminum). The lower plate 30 of the capacitor is formed, and the trench 26 (if any) is filled with the conductor to form the wire structure 32 in the same manner. Most low-resistance metals (such as copper and aluminum) generally require a thin layer of heat-resistant metal (not shown) to be formed on the sides and bottom of the trench in a conventional manner. If copper is deposited in the trenches 22 and 26, a conventional copper inlay deposition process is used. Such a process includes electroplating copper in the inlay trenches, and generally a copper seed layer is first formed by sputtering or other deposition methods at the location where the steel is deposited. Please refer to Figure 1b. In the figure, a passive layer 40 is deposited on the tops of the insulating layer 24, the lower plate 30, and the wiring structure 32. The passive layer 40 may include a silicon nitride layer 44 (such as 50 nanometer silicon hydride silicon); a silicon oxide layer 46 (such as 500 nanometer silicon dioxide) over the silicon nitride layer 44; And a silicon nitride layer 48 (such as 500 nanometer silicon hydride), which is located on the silicon oxide layer 46. Next, a photoresist layer 50 is coated on the silicon nitride layer 48 and the patterned photoresist layer forms an opening. Page 8 I · 1 H ^ 1 ϋ ϋ IIIII · aMmm · 1 ί ϋ * ϋ ϋ δ- · Im— a— n an > 1 · n ^ aemm I 2¾ Please read the notes on the back of the page before filling out this page) 479310 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () 5 2 ， The openings 5 2 are generally located above the lower plate 30. Then refer to Figure 1c. The opening 54 is etched down through the passive layer 40 to the lower plate 30 along the opening 52 by a conventional non-uniform etching (such as reactive ion etching). This etching uses a conventional standard chemical,% fluorocarbon or hydrogen. Fluorocarbons, etc. In particular, the silicon nitride layer 48 is etched first, and the silicon oxide layer 46 is etched later. The preferred selective etching is stopped at the silicon nitride layer 4 4. Finally, the silicon nitride layer 44 is etched and the lower plate 30 is exposed. It is worth noting that if the lower plate 30 is copper, a silicon nitride layer 44 must be present; if it is other metals (such as an aluminum-copper alloy), the presence of this layer 44 is not required. From this perspective, it is assumed that the material of the lower plate 30 is copper, and the exposed copper surface must be modified so that it can be used as the lower plate of the capacitor without causing the actual copper surface and the dielectric layer to function. There are currently three competitive copper surface modification methods that can be used to form the barrier layer 56. The first method is to form a copper metal silicide or copper metal germanide on the copper surface by exposing the lower plate 30 to a flow of silane or germane from 50 seem to 1,000 seem. When using this method, the wafer must be kept below 400 ° C. For the purposes of this document, distorted copper is formed from copper alloys under germane or other germanium-containing gases. The second method is to convert the exposed top surface of the lower plate to a copper alloy by depositing another metal film (such as tin, indium, aluminum, and zinc) and tempering the wafer at 400 ° C for 1 hour. (Such as tin-copper alloy), and then remove the unreacted tin by selective etching. The alloy is left on the surface of the container plate 30 using a self-aligned process, and any metal that can be alloyed with copper can be used to form a copper alloy in this way. The third method includes forming a tantalum nitride layer on the surface of the lower plate 30 before forming the passive layer 40, depositing a photoresist on the insulating layer 24, and patterning this page 9. This paper size applies Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) ---- 1.II1 --------- l ·! Order --------- line · (Please read the precautions on the back before filling this page) 479310 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (: resistance to expose the lower plate of the capacitor 30. Then, an appropriate etching W (for example, when the material of the lower plate 30 is copper) Dilute sulfuric acid etching) is used to etch a depth of 50 to 100 nanometers to form a trench. After photoresist, a 100 to 2000 nanometer nitride is deposited by physical gas: deposition method on the wafer and taken 'Nitride-mosaic is formed in the trench by chemical mechanical polishing. As shown in Figure 1d, the capacitor dielectric layer 60 is isomorphically deposited on the silicon nitride layer 48 and within the opening 54, and also includes the top of the lower plate 30. Above, the dielectric layer 60 forms a capacitor dielectric layer (described below), and the dielectric constant of the dielectric material is preferably At 4, generally greater than 7. Suitable materials for the dielectric layer 60 (such as osmium pentoxide, trisilicon tetranitride • silicon dioxide, and titanium gill barium) are deposited to 1 to 100 nm The thickness is preferably 10 to 50 nanometers. When different materials are used, the conventional methods used will also vary. These methods include plasma enhanced chemical vapor deposition (PECVD), physical vapor phase Deposition (PVD), chemical vapor deposition (Cvd), spin-coating processes, etc. Then a 'copper metal diffusion barrier layer 62 is deposited on top of the dielectric layer 60. Materials suitable for the barrier layer 62 include heat resistance Metal (can be used alone or in combination), such as ytterbium nitride, hafnium nitride, tantalum nitride / rhenium, nitride button / titanium, titanium nitride, tungsten nitride, and other metals. It is preferably 10 nm. In addition, in some examples, the barrier layer 62 is not necessarily used. Then, a photoresist layer 66 is deposited on the barrier layer 62. Then, the photoresist is patterned by a conventional technique. These two steps are shown in Figure 1d. Please continue to refer to Figure 1e. When a wire structure 3 2 is provided , The opening 68 is etched through the barrier layer 62, the dielectric layer 60 and the passive layer 40 and stops on the inverted structure to form the opening 70. It is suitable for the process of forming the opening 70 in the barrier layer 62 page 10 This paper is applicable to this paper China National Standard (CNS) A4 Specification (210 X 297 mm) — — — — — — — — — — — — — 111 · — —! ^ «— — — — — — I — (Please read the back one first Note: Please fill in this page again) 479310 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention () Including SF6, BC13, reactive ion etching containing chlorine or other containing peroxide gas or sulfur peroxide * Wet etching of argon. The dielectric layers 60, 48, 46, and 4 4 are etched as described above to form the openings 54. Preferably, after the dielectric layer 60 and the silicon nitride layer 48 are etched, the dielectric layer 46 is etched with the selective etching dielectric layer 44 as an etch stop layer. Next, the photoresist 68 is peeled off and then the dielectric layer 44 is etched to expose the wire structure 32. A suitable etch is a conventional pFC or HFC process as previously described. A diffusion barrier layer 72 (e.g., a nitride button) is also provided, and the degree of deposition is preferably 1 to 50 nm 'and preferably about 10 nm. Thereafter, the top of the barrier layer 62 and the opening 70 prevent copper from diffusing from the wire structure 32 into the conductor 74; then, a metal layer 74 is deposited on the barrier layer 72. When the wire structure 32 and the metal layer 74 are both traditional aluminum or aluminum-copper alloys (generally obtained by physical vapor deposition, ionized physical vapor deposition, or chemical vapor deposition), the barrier layer 72 is not necessary. of. In contrast, the metal layers 32 and 74 may be copper metal layers deposited by a copper metal damascene process, and generally include a copper seed layer deposited by base plating, and the main copper material is obtained by electroplating. Preferably, a tantalum nitride layer 76 is then deposited on the top end of the metal layer 74 'with a thickness of about 1 to 500 nm, and more preferably about 0 nm. Referring to the If figure, a photoresist 78 is deposited on the tantalum nitride layer 76. The photoresist 78 is patterned to remove most of the photoresist, leaving only a portion of the photoresist section above the lower plate 30 and extending slightly. Exceed the lower plate 30; and a part of the photoresist 86 is located above the trench 70 and extends slightly beyond the trench 70. This creates an opening 88 between the partial photoresist 84 and 86, an opening 90 on the left side of the partial photoresist section, and an opening 92 on the right side of the partial photoresist 86. Then use the traditional selective ion etching process with St, BC13, Ch and other chemicals along the opening 88, 90. Page 11 This standard applies the Chinese National Standard (CNS) A4 specification (X 297 public love) '--- ----------------- r --- Order --------- Line (Please read the precautions on the back before filling out this page) 479310 Intellectual Property of the Ministry of Economic Affairs Bureau employee consumer cooperative printed A7 B7 V. Description of invention () and 92 are etched down to Dielectric Guang 48. Referring to FIG. 1g, after the photoresist 78 is peeled off, the remainder is a complete capacitor 94, which has an upper plate 96 and a contact pin 98 in contact with the lower plate 30. Since the etching from the opening 88 extends down to the dielectric layer 48, the capacitor 94 and the contact plug 98 are isolated from each other; and then metal interconnects, wire contacts or solder contacts (not shown) and The upper plate 96 of the capacitor 94 is in contact. Refer to Figures 2a to 2e. Figures 2a to 2e are embodiments of the present invention which are different from the embodiments shown in Figures 1a to 1g, and an upper board 9 6 is provided on the same wire layer as the lower board 30. Connection of metal interconnects. As shown in Fig. 2a, this process is similar to the process shown in Fig. 1b, except that an additional trench 120 is formed on the insulating layer 24, and copper or its metal is filled therein. The process steps shown in Figures 2a and 2b are the same as the process steps shown in Figures 1b and 1c. The process steps shown in FIG. 2c are similar to the process steps shown in FIG. 1d, with only one difference. The difference is that an opening 126 is formed in the photoresist layer 66 on the lead structure 122. Figure 2c does not show the opening 68 in the photoresist layer 66, and the contact inspection 98 is not shown in Figures 2a to 2e. Therefore, if based on design requirements, the contact inspection 98 can be formed in the embodiment shown in Figs. 2a to 2e, as the contact pin 98 can be formed in the embodiment shown in Figs. 1a to 1g. Removed in general. Continuing to refer to FIG. Id, the opening 126 continues down to the wire structure 12 to form the opening 1 28. The method of forming the opening 1 28 is the same as the method of forming the opening 70 described above. A barrier layer 72 is deposited within the openings 1 2 8 and other areas as shown in FIG. 1e. The deposited metal layer 74 fills the openings 1 2 8 and forms a continuous connection with the metal layer in the openings 5 4. The patterned photoresist layer 7 8 covers a portion of the metal layer 74 above the openings 54 and 128, and immediately _ _12th_ This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)- -------------- r-order ------- line 4P (Please read the notes on the back before filling out this page) 479310 A7 B7 Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printing 5. Description of the invention (an opening 1 3 0 is created on the upper right side of the opening 5 4 and an opening 1 3 2 is created on the upper left side of the opening 1 2 8. Finally, as shown in Figure 2e, the opening 1 3 0 And 1 3 2 have been etched down to the layer 48 to separate the capacitor 94 from other structures as described in FIG. 1 f. As a result of the last step, the capacitor 94 forms an extension 1 34 which is connected to the conductor structure. 122 contact. This allows the lower plate 30 and the upper plate 96 to be connected to the wires of the same wire layer under the capacitor 94. In contrast, the extension portion 1 4 can be manufactured by other conventional methods, such as a tungsten metal inlay process. The capacitor 94 manufactured according to the processes shown in Figures la to lg and Figures 2a to 2e has an important advantage That is, the process of copper inlaid wire manufacturing can be quickly added. Only one photomask is needed, which makes the semiconductor wafer manufacturing using this process overcome the obvious price pressure. Figures 1a to 1g and 2a to 2e The process shown includes a capacitor dielectric layer 60 and an upper plate 96 using a limited-etching process. The present invention also includes a capacitor dielectric layer 60 and an upper plate 96 using a damascene process, as shown in Figures 3 to 3d. As shown in the previous process steps shown in Figures 1a and 1b and Figure 2a, the lower plate 30 and the conductor structures 32 and 122 are formed in the insulating layer 24. The conductors in the 3 & to 3d diagrams The interlayer window structures 3 2 and 1 22 are optional and need to be provided only when the design of the contact plug 98 and the extension 134 is provided. The process shown in FIG. 3a and the processes shown in FIG. 3b and FIG. 2a The only difference shown is that it does not require a silicon nitride layer 48. The added openings 52 and 54 are as wide as the lower plate 30. Conversely, the opening 54 in the embodiment shown in Figures lb and 2a is smaller than the lower plate 3〇 also ----------------- r --- order --------- line (please read the notes on the back before filling this page)
479310 五、發明說明（） 寬。不远，本發明之第la至lg圖及第2a至2e圖所示之實施 例中同樣包含提供一開口 54的步驟，而該開口 54較下板3〇 為窄；而在第3a至3d圖所示之實施例中，該開口 54則較下 板3 0為寬。 接著，第3 b圖所繪示的製程，如前第1 c圖所示之製程 步驟。然後，如第3c圖所示，沉積一介電層60，沉積一銅 擴散阻障層62於介電層60之上’而一金屬層74則沉積於阻 障層62之上。應注意的是，金屬層74可以為銅、銘或是鋁 銅合金。如果金屬層74為鋁，則阻障層62可以省略。這和 前面第le圖中所敘述的完全相同。 然後，如第3d圖所示，半導體元件20以傳統化學機械 研磨法進行平坦化製程，以產生一個平面1 5 0。殘留在開 口 54中的金屬層74晶平坦化之後形成電容器94的上板 96。上板和擴散層60均形成於被動層40之中。雖未繪示於 圖中，形成上板9 6的同時，一延伸部1 3 4 (請參照第2 e圖） 至導線結構122和一接觸栓98(請參照第ig圖）至導線結構 3 2也可能形成。 本發明在以上所述之不同實施例包括在下板3 0的頂 端上形成一銅合金擴散阻障層5 6。一選擇性的做法包括沉 積一鋼擴散阻障層陳述如下，這是關於繪示於第4a至4f圖 本發明的一實施例。 本實施例的第一步驟繪示於第4a圖，這和第1 a至1 c圖 及第2a至2b圖所繪示的實施例的步驟相同。一樣的，如第 4b圖所示，開口 54的寬度大於下板30。與第lc、2b和3b圖 第u頁 本紙張尺度適用_國國家標準（CNS)A4規格（210 X 297公爱） -----------------r---訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 479310479310 V. Description of the invention () Wide. Not far, the embodiments shown in Figures la to lg and Figures 2a to 2e of the present invention also include the step of providing an opening 54 that is narrower than the lower plate 30; and in Figures 3a to 3d In the embodiment shown in the figure, the opening 54 is wider than the lower plate 30. Next, the process shown in Fig. 3b is the same as the process steps shown in Fig. 1c. Then, as shown in FIG. 3c, a dielectric layer 60 is deposited, a copper diffusion barrier layer 62 is deposited on the dielectric layer 60 ', and a metal layer 74 is deposited on the barrier layer 62. It should be noted that the metal layer 74 may be copper, aluminum, or an aluminum-copper alloy. If the metal layer 74 is aluminum, the barrier layer 62 may be omitted. This is exactly the same as described in the previous figure. Then, as shown in FIG. 3d, the semiconductor device 20 is subjected to a planarization process by a conventional chemical mechanical polishing method to produce a flat surface 150. After the metal layer 74 remaining in the opening 54 is flattened, an upper plate 96 of the capacitor 94 is formed. Both the upper plate and the diffusion layer 60 are formed in the passive layer 40. Although not shown in the figure, while forming the upper plate 96, an extension portion 1 3 4 (refer to FIG. 2e) to the lead structure 122 and a contact pin 98 (refer to FIG. Ig) to the lead structure 3 2 may also form. The different embodiments of the present invention include forming a copper alloy diffusion barrier layer 56 on the top end of the lower plate 30. An alternative approach involves depositing a steel diffusion barrier layer as described below. This is illustrated in Figures 4a to 4f of an embodiment of the present invention. The first step of this embodiment is shown in Fig. 4a, which is the same as the steps of the embodiment shown in Figs. 1a to 1c and Figs. 2a to 2b. Similarly, as shown in Fig. 4b, the width of the opening 54 is larger than that of the lower plate 30. Applicable to lc, 2b and 3b pages on page u This paper size is applicable _ National Standard (CNS) A4 (210 X 297 public love) ----------------- r- --Order --------- line (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 479310
經濟部智慧財產局員工消費合作社印製 五、發明說明（） 所繪示之製程不痛除在於並不在下板30頂端上方形成一 銅合金擴散阻障層，而是以在氮化矽層48之上和開口54之 内以物理氣相沉積、離子物理氣相沉積或化學氣相沉積沉 積一非同形的銅擴散阻障層180。層膜180以為妲、氮化 鈕'氮化鈕/钽、鈦、氮化鈦、@、氮化鎢及其它相似的材 質為佳，沉積的厚度在1至100奈米之間，並以約5〇奈米為 佳，雖然可能包括使用於如前所述阻障層62的任何材質， 除非可以如第4c圖所示可以進行非同形沉積的材質。層膜 1 80必須是非同形的（例如，側壁上的厚度除以底部的厚度 要小於1，較佳是小於〇 · 5 )，如此下述的均向蝕刻才會更簡 便。 接著’如第4d圖所示，阻障層1 80以過氧化氫為基底 的濕式蚀刻或以S F6、β C13、C12按相似的反應性離子4虫刻 來進行均向回蝕。這一除了阻障層1 8 〇垂直的部分，例如， 在開口 5 4側壁的邵分。同樣地，附在下板3 〇上的部分阻障 層1 80a以一般回蝕會稍微離開開口 54的側壁，這是非常的 重要’因為控制回蝕製程而使得部分阻障層i 8(^未被回蝕 至離開開口的側避而曝露出下板30，這意味下板完全被部 分阻障層1 8 0 a所覆蓋。 然後’如第4e圖所示，沉積電容器介電層60和鋼擴散 阻障層62，如第3c圖所示。然後，沉積一金屬層74，也如 第3 c圖所描述的有關。 最後，如第4f圖所示，半導體元件20被平坦化，如第 3c圖相關敘述所示。這個結果表示電容器94的上板96和介 ______第15頁 本紙張尺度適用中國國豕標準（CNS)A4規格（210 X 297公釐） -----r---訂---------^· (請先閱讀背面之注意事項再填寫本頁) 479310 經濟部智慧財產局員工消费合作社印製 A7 B7 五、發明說明（） 電層60均形成於被動層40之中。雖未繪示於第4f圖，形成 上板96的同時，一延伸134(請參照第2e圖）至導線結構122 和一接觸栓98(請參照第lg圖）至導線結構32也可能形成。 本發明的另一樣態是一三板電容器具有以金屬鑲嵌 沉積製程形成二下板和一上板，以及這種電容器的製造方 法。請參照第5a至5e圖，本發明的實施例以在一絕緣層224 形成一左溝渠222和一右溝渠223開始，其中絕緣層224可 為一半導體元件220的氧化矽層。第三溝渠226和/或第四溝 渠228有選擇性的形成於絕緣層224之内。 溝渠222和223如同如果被提供的溝渠226和228，然後 較佳的是如同填滿溝渠22般的填滿銅金屬，如同第1 a和1 b 圖的相關描述。這結果在溝渠222形成左下板230以及在溝 渠223形成右下板231。同樣地，導線結構232形成於溝渠 226之内以及導線結構233形成於溝渠228之内，較佳是以 前述的製程在溝渠中填滿銅。 形成溝渠222,223，226和228較佳的是使板230、231及 導線結構232，23 3位於同一導線層，所以，他們位在共同水 平面或幾乎共同水平面上。當銅是較佳的材質適用於下板 23 0,23 1及導線結構232,23 3，本發明則將重點置於使用鋁 或鋁銅合金來形成板和結構。鋁和鋁銅合金以習知的物理 氣相沉積、離子物理氣相沉積或化學氣相沉積以及類似的 方法沉積入溝渠222,223，226和228。阻障層56然後以前面 有關第lc圖所敘述的製程形成於下板230和231之頂端表 面上。 __ 第16頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ------1——訂---------線· (請先閲讀背面之注意事項再填寫本頁) 479310 經濟部智慧財產局員工消費合作社印製 A7 _ " --------- B7 五、發明說明（） k供一被動層240於絕緣層224之上包括氮化矽層 244、氧化矽層246和氮化矽層248。這些材質層是獨立的， 如前述的層44,46和48。 光阻層250沉積於氮化矽層248之上。圖案化光阻層 250而形成開口 252位於了板23〇的左上方及了板231的右 上方。 請參照第5b圖，開口 52向下延伸穿過被動層24〇絕緣 層224的頂端，和板230和231的頂端。這結果是在下板230 和231的上方，絕緣層224之内形成開口 254。如前所述在 絕緣層4 0内以蝕刻形成開口 5 4的製程亦可適用於形成開 口 254和 255。 接著請參照第5 c圖。圖中一高介電係數介電層2 6 〇沉 積於開口 254和255之内及被動層240之上。前述之適用於 介電層60的材質及製程皆可用於介電層26〇的沉積上。然 後，導體層262再沉積於介電層260之上，其中導電層26〇 以為低電阻材質為佳，並可加以前述之蝕刻化學物處理而 蝕刻成一開口 289。若導體層262以鋁銅合金為之，那麼一 薄膜堆疊10奈米/500奈米/10奈米的氮化鈥/銘銅合金/氮 化欽可用來作為導體層；導體層262若以耐熱金屬為之， 則一 10奈米/500奈米的氮化鈦/鎢堆疊可以被使用。要注意 的是圖中的厚度只用以說明，導體為任何厚度時均可以本 發明所揭露之習知技術使用化學物來進行蝕刻。 請繼續參照第5d圖。圖中絕緣層273沉積於導體層262 之上，其中絕緣層273以為聚醯胺旋塗在阻障層262之上並 第17頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚1 -- ---------1 —-----r—^---------線 (請先閱讀背面之注意事項再填寫本頁) 479310 經濟部智慧財產局員工消費合作社印製 A7 — —________ 五、發明說明（） 填滿開0254和255至厚度為1至30微米為佳，並以高出導 體層5微米為更佳。其它適合於絕緣層273的材質包括光敏 聚酿胺和苯并環丁晞（benzocyclobutene)。然後，光阻層278 沉積於絕緣層273之上，並加以圖案化，以形成一開口 288 於導線結構2 3 2之上。較佳的是開口 2 8 8向側邊延伸超過導 線結構2 3 2的邊緣。若使用者為光敏聚醯胺，那麼聚醯胺 不需加以圖案化。若開口（圖中未顯示）和導線結構23 3需要 形成接觸那麼開口便製作於導線結構光阻層2 7 8上方， 開口 2 8 8就同時形成。 接著參照第5 e圖’在半導體元件2 2 0以一蚀刻製程沿 開口 2 8 8向下蝕刻至導線結構2 3 2而形成一開口 2 8 9。首 先，導體層262被蝕刻。若導體層262為前述之氮化鈦/鎢， 此時可使用習用之含S F6和含氣的触刻劑。若導體層2 6 2為 氮化鈦/鋁銅合金/氮化鈦，那麼前述之習用含氯蝕刻劑可 適用之。另外，如果導體層2 6 2是其它金屬（例如是電鍍銅 沉積於一鉻黏著層之上），此時可使用以硫酸和過氧化氫 為主的濕式蝕刻劑。自開口 2 8 8處移除導體層2 6 2之後，以 前述習知的氟碳化物和氫氟碳化物的反應性離子蝕刻蚀 刻介電層260、並將導線結構232曝出，曝露出的導線結構 2 3 2則可導線接點連接（未繪示於圖上）。 如第5e圖所示，電容器294的上板296以延伸涵蓋並超 過左下板2 3 0和右下板2 3 1的外緣為佳。此非本發明的一必 然現象’涵蓋結構的優點在於消除位於電容器角落2 9 8的 弱電位區域。 ____ 第18頁 本紙張尺度適用中國國家標準（CNS)A4規格（21G X 297公爱）~ -----------------r-- 丨訂---------線· (請先閱讀背面之注意事項再填寫本頁) 479310 經濟部智慧財產局員工消費合作社印製 A7 B7 —_— 一_____ 五、發明說明（） 本發明繪示於第5a至5e圖的之實施例具有三板的電 容器含如上所述包括以一習知的沉積製程形成下板2 3 0和 23 1和導線結構232和233於溝渠之内。本發明也包含三板 電容294的製造，製造方式是利用蝕刻（subtractive etch)製 程而將下板及其它導線結構形成於同樣的導線層上，如第 6a至6g圖所示。在下面本發明實施例的敘述中，材質層的 材質和結構和本發明第5 a至5 e圖所述之實施例相同，並使 用相同的樣號，除了 2 0 0系列改為3 〇 〇系列之外皆然。舉例 說來，第5a圖中下板以230表示，而在第6c圖中下板以330 表示。 請參照第6 a圖，本發明之該樣態以半導體元件3 1 0當 作起始物，其中半導體元件3 1 〇具有一絕緣層3 1 2，導線3 1 4 和介層窗3 1 6形成於其中。接著，如第6b圖所示，使用如 前所述用於形成阻障層6 2的材質形成阻障層3 1 8，其厚度 為5至1〇〇奈米，較佳約為1〇奈米，沉積於絕緣層3 12之上。 接著’沉積一金屬層3 2 0於整個阻障層3 1 8之上（和提供的 其它任何阻障層之上）。金屬層320的材質可為鋁、鋁銅合 金、耐熱金屬銅及任何低阻值金屬，不過耐熱金屬（如鎢） 也是不錯的選擇，因其具有高抗腐蝕性。若使用者為鋼， 那麼一般都希望能提供一第二阻障層來當作阻障層62，其 材負為氮化赵、氮化组/赵（未緣示於圖上）。該阻障層6 2米 成於阻障層318之上’這在前文已有說明。金屬層320可以 物理氣相沉積、離子物理氣相沉積或化學氣相沉積及類似 的方法沉積，且所述之金屬層320可為多層金屬看。 第19頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) -------I---------丨 丨訂---------線411^ (請先閱讀背面之注意事項再填寫本頁) 479310 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 接著，如第6b圖所示，光阻層322沉積於金屬層320之 上。然後，圖案化光阻層322以形成開口 324a、324b、324c、 324d和 324e 〇 然後，如第6c圖所示，半導體元件3 1 〇以非均向蝕刻 之方式處理（如可以習知之含氯反應性離子加以蝕刻），向 下延伸開口 324a-e至絕緣層3 12的頂端表面。將光阻層322 剝離之後，剩下的金屬層3 2 0便形成左下板3 3 0、右下板 33 1、導線結構3 3 2和導線結構3 3 3。 請參照第6 d圖，由二氧化石夕所形成的介電層3 4 1 (厚度 為〇 · 1至1 0微米，較佳為0.5微米）沉積於絕緣層3丨2、下板 3 30和33 1和導線結構332和3 3 3之上。另外，上述之阻障層 341也可為習用之被動介電膜堆疊。接著，一氮化矽層343 沉積於介電層341之上，其厚度為0.1至1〇微米，並以為〇.5 微米為佳。接著，塗佈一光阻層3 5 0、並加以圖案化，以 形成開口 3 52a、352b和 3 53。 半導體元件3 1 0以非均向蝕刻方式處理（例如以反應 性離子蝕刻方式處理），向下延伸開口 3 52a、3 52b和3 5 3穿 過介電層343和341、左下板330、右下板331和導線結構 332，開口 35 4a、354b和355便形成於介電層341和343之 中，所形成之結構如第5b圖所述。接著，半導體元件3 1 0 以第5b圖所描述半導體元件220的處理製程步驟來進行處 理’這會形成一如第6a至6g圖所示之三板電容器394。三 板電容器294中，上板396以延伸涵蓋並超過左下板330和 右下板3 3 1的外緣為佳，但非必要。 ______第 201_____ 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） ----------------l·---訂---------線# (請先閱讀背面之注意事項再填寫本頁) 479310 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 三板電容器294和394只有具相同標示值（f00tprint) 之雙板堆疊電容器一半的電容值，以晶片以寶貴空間來提 供電容形成所需之空間觀點視之，這是一項缺點。但是， 因為電容器2 94和3 94可以很輕易與現今之半導體製程一 起進行（包括銅鑲嵌製程，一般僅需多一道光罩），因此在 低製造成本考量較高電容器密度考量為重要時，該電容器 不失為較佳之選擇。這樣的因素犧牲（tradeoff)在具較稀疏 電容器密度的混合訊號應用設計中是能被接受的。 如上所述，電容器94、294和394都形成於半導體元件 最上一層的導線層。此優點在於最上層區域金屬化導線可 以由基底自然隔離，並可由設計輕易隔離導線間的電容。 另外，最上層區域金屬化導線部會被溫度及較下層導線及 元件的污染物質所影響。 雖然電容器94、294和394是意欲製造相較於傳統較精 確比值電容器以適用於内階段（intra-stage)電路元件，但本 發明並不受限於此。例如，電容器9 4、2 9 4和3 9 4可更進一 步適用於混合訊號應用中，以提供一線性電路電相較於相 鄰的數位雜訊一電力去耦合。 如弟5a至5e及6a至6g圖所示之三板電容器294和 394，上板296和396可以被在基底上被製造的所有的電容 器分享。若無如此設計（例如上板296和396需彼此分隔）， 此時就需要另加上一道光罩及蝕刻製程（未繪示於圖上）來 圖案化並蚀刻上板，以達到隔離的目的。 本發明另一重要的優點在於第7a至7b圖所输示之平 _ 第 211 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ----------------^----^-------1 (請先閱讀背面之注意事項再填寫本頁) 4/^310Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention The process shown is not painful except that a copper alloy diffusion barrier layer is not formed above the top of the lower plate 30, but a silicon nitride layer 48 A non-shaped copper diffusion barrier layer 180 is deposited on and within the opening 54 by physical vapor deposition, ion physical vapor deposition, or chemical vapor deposition. The layer film 180 is preferably made of rhenium, nitride button, nitride button / tantalum, titanium, titanium nitride, @, tungsten nitride, and other similar materials. The deposited thickness is between 1 and 100 nanometers, and is approximately 50 nanometers is preferred, although it may include any material used for the barrier layer 62 as described above, unless a material that can be non-isomorphically deposited as shown in FIG. 4c. The layer film 180 must be non-isomorphic (for example, the thickness on the side wall divided by the thickness on the bottom is less than 1, preferably less than 0.5), so that the following isotropic etching will be more simple. Next, as shown in FIG. 4d, the barrier layer 1 80 is wet-etched on the basis of hydrogen peroxide or S F6, β C13, and C12 are similarly etched back by four reactive ions. This vertical portion except the barrier layer 180 is, for example, a shaw on the side wall of the opening 54. Similarly, part of the barrier layer 1 80a attached to the lower plate 30 will leave the side wall of the opening 54 slightly in general etchback, which is very important. Because of the control of the etch-back process, part of the barrier layer i 8 (^ 未Etching back to the side away from the opening exposes the lower plate 30, which means that the lower plate is completely covered by a partial barrier layer 180a. Then 'as shown in Figure 4e, the capacitor dielectric layer 60 and steel are deposited The diffusion barrier layer 62 is shown in FIG. 3c. Then, a metal layer 74 is deposited, as described in FIG. 3c. Finally, as shown in FIG. 4f, the semiconductor element 20 is planarized, as shown in FIG. This is shown in the relevant description of Figure 3c. This result indicates that the upper plate 96 and the capacitor of the capacitor 94______ page 15 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----- r --- Order --------- ^ · (Please read the notes on the back before filling out this page) 479310 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Electric layer 60 Both are formed in the passive layer 40. Although not shown in FIG. 4f, an extension 134 is formed while the upper plate 96 is formed (refer to FIG. 2e) To the lead structure 122 and a contact plug 98 (refer to FIG. 1g) to the lead structure 32 may also be formed. Another aspect of the present invention is that a three-plate capacitor has two lower and one upper plates formed by a damascene deposition process. And a method for manufacturing such a capacitor. Referring to FIGS. 5a to 5e, the embodiment of the present invention starts with forming a left trench 222 and a right trench 223 on an insulating layer 224, where the insulating layer 224 may be a semiconductor element 220. A silicon oxide layer. The third trench 226 and / or the fourth trench 228 are selectively formed in the insulating layer 224. The trenches 222 and 223 are like the trenches 226 and 228 if provided, and then preferably like filling the trenches. 22 is filled with copper metal, as described in Figures 1a and 1b. As a result, the lower left plate 230 is formed in the trench 222 and the lower right plate 231 is formed in the trench 223. Similarly, the wire structure 232 is formed in the trench 226 The inner and the lead structure 233 are formed in the trench 228, and the trench is preferably filled with copper by the aforementioned process. To form the trenches 222, 223, 226, and 228, it is preferable that the plates 230, 231 and the lead structures 232, 23 3 are located. Same guide Layer, so they are located on a common horizontal or almost common horizontal plane. When copper is a better material suitable for the lower plate 23 0,23 1 and the wire structure 232,23 3, the present invention will focus on the use of aluminum or aluminum Copper alloys to form plates and structures. Aluminum and aluminum-copper alloys are deposited into trenches 222, 223, 226, and 228 using conventional physical vapor deposition, ion physical vapor deposition, or chemical vapor deposition, and similar methods. The barrier layer 56 then It is formed on the top surfaces of the lower plates 230 and 231 by the process described in the foregoing FIG. __ Page 16 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 public love) ------ 1——Order --------- Line · (Please read the Note for this page, please fill out this page) 479310 Printed by A7 _ " --------- B7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () k for a passive layer 240 on the insulating layer 224 It includes a silicon nitride layer 244, a silicon oxide layer 246, and a silicon nitride layer 248. These texture layers are independent, such as the layers 44, 46, and 48 previously described. A photoresist layer 250 is deposited on the silicon nitride layer 248. The photoresist layer 250 is patterned to form an opening 252 located at the upper left of the plate 23 and the upper right of the plate 231. Referring to FIG. 5b, the opening 52 extends downward through the top of the passive layer 24 and the insulating layer 224, and the tops of the plates 230 and 231. As a result, an opening 254 is formed in the insulating layer 224 above the lower plates 230 and 231. The process of forming the openings 54 by etching in the insulating layer 40 as described above can also be applied to the formation of the openings 254 and 255. Then refer to Figure 5c. In the figure, a high-k dielectric layer 26 is deposited within the openings 254 and 255 and above the passive layer 240. The foregoing materials and processes suitable for the dielectric layer 60 can be used for the deposition of the dielectric layer 26. The conductive layer 262 is then deposited on the dielectric layer 260. The conductive layer 26 is preferably a low-resistance material, and can be etched into an opening 289 by the aforementioned etching chemical treatment. If the conductor layer 262 is made of aluminum copper alloy, then a thin film stack of 10 nm / 500 nm / 10 nm can be used as the conductor layer; if the conductor layer 262 is heat resistant, For metals, a 10nm / 500nm titanium nitride / tungsten stack can be used. It should be noted that the thickness in the figure is only used for illustration. When the conductor is any thickness, the conventional techniques disclosed in the present invention can be used to etch using chemicals. Please continue to refer to Figure 5d. In the figure, the insulating layer 273 is deposited on the conductor layer 262, wherein the insulating layer 273 is spin-coated on the barrier layer 262 with polyamine and page 17 This paper is in accordance with China National Standard (CNS) A4 (210 X 297) Gongchu 1---------- 1 ------- r-^ --------- line (please read the notes on the back before filling this page) 479310 Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative A7 — — ________ 5. Description of the invention () It is better to fill in 0254 and 255 to a thickness of 1 to 30 microns, and it is better to be 5 microns higher than the conductor layer. Other suitable for insulation The material of the layer 273 includes photosensitive polyamine and benzocyclobutene. Then, a photoresist layer 278 is deposited on the insulating layer 273 and patterned to form an opening 288 in the wire structure 2 3 2 It is preferable that the opening 2 8 8 extends to the side beyond the edge of the lead structure 2 3 2. If the user is a photosensitive polyamide, then the polyamide need not be patterned. If the opening is not shown (not shown in the figure) It is necessary to make contact with the wire structure 23 3 and the opening is made over the wire structure photoresist layer 2 7 8. The opening 2 8 8 is Then, referring to FIG. 5e ', an etching process is performed on the semiconductor element 2 20 along the opening 2 8 8 down to the wire structure 2 3 2 to form an opening 2 8 9. First, the conductor layer 262 is etched. If the conductor layer 262 is the aforementioned titanium nitride / tungsten, conventional etchants containing S F6 and gas can be used. If the conductor layer 2 6 2 is titanium nitride / aluminum-copper alloy / titanium nitride, then The aforementioned conventional chlorine-containing etchant is applicable. In addition, if the conductor layer 2 6 2 is other metal (for example, electroplated copper is deposited on a chromium adhesion layer), sulfuric acid and hydrogen peroxide may be used as the main layer. Wet etchant. After removing the conductive layer 2 6 2 from the opening 2 8 8, the dielectric layer 260 is etched with the conventional reactive ion of fluorocarbon and hydrofluorocarbon, and the wire structure 232 is exposed. The exposed wire structure 2 3 2 can be connected by wire contacts (not shown in the figure). As shown in Figure 5e, the upper plate 296 of the capacitor 294 extends to extend beyond the lower left plate 2 3 0 and right The outer edge of the lower plate 2 3 1 is better. This is not an inevitable phenomenon of the present invention. The advantage of the covered structure is that Eliminate the weak potential area at the corner of the capacitor 2 9 8. __ Page 18 This paper size applies Chinese National Standard (CNS) A4 specification (21G X 297 public love) ~ -------------- --- r-- 丨 Order --------- Line · (Please read the notes on the back before filling in this page) 479310 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 —_— 一 _ ____ 5. Description of the invention () The embodiment of the present invention shown in Figures 5a to 5e has a three-plate capacitor. As described above, it includes forming a lower plate 2 3 0 and 23 1 and a wire structure 232 by a conventional deposition process. And 233 within the ditch. The present invention also includes the manufacture of a three-plate capacitor 294. The manufacturing method is to form a lower plate and other wire structures on the same wire layer by using a subtractive etch process, as shown in FIGS. 6a to 6g. In the following description of the embodiment of the present invention, the material and structure of the material layer are the same as the embodiment described in Figures 5a to 5e of the present invention, and the same sample number is used, except that the 2000 series is changed to 300. It's the same outside the series. For example, the lower plate in Fig. 5a is represented by 230, and the lower plate in Fig. 6c is represented by 330. Please refer to FIG. 6a. In this aspect of the present invention, the semiconductor element 3 1 0 is used as a starting material. The semiconductor element 3 1 0 has an insulating layer 3 1 2, a conductive wire 3 1 4 and an interlayer window 3 1 6. Formed in it. Next, as shown in FIG. 6b, the barrier layer 3 1 8 is formed using the material for forming the barrier layer 62 as described above, and the thickness is 5 to 100 nanometers, preferably about 10 nanometers. Meters, deposited on the insulating layer 3 12. Next, a metal layer 3 2 0 is deposited on the entire barrier layer 3 1 8 (and any other barrier layer provided). The material of the metal layer 320 can be aluminum, aluminum-copper alloy, heat-resistant metal copper, and any low-resistance metal, but heat-resistant metals (such as tungsten) are also good choices because of their high corrosion resistance. If the user is steel, it is generally desirable to provide a second barrier layer as the barrier layer 62, and the material negatives are Nitride Zhao, Nitride Group / Zhao (not shown in the figure). The barrier layer 62 is formed on the barrier layer 318 'as described above. The metal layer 320 may be deposited by physical vapor deposition, ionic physical vapor deposition or chemical vapor deposition, and the like, and the metal layer 320 may be a multilayer metal. Page 19 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------- I --------- 丨 丨 Order -------- -Line 411 ^ (Please read the precautions on the back before filling this page) 479310 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Then, as shown in Figure 6b, the photoresist layer 322 is deposited On the metal layer 320. Then, the photoresist layer 322 is patterned to form openings 324a, 324b, 324c, 324d, and 324e. Then, as shown in FIG. 6c, the semiconductor element 3 1 0 is processed by means of non-uniform etching (such as the conventional chlorine-containing chlorine). Reactive ions are etched), and the openings 324a-e are extended downward to the top surface of the insulating layer 312. After the photoresist layer 322 is peeled off, the remaining metal layer 3 2 0 forms a lower left plate 3 3 0, a lower right plate 33 1, a lead structure 3 3 2 and a lead structure 3 3 3. Referring to Fig. 6d, a dielectric layer 3 4 1 (thickness of 0.1 to 10 microns, preferably 0.5 microns) formed from the dioxide is deposited on the insulating layer 3 2 and the lower plate 3 30 And 33 1 and wire structures 332 and 3 3 3. In addition, the above-mentioned barrier layer 341 can also be a conventional passive dielectric film stack. Next, a silicon nitride layer 343 is deposited on the dielectric layer 341 with a thickness of 0.1 to 10 micrometers, and preferably 0.5 micrometers. Next, a photoresist layer 3 50 is applied and patterned to form openings 3 52a, 352b, and 3 53. The semiconductor element 3 10 is processed by anisotropic etching (for example, by reactive ion etching), and the openings 3 52a, 3 52b, and 3 5 3 extend through the dielectric layers 343 and 341, the lower left plate 330, and the right The lower plate 331 and the wire structure 332, and the openings 35 4a, 354b, and 355 are formed in the dielectric layers 341 and 343. The structure formed is as shown in FIG. 5b. Next, the semiconductor element 3 1 0 is processed according to the processing steps of the semiconductor element 220 described in FIG. 5b. This will form a three-plate capacitor 394 as shown in FIGS. 6a to 6g. Of the three-plate capacitors 294, the upper plate 396 preferably extends beyond the outer edges of the lower left plate 330 and the lower right plate 3 31, but is not necessary. ______Article 201_____ This paper size applies to China National Standard (CNS) A4 (21〇X 297mm) ---------------- l · --- Order ---- ----- 线 # (Please read the notes on the back before filling out this page) 479310 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () The three-plate capacitors 294 and 394 only have the same marked value ( f00tprint), which is half of the capacitance value of a two-plate stacked capacitor. This is a disadvantage from the perspective of the chip providing valuable space to form the capacitor. However, because capacitors 2 94 and 3 94 can be easily carried out with today's semiconductor processes (including copper damascene processes, generally only one more photomask is needed), so when low manufacturing costs and higher capacitor density considerations are important, A capacitor is a better choice. Such a factor tradeoff is acceptable in mixed signal application designs with sparse capacitor densities. As described above, the capacitors 94, 294, and 394 are all formed on the uppermost wiring layer of the semiconductor element. This advantage is that the metallized wires in the uppermost layer can be naturally isolated by the substrate, and the capacitance between the wires can be easily isolated by design. In addition, the metallized lead portion in the uppermost area is affected by temperature and pollutants from the lower level wires and components. Although the capacitors 94, 294, and 394 are intended to be used to manufacture intra-stage circuit elements with a more accurate ratio than conventional capacitors, the present invention is not limited thereto. For example, capacitors 9 4, 2 9 4 and 3 9 4 can be further adapted for mixed signal applications to provide a linear circuit that is electrically decoupled from adjacent digital noise and power. As shown in the figures 5a to 5e and 6a to 6g of the three-plate capacitors 294 and 394, the upper plates 296 and 396 can be shared by all the capacitors manufactured on the substrate. If there is no such design (for example, the upper plates 296 and 396 need to be separated from each other), a mask and an etching process (not shown in the figure) need to be added to pattern and etch the upper plate to achieve the purpose of isolation . Another important advantage of the present invention lies in the level shown in Figures 7a to 7b. _ 211 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) ---------- ------ ^ ---- ^ ------- 1 (Please read the notes on the back before filling this page) 4 / ^ 310
、發明說明（ a面（例如介面18&和18b之平面金屬層-介電層-金 ，:面)可不需使用這消除了平面MIM介面上存在之 金屬污染造成漏電流路徑的可能性。 —雖然本發明以較佳實施例揭露如上，然其並非用以限 二^ 任何熟習此技蟄者，在不脫離本發明之精神和 ,内田可作各種之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 第22肓 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）The invention description (a plane (such as the planar metal layer-dielectric layer-gold of the interface 18 & and 18b) can be omitted. This eliminates the possibility of leakage current paths caused by metal pollution on the planar MIM interface. — Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit it. Anyone skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention (Please read the notes on the back before filling out this page) (Printed on the back page of the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperatives, 22nd) This paper size applies Chinese National Standards (CNS) A4 size (210 X 297 mm)