TW543175B - Method for integrating MIM copper capacitor device, inductance device, and copper wire - Google Patents

Abstract

The present invention provides a manufacture of MIM structured capacitor using copper as conductor, which comprises the steps of: first providing a semiconductor substrate having a surface formed thereon a first copper block for use as the lower electrode of the capacitor device; next, globally forming a first dielectric layer on the semiconductor substrate; then, selectively removing the first dielectric layer to form a first opening for exposing the first copper block, thereby defining the range of the upper electrode of the capacitor device; next, forming an insulating layer at the bottom and sidewall of the first opening for use as an insulating layer of the capacitor device; and finally filling copper into the first opening for use as the upper electrode of the capacitor device. The present invention manufactures MIM capacitor by using single damascene process of copper, instead of introducing the aluminum-copper alloy depositing and etching steps. Furthermore, the present invention is able to simultaneously form the upper electrode of MIM capacitor, plug of the inductor, and plug of copper wire, thereby simplifying the process and reducing the cost.

Description

543175 V. Description of the invention (l) The present invention relates to a method for manufacturing MIMO copper capacitor elements, and more particularly to a method for integrating MIMO copper capacitors, inductors, and copper wires. The plug and the copper wire plug can be formed simultaneously. Please refer to FIGS. 1A to 1C, which show the cross-sectional schematic diagrams of the process of integrating copper conductors and capacitors in the conventional technology. First, please refer to FIG. 1A. Symbol 10 indicates a semiconductor substrate on which several integrated circuits have been formed. Symbols 11 a and 1 1 b indicate copper blocks used as copper wires and electrodes under the capacitor element, respectively. Symbol 2 Denotes an insulating layer formed on the surface of the semiconductor substrate 10, and the symbol 20 represents a metal layer made of, for example, an aluminum-copper alloy. Next, referring to FIG. 1B, a lithography process and a conventional etching step are used to selectively etch the above-mentioned metal layer 20 to form an electrode 20a on the capacitor element. In this way, a metal-insulator-metal (MIM) capacitor with 1 ib as the lower electrode, 12 as the insulating layer, and 20a as the upper pole is configured. 'Then, referring to FIG. 1C, the copper process is continued to form an insulating layer 3 0 formed of, for example, silicon dioxide, and then the above-mentioned insulating layer 3 is selectively etched to form a contact hole and an interconnect trench. (Trench) double mosaic opening DD. Next, referring to FIG. 11}, copper metal is filled into the above-mentioned double damascene opening D D ′ and subjected to chemical mechanical polishing (c μ p) to form a copper wire 32. However, in the above-mentioned conventional technology, the M capacitor and the copper wire must be separated into two steps and cannot be formed at the same time, which will cause inconvenience to the process operation and increase complexity. And ’after the capacitor 20a is formed on the capacitor,

543175

Insulating layer 30, the insulating layer in the capacitor portion will be higher, and when there is a topography situation, when two mosaic openings dd are connected, a y-engraved pattern will be formed during exposure: in view of this, the present invention The purpose is to provide a method for manufacturing a MIM capacitor using a copper damascene of copper (Damascene of copper) process without introducing aluminum copper a to the deposition and etching steps. Another object of the present invention is to provide a manufacturing process for simultaneously forming an electrode on a MIM capacitor and a copper wire, thereby simplifying the manufacturing process and reducing costs. Yet another object of the present invention is to provide a process for simultaneously forming a plug on an M 丨 M capacitor and an inductor, thereby simplifying the process and reducing it to 0. Another object of the present invention is to provide a method for simultaneously forming a MIM capacitor. The process of plugging electrodes, inductors, and copper wires can simplify the process and reduce costs. In order to achieve the purpose of the present invention, the method for manufacturing a copper capacitor element according to the present invention includes the following steps: (a) providing a semiconductor substrate having a first copper block on the surface of the substrate as an electrode under the capacitor element; b) comprehensively forming a first dielectric layer over the semiconductor substrate; (c) selectively removing the first dielectric layer to form a first opening exposing the first copper block to define the capacitor element The range of the upper electrode; (d) forming an insulating layer on the bottom and side walls of the first opening to serve as the insulating layer of the capacitor element; and (e) filling the first opening with copper metal to Used as the electrode above the capacitor. According to the present invention, it is also possible to integrate the MM copper capacitor element and the inductance element,

543175 V. Description of the invention (3) Simultaneously forming a plug between the electrode on the capacitive element and the inductive element 'This method includes the following steps ... (a) Provide a semiconductor substrate whose surface is divided into a capacitor region and an inductor region. The capacitor region has a first copper block, which is used as the lower electrode of the capacitor element, and has a second copper block on the inductor region; (b) a first dielectric layer is comprehensively formed over the semiconductor substrate; (c ) On the capacitor region, selectively removing the first dielectric layer to form a first opening exposing the first copper block to define a range of electrodes above the capacitor element; (d) on the first opening Forming / insulating layer on the bottom and side walls to serve as the insulating layer of the capacitor element; (e) selectively removing the first dielectric layer on the inductor region to form a second opening exposing the second copper block To define the plug of the inductive element; and (f) at the same time, fill the first opening and the second opening with copper metal 'to serve as the electrode above the capacitive element and the plug of the inductive element, respectively. According to the invention, the following step area and surface area of the capacitive element are simultaneously formed, and (d) of the block is a capacitor element according to the present invention: (a) a wire area is lifted, an electrode is lower, and the semiconductor is selectively Except for the first step, half of the capacitor is formed by opening the first dielectric layer of the insulating layer of the capacitor element, and the capacitor is supplied on the copper conductive substrate to the bottom of the first step. (E) The copper capacitor is exposed. The method includes plugging a component and a copper wire, and a pole and a copper wire. The method includes a conductor substrate. The surface of the substrate is divided into a capacitor region having a first copper block as a third copper block on the wire region. (B) A first dielectric layer is formed on all sides; (c) a capacitor-dielectric layer is formed to expose a range of electrodes above the first copper region and the valley element; and an insulating layer is formed on the side wall to serve as the copper wire. Area, the third opening of the second copper block is selectively removed to define

543175 V. Description of the invention (4) Insert the copper wire plug; and (f) Fill copper metal into the first opening and the third opening at the same time as the electrodes on the capacitor element and the copper wire, respectively. The plug. According to the present invention, M 丨 M copper capacitor element, inductor element, copper wire] can also be integrated to form an electrode on the capacitor element, the plug of the inductor element and the plug of the copper wire at the same time. This method includes the following steps ... (a ) A semiconductor substrate is provided. The surface of the substrate is divided into a capacitor region, an inductor region, and a copper wire region. A first copper block is provided on the capacitor region as a lower part of the capacitor element. The second copper block has three copper blocks on the copper wire area; (b) a first w electrical layer is formed comprehensively above the semiconductor substrate, (c) on the capacitor area, the first A dielectric layer forms a first opening exposing the first copper block to define a range of electrodes above the capacitive element; (d) forming an insulating layer on the bottom and sidewalls of the first opening as the An insulating layer of the capacitor element; (e) selectively removing the first dielectric layer while forming a second opening exposing the second copper block, so as to define a plug of the inductive element and forming the first element to be exposed; The second opening of the three copper blocks to define the Copper wire plugs; and (f) simultaneously filling copper openings in the ^ opening, the first opening, and the second opening to serve as the electrode above the capacitor element, the plug for the inductor element, and the copper Plug of the wire. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Brief description of the drawings:

543175 _ Case No. 89112061 _ year month day _ ^ _ V. Description of the invention (5) The first 1 ~ 1D diagram is a schematic cross-sectional view of the process of traditionally integrating copper wires and capacitor elements. Figures 2A to 2G are schematic cross-sectional views of a manufacturing process of integrating a μ I μ copper capacitor, an inductor, and a copper wire according to a preferred embodiment of the present invention. Description of component symbols: 100 ~ semiconductor substrate, 610 ~ capacitor area, 6200 ~ inductance area, 630 ~ copper wire area, 110 ~ first copper block, 120 ~ second copper block, 130 ~ third copper block, 140 ~ etch stop layer, 150 ~ first dielectric layer 150, 160 ~ first opening, 200 ~ insulation layer, 220 ~ second opening, 230 ~ third opening, 310 ~ capacitor element electrode, 320 ~ inductive element Plug of 330 ~ copper wire, 400 ~ second dielectric layer, 410 ~ first trench, 420 ~ second trench, 430 ~ third trench, 510, 520, 530 ~ copper interconnect line. EXAMPLES The following is a schematic cross-sectional view of the process of integrating the capacitive element, the inductive element, and the copper wire shown in FIGS. 2A to 2G to illustrate the preferred embodiment of the present invention. 0 First, please refer to FIG. 2A. The semiconductor substrate of the integrated circuit is divided into a capacitor region 610, an inductor region 620, and a copper wire region 630. A first copper block 110 is provided on the capacitor region 610 as a lower electrode of the capacitor element, a second copper block 120 is provided on the inductor region 620, and a third copper block 130 is provided on the copper wire region 630. An etch stop layer 140, such as Si ON, is formed on the semiconductor substrate 100 in a comprehensive manner. Next, a first dielectric layer 150, such as a silicon dioxide layer, is formed in a comprehensive manner. The formation method can be a chemical vapor deposition (CVD) method.

0503-5288TWF2: TSMC1999-0676: CATHY.ptc Page 8 543175 V. Description of the invention (6) Reading the 2β diagram 'on the capacitor area 610, using the lithography process technology to selectively remove the first dielectric layer 150. The etch stop layer 14o and the first opening σ16 of the -th copper block 11G define the range of the capacitor element ^ =. For example, a photoresist is used as a mask, and anisotropic etching is performed by a reactive ion money engraving method. Next, referring to FIG. 2C, an insulating layer 200 is formed at the bottom and the side wall of the first opening 160 as an insulating layer of the capacitor element. For example, a chemical vapor deposition process is used to form an insulating layer 200 on the surface of the first dielectric layer 150, which extends to the bottom and sidewalls of the first opening 160. The insulating layer 200 can be formed by SiN, SiN, SiON, etc. In the case of TaN, TaN Π is also used as a diffusion barrier iayer to prevent the diffusion of copper, so it is particularly suitable. The ratio of Ta and N can be adjusted as needed to obtain a TaN insulating material with a desired dielectric constant. Next, referring to FIG. 2D, the insulating layer 2000, the first dielectric layer 150, and the etch stop layer 14 are selectively removed, and at the same time, a second opening 220 is formed to expose the second copper block 1 ^ 0. To define the plug of the inductive element, and to form a third opening 23, which exposes the third copper block 30, to define the plug of the copper wire. For example, a series of steps such as coating photoresist, baking, exposure, and development can be performed using a lithography process to form a photoresist pattern (not shown), and then this photoresist pattern is used as an etching mask to selectively etch the insulation The layer 200, the first dielectric layer 150, and the etch stop layer 400 are formed, and the second opening 220 and the third opening 230 are formed at the same time. Next, read Figure 2E, and simultaneously fill copper in the first opening 260, the second opening 220, and the first opening 230. For example, using electrochemical sinking

543175 V. Description of the invention (7) Elect ro-chemi cal deposition (ECD) comprehensively forms a copper metal layer to fill in the first opening 160, the second opening 220, and the third opening 230. Into copper metal. Next, chemical mechanical polishing (CMP) is used to planarize the copper metal layer and remove the insulating layer 2 0 ′ to form electrodes 310 on the capacitor element, plugs 320 of the inductor element, and copper wires. Plug 33〇. Next, referring to FIG. 2F, a second dielectric layer 400, such as a dioxide layer, is comprehensively formed. Next, the second dielectric layer 400 is selectively removed to simultaneously form a first trench 410 exposing the electrode 310 above the capacitive element and a second trench 4 2 forming a plug 3 20 exposing the inductive element. 0, and a third trench 4 3 0 forming a plug 3 3 0 exposing the copper wire. For example, a series of steps such as coating photoresist, baking, exposure, and development can be performed using a lithography process to form a photoresist pattern (not shown) having grooves 40, 420, and 430, and then the photoresist is used. The pattern is used as an etching mask, and a dielectric layer 400 'is selectively etched to form the above trench. Then, referring to FIG. 2G, copper metal is simultaneously filled in the first trench 410, the second trench 4 2 0, and the third trench 4 3 0. For example, an electrochemical deposition method (ECD) is used to comprehensively form a copper metal layer to fill the first trench 410, the second trench 420, and the third trench 430 with copper metal. Next, chemical mechanical polishing (CMP) is used to planarize the copper metal layer to form copper interconnects 5i, 520, and 530, respectively. To sum up, the present invention provides a method for manufacturing a MI capacitor by using a single damascene process of copper without introducing the aluminum-copper alloy deposition and etching steps.

Page 10 543175 V. Description of the invention (8). The invention can simultaneously form an electrode on the MIMO capacitor, a plug of the inductor, and a plug of the copper wire, thereby simplifying the manufacturing process and reducing the cost. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

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Claims (1)

543175 Correction: A method for integrating copper capacitor elements, inductor elements, and copper wires, including the following steps: (a) Provide a semiconductor substrate whose surface is divided into a capacitor region, an inductor region, and a copper wire region. The capacitor area has a first copper block, which is used as the lower electrode of the power valley element, a second copper block on the inductance area, and a third copper block on the copper wire area; (b) comprehensive Forming a first dielectric layer over the semiconductor substrate; (C) on the capacitor region, selectively removing the first dielectric layer to form a first opening out of the first copper block to define (D) forming an insulating layer on the bottom and side walls of the first opening to serve as the insulating layer of the capacitive element; (e) selectively removing the first dielectric The electrical layer forms a second opening exposing the second copper block at the same time to define a plug of the inductive element, and a third opening exposing the third copper block to define a plug of the copper wire. ; And (f) simultaneously in the first opening, the second Fill into the mouth, and a third opening copper metal, as respectively on the electrode of the capacitor, the inductance element of the plug is inserted, and insertion of the copper wire plug. 2. The method as described in item 1 of the scope of patent application, after the step (f) is performed, further comprising the following steps: forming a second dielectric layer comprehensively; selectively removing the second dielectric layer while simultaneously Forming a first trench exposing an electrode above the capacitive element, forming a second trench exposing a plug of the inductive element, and forming a third trench exposing a plug of the steel wire; and 0503-5288TWF1: TSMC1999-0676; CATHY.ptc ^ brother page 543175 At the same time, copper interconnects are formed in the first trench and the second metal '. The method according to item 丨 of the scope of patent application, wherein before the step-stopping layer is further included, a comprehensive formation is formed over the semiconductor substrate-where the remaining moment is stopped in the insulating layer and the insulating layer 4 · The method stop layer described in item 3 of the patent application scope is SiON. 5. The method described in item 1 of the scope of patent application is to select the group consisting of TaN, SiN, and SiON. 6 The method described in item 5 of the scope of patent application is TaN 〇7. The method according to item 1, wherein the eighth electric layer is dioxide; ; 8. The method as described in item 1 of the scope of the patent application, wherein the step (f) of the copper method includes: J Zhen comprehensively forms a copper metal layer by an electrochemical deposition method; and the chemical mechanical polishing method is used to perform the above Flattening of the steel metal layer.