TW583752B - Method of forming MIM capacitor integrated with damascene process - Google Patents

Abstract

A method of forming a metal-insulator-metal (MIM) capacitor integrating damascene. First, a substrate embedded with a bottom electrode and a lower wiring layer is provided. Next, a first dielectric layer, having first and second openings to respectively expose the bottom electrode and the lower wiring layer, is deposited on the substrate. The width of the first opening is larger than the second one. Next, a first metal layer is formed over the surface of the first opening and fills the second one by electrochemical plating. Next, a conformable capacitor dielectric layer is formed over the first metal layer in the first opening. Finally, the first opening is filled with a second metal layer as a top electrode.

Description

583752

Field of the Invention: The present invention relates to a method for manufacturing a metal-insulator-metal capacitor (M I M), and more particularly to a method for integrating metal-insulator-metal capacitors. . '' Prior technology: Capacitors are the key components of today's semiconductor integrated circuits, such as mixed-signal circuits, high-frequency circuits, analog and digital circuits. Typical capacitor structures in integrated circuits include metal-insulator-semiconductor (MIS) capacitors, PN junction capacitors, and polycrystalline stone-insulator-polycrystalline stone (p.o.). lysilic〇n — insulator — polysi 1 icon (PIP) capacitor. These capacitors include at least one Shi Xi layer as a capacitor electrode. In the above circuit, it is necessary to have high-performance high-speed capacitors, low series resistance, and low power loss. However, the use of a silicon layer as a capacitor electrode has the disadvantages of higher series resistance and instability in high-frequency circuits. Therefore, a metal-insulator-metal (MIM) capacitor has been developed to provide low series resistance. In addition, in order to have high performance, today's hybrid ancient wear-through circuits or high-frequency circuits need to use a copper dual damascene process. Therefore, it is necessary to make a metallization process that is integrated with the dual damascene process. '' Traditionally, copper processes have been integrated into capacitor processes only in planar-type capacitors. The following describes the conventional method of integrating the mosaic process in the manufacturing of MEMS capacitors with reference to Figures 1a to 1c. First, please refer to the i &

583752 V. Description of the invention (2) Intermetal dielectric (IMD) 102 is deposited on the substrate 100. Among them, a copper lower electrode 103 and a lower copper wire layer 104 are formed in the first all-in-one sound by a damascene process. After that, a capacitor dielectric layer and a metal-to-metal interlayer dielectric layer 102 are formed to make a MIM capacitor. Next, a photoresist layer 110 is formed on the metal layer 108 to define an electrode above the MIM capacitor. Next, please make a photolithography process on the photoresist layer 丨 丨 0 to expose part of the metal layer 108 as shown in Figure 1b. Next, the metal layer 108 which is not covered with the photoresist pattern layer 110a is etched to expose the capacitor dielectric layer 106. The remaining metal layer 108a is used as the upper electrode of the MIM capacitor. Finally, please sign Figure 1c. After removing the photoresist pattern layer, the manufacturing of the horizontal MIM capacitor 109 is completed. Next, a second metal interlayer dielectric layer 112 is deposited over the upper electrode 108a and the capacitor dielectric layer 106. After chemical mechanical polishing (CMP) is used to planarize the second metal interlayer dielectric layer 112, the upper electrode 108 is exposed by lithographic etching to form interlayer holes 114 and 115 therein. And the lower wire layer 104. However, the height difference between the upper electrode 108a and the lower wiring layer 104 causes the depth of the via hole 114 to be different from the via hole 115. In the above case, it is very difficult to precisely control the etching of the via hole. Therefore, the upper electrode 08a is easily damaged due to excessive time. Furthermore, in the above-mentioned capacitor manufacturing process, more than one lithography process is needed, which increases the manufacturing steps and manufacturing costs. In addition, limited by the utilization space of the wafer, horizontal capacitors cannot provide a larger effective electrode area, which will lead to the inability to obtain larger capacitance values in future generations of high-density mixed-signal circuit applications.

0702-8995twf (nl); 91P62; SPIN.ptd 583752 V. Description of the invention (3) Summary of the invention: In view of this, during the process of manufacturing a metal-inlay process and saving the metal-insulator of the present invention (crown-type is different) The depth is based on the above-mentioned metal making, which has a wide opening on the first lower electrode, an opening on the inside, an opening, a dielectric, and a first, on the first, the dielectric layer is buried on the insulating surface, and the shape is larger than that Four openings and two opening electrodes above the first filling layer are connected to power down. The purpose of the present invention is to provide a method for integrating a mosaic-insulator-metal-type (Μ Μ) capacitor, so as to simultaneously manufacture the Μ I Μ capacitor and Metal plugs are used to reduce manufacturing costs. Another purpose is to provide a method of integrating a damascene process to manufacture a metal capacitor, which forms a crown-shaped ΜIM capacitor to avoid square dielectric holes in the MEMS capacitor and the conductor layer. Increase its capacitance. OBJECT ' The present invention provides a method for integrating a damascene process into a product-metal capacitor. First, a substrate is provided with a lower electrode and a lower wiring layer. Depositing on the substrate, and then forming a first opening in the first dielectric layer to expose a second opening to expose the lower wiring layer, where the first = opening. Then, a first metal layer is opened on the first by electrochemical plating and filled in the second opening. After that, a capacitive dielectric layer is conformably formed on the gold f layer. The second metal layer is used as an upper electrode. Next, a first dielectric layer is formed in the first / second layer, in which a third opening is formed and located above the first opening and the second opening, respectively. A third metal layer is filled in the last and fourth openings to serve as the contact area and an upper metal layer, respectively. Electrode, lower wire layer, first metal layer, and third gold

0702-8995twf (nl); 91P62; 583752 V. Description of the invention (4) The metal layer can be a copper metal layer and surrounded by nitride and barrier materials. Furthermore, the second metal layer includes at least a titanium nitride layer or a nitrided layer. Furthermore, the capacitor dielectric layer may be a silicon nitride layer or a carbide carbide layer. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with the accompanying drawings as follows: Embodiments: The following descriptions are given in conjunction with Figures 2a to 2h. The integrated post-mounting process of the embodiment of the present invention is a method for manufacturing a metal-insulator-metal capacitor (MIM). First, please refer to FIG. 2a to provide a semiconductor substrate 200, such as a Shixi wafer. In this embodiment, the substrate 200 includes different elements, such as transistors, diodes, and other conventional semiconductor elements (not shown). In addition, the substrate 200 also includes other metal interconnect layers. In order to simplify the drawing, a flat substrate is shown here in gold. Then, in the substrate 2000, a metal-metal interlayer dielectric layer (IMD) 202 is embedded with the following ::: main 3 * and; forming a lower wire layer 204. The metal interlayer dielectric layer 202 is composed of a single-layer or multi-layer dielectric material. = s ， / the two dielectric layers 2 ° 2 can be made of stone dioxide, phosphorus stone glass (PSG), sapporo stone stone glass (R R ρ ς r, upper, lower, lower diamond, etc.), or Fluorine-doped silica glass (FSG… Diamond Temple Low, the layer 204 made of electrical material can be made of copper metal to attack the electrode 203 and the lower layer ¥ line and / or by a barrier material (not shown)

0702-8995twf (nl); 91P62; SPIN.ptd page 8 583752

Surround, such as titanium / titanium nitride (Ti / TiN) or button / nitride button (Ta / TaN) and then 'deposit another interlayer dielectric layer 2 06 on the interlayer dielectric layer 2 06. It may be made of silicon dioxide , Low-dielectric materials such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorine-doped silicate glass (FSG), black diamond, and its preferred thickness is 4,000 to 1 Next, please refer to FIG. 2b, and use a photoresist mask layer (not shown) to etch the metal interlayer dielectric layer 206, for example, using conventional reactive ion etching. (Reactive ion etch, RIE). In this step, a damascene trench 207 is formed to expose the lower electrode 203 and a via hole 209 is formed to expose the lower wiring layer 204. In the present invention, the width of the damascene trench 207 is greater than The via hole 2 0 9. For example, the critical dimension (CD) of the mosaic trench 2 07 is about 5 micrometers, and the via hole 20 9 is about 0.2 micrometers. Next, please Referring to Figure 2c, using conventional deposition techniques, such as chemical vapor deposition (CVD) or physical vapor deposition Physical vapor deposition (PVD), a barrier layer 2 1 0 is formed on the interlayer dielectric layer 2 06 and the inner surface of the damascene trench 2 07 and the dielectric hole 2 0 9 conforms to this barrier. The layer 2 10 may be composed of titanium / titanium nitride (Ti / TiN) or button / tantalum nitride (Ta / TaN) and has a thickness in the range of 100 to 300 Angstroms. Then, by electrochemical Electrochemical plating (ECP), conformally forming a metal layer 2 1 2 such as a copper metal layer over the barrier layer 2 10. In the present invention, the electroplating process includes the following steps:

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A copper seed layer (not shown) is deposited over the barrier layer 210 to a thickness of about 100 to 300 angstroms. Next, a copper metal layer 212 is deposited on the copper seed layer by Ecp to a thickness ranging from about 100 to 800 angstroms. Since the width of the via hole 209 is smaller than the damascene trench 207, the copper metal layer 212 will completely fill the via hole 209 in the above-mentioned deposition process, and conformally form the resistance in the damascene trench 207. Above the barrier layer 210, as shown in FIG. 2C. Next, referring to FIG. 2d, a dielectric layer 214 is conformably formed over the metal layer 212 by a conventional deposition technique, such as CVD. This dielectric layer 2 1 4 is a conventional valley dielectric material, such as silicon nitride or silicon carbide. Here, in order to manufacture a capacitor having a larger capacitance value in a subsequent process, a thinner dielectric layer 214 is used, for example, the thickness thereof is in a range of 100 to 1000 angstroms. 'Next, by a conventional deposition technique, such as cVD, a metal layer 216 is formed above the dielectric layer 2 and 4 and completely fills the damascene trench 207, as shown in FIG. 2d. In the present invention, the metal layer 216 may be composed of titanium / titanium nitride (Ti / TiN) or group / nitride (Ta / TaN), and its thickness is about "0 Angstroms.

Next, please refer to FIG. 2e. Using conventional polishing techniques, such as CMP, sequentially remove the excess metal layer 216 over the metal interlayer dielectric layer 206, the dielectric layer 214, the metal layer 212, and the barrier layer. 210. The remaining metal layer 21 2a and the remaining barrier layer 21a in the via hole 209 serve as a metal plug n 5 to be in electrical contact with the underlying wire layer 204. In addition, the remaining metal layer 216a, the remaining dielectric layer 214a, the remaining metal layer 2i2b, and the remaining barrier layer 2 1 0 b in the damascene trench 2 07 are configured with the lower electrode 2 03 A coronal mi Μ capacitor 217 'wherein the remaining metal layer 216a serves as an upper electrode and the remaining dielectric

5. Description of the invention (7) The electric layer 214a is used as a capacitor dielectric layer. Next, referring to FIG. 2f, another inter-metal dielectric layer 218 is deposited over the inter-metal dielectric layer 206. Preferably, the thickness of the metal interlayer dielectric layer 218 is in the range of 400 to 100 angstroms. Next, the metal interlayer dielectric layer 218 is etched by a photoresist mask layer (not shown). For example, RIE 'is used to form an inlay trench 219 to expose the metal plug in the dielectric hole 209. 21 5 and forming a mosaic trench 221 to expose the mosaic trench capacitor 217.

Next, please refer to FIG. 2g. Using a conventional deposition technique, such as PVD or ECP, a metal layer 222 surrounded by a resistive layer 220 is formed on the interlayer dielectric layer 218 and completely fills the mosaic Trenches 21 9 and 221. In the present invention, the barrier layer 22 may be composed of titanium / titanium nitride (Ti / TiN group / nitride nitride (Ta / TaN), and the metal layer 222 may be composed of copper metal. Finally, please refer to Section 2h Figure, by the conventional grinding technology, such as CMP, sequentially remove the metal interlayer dielectric layer 2! 8 ± excess metal layer 222 and the resist layer 220. The remaining metal layer in the trench 219 is embedded, and the rest is used as a The upper wire layer 223 is in electrical contact with the wire layer 2G4 through the metal plug 215. In addition, the remaining ^ 222b and the remaining barrier layer 22b in the money insertion slot 221 serve as an upper electrode contact area 225 Compared with the conventional technology, the crown capacitor of the present invention can be formed simultaneously with the metal plug in the inlaying process. Because of &, the manufacturing process can be effectively simplified. The electrode of the M I M capacitor of the present invention does not require additional micro This step can reduce the manufacturing cost. In addition, compared with the conventional horizontal type called electricity 1 3752 V. Description of the invention (8) The crown capacitor of the present invention provides a larger effective electrode area to obtain a larger capacitance value. Furthermore, since the interface between the lower electrode and the capacitor dielectric layer has not undergone a CMP process, This may have a better interface quality. That is, the crown M IM capacitor of the present invention has a higher breakdown voltage and a lower interface leakage current. Although the present invention has been disclosed above in a preferred embodiment, it is not useful. To limit the present invention, anyone skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

0702-8995twf (nl); 91P62; SPIN.ptd Page 12 53752 Brief Description of Drawings Figures 1a to 1c are cross-sectional schematic diagrams showing a conventional integrated damascene process for manufacturing MIMO capacitors. Figures 2a to 2h are schematic cross-sectional views showing a method for manufacturing a MEMS capacitor by an integrated damascene process according to an embodiment of the present invention. Explanation of symbols: 100 ~ semiconductor substrate; 102 ~ first metal interlayer dielectric layer 103 ~ copper lower electrode; 104 ~ lower copper wire layer; 106 ~ capacitor dielectric layer; 108 ~ metal layer; 108a ~ Upper electrode; I 09 ~ Capacitor; II 0 ~ Photoresist layer; 110a ~ Photoresist pattern layer; 114 The present invention 200 202 203 204 112 ~ Second metal interlayer dielectric layer 1 15 ~ Interlayer hole. Semiconductor substrate; 206, 218 ~ metal interlayer dielectric layer; lower electrode; lower wire layer;

0702-8995twf (nl); 91P62; SPIN.ptd page 13 583752 Simple illustration of the diagram 2 0 7, 2 1 9, 2 2 1 ~ Inlaid trench; 2 0 9 ~ Via hole; 2 1 0, 2 2 0 ~ barrier layer; 210a, 210b, 220a, 220b ~ remaining barrier layer; 212, 216, 222 ~ metal layer; 212a, 212b, 216a, 222a, 222b ~ remaining metal layer; 2 1 4 ~ Dielectric layer; 214a ~ remaining dielectric layer; 215 ~ metal plug; 217 ~ capacitor; 223 ~ upper wire layer; 2 2 ~ upper electrode contact area.

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Claims (1)

583752 VI. Scope of patent application 1. A method for integrating a damascene process in manufacturing a metal-insulator-metal capacitor, including at least the following steps: providing a substrate with a lower electrode and a lower conductor layer embedded on the surface; on the substrate Depositing a first dielectric layer; forming a first opening in the first dielectric layer to expose the lower electrode and forming a second opening to expose the lower wiring layer, wherein the width of the first opening is larger than the second opening Forming a first metal layer on the inner surface of the first opening and filling the second opening by electrochemical plating; compliantly forming a capacitive dielectric layer on the first metal layer of the first opening; and A second metal layer is filled in the first opening to serve as an upper electrode. 2. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 1 of the scope of the patent application, further comprising the following steps: depositing a second dielectric layer over the first dielectric layer; A third opening and a fourth opening are formed in the second dielectric layer and are located above the first opening and the second opening, respectively; and a third metal layer is filled in the third opening and the fourth opening. As an upper electrode contact area and an upper metal layer, respectively. 3. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 2 of the scope of the patent application, wherein the second dielectric layer is a metal interlayer dielectric layer. 4. Integrated inlaying process as described in item 2 of the patent application scope 0702-8995twf (nl); 91P62; SPIN.ptd page 15 583752 6. Method of applying for a patent metal-insulator-metal capacitor, wherein the third metal layer is a copper metal layer and is blocked by a barrier material Surrounded. 5. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 4 of the scope of the patent application, wherein the barrier material is titanium nitride or tantalum nitride. 6 · The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 1 of the scope of patent application, further comprising forming a barrier layer between the first dielectric layer and the first metal layer . 7. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 6 of the scope of patent application, wherein the barrier layer is a titanium nitride layer or a nitride group layer. 8. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 6 of the scope of the patent application, wherein the thickness of the barrier layer is in the range of 100 to 300 angstroms. 9. The method of integrating a damascene process as described in item 1 of the scope of application for manufacturing a metal-insulator-metal capacitor, wherein the lower electrode and the lower wire layer are a copper metal layer. 10. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 1 of the scope of the patent application, wherein the first dielectric layer is a metal-to-metal dielectric layer. 11. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 1 of the scope of the patent application, wherein the first metal layer is a copper metal layer. 1 2.Integrate the inlay process as described in item 11 of the scope of patent application 0702-8995twf (nl); 91P62; SPIN.ptd page 16 583752 6. Method of applying for a patent to make a metal-insulator-metal capacitor, wherein the thickness of the metal layer is between 1 0 0 0 and 8 0 0 0 Angstroms. Range. 1 3. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 1 of the scope of the patent application, wherein the capacitor dielectric layer is a nitrided layer or a carbide chip. 1 4. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 13 of the scope of the patent application, wherein the thickness of the capacitor dielectric layer is in the range of 100 to 100 angstroms. . 1 5. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 1 of the scope of the patent application, wherein the second metal layer includes at least a nitride layer or a nitride group layer. 16. A method of integrating a damascene process into manufacturing a metal-insulator-metal capacitor, including at least the following steps: providing a substrate with a copper lower electrode and a lower copper conductor layer embedded on the surface; depositing a substrate on the substrate A metal interlayer dielectric layer; forming a first opening in the metal interlayer dielectric layer to expose the lower electrode and forming a second opening to expose the lower wiring layer, wherein the width of the first opening is greater than the second opening; A barrier layer is formed over the metal dielectric layer and the inner surfaces of the first and second openings; a first metal layer is conformably formed over the barrier layer by electrochemical plating and completely fills the second opening Compliantly forming a capacitive dielectric layer over the first metal layer; 0702-8995twf (nl); 91P62; SPIN.ptd page 17 583752 6. The scope of the patent application is to conform to form a second metal layer above the capacitive dielectric layer; and to remove the brother above the dielectric layer of the delta metal layer Two metal layers, the capacitor electrical layer, the first metal layer, and the barrier layer to form a metal-insulator in the first opening ~ a metal capacitor and a metal plug in the second opening Stuffed. 17 · The method of integrating & manufacturing metal & insulator-metal type capacitor as described in item 16 of the scope of patent application, wherein the barrier layer includes at least a titanium nitride layer or a nitride button The stratum has a thickness in the range of 100 to 300 Angstroms. 18. The method of integrating a damascene process into a metal-insulator-metal capacitor as described in item M of the scope of the patent application, wherein the first metal layer is a copper metal layer and has a thickness of 1000 to 80 0 0 Angstrom range. 19 · The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 16 of the scope of the patent application, wherein the capacitor dielectric layer is a silicon nitride layer or a carbide chip and its thickness In the range of 100 to 100 Angstroms. The system described in the process of inlaying and fitting is described in item 6 I 丄 利 Fan Li, please apply as such. Fang Guangzhi's silver-capacitance electro-nitrogen type is a genus or gold layer-titanium physicochemical marginal nitrogen. I includes metal, including gold, and less. It is made of gold. It is described in item 6 of the process and mosaic setting. Wei Fanli specially requested Shen Ru to learn the mechanics of mechanical mechanics, and borrowed from the bank to belong to the second, the law of the party. Fang Guangrong Capacitors Electrical layer resistance type electrical and metal layers, I layer layer, material layer, edge gold and gold, except I, go to the gold mill, research layer 0702-8995twf (nl); 91P62; SPIN.ptd page 18