TW200418137A - Method of forming MIM capacitor integrated with damascene process - Google Patents

Abstract

A method of forming a metal-insulator-metal (MIM) capacitor integrating damascene. First, a substrate embedded with a bottom electrode and a lower wiring layer is provided. Next, a first dielectric layer, having first and second openings to respectively expose the bottom electrode and the lower wiring layer, is deposited on the substrate. The width of the first opening is larger than the second one. Next, a first metal layer is formed over the surface of the first opening and fills the second one by electrochemical plating. Next, a conformable capacitor dielectric layer is formed over the first metal layer in the first opening. Finally, the first opening is filled with a second metal layer as a top electrode.

Description

200418137

Field of the Invention: The present invention relates to a method for manufacturing a metal-insulator-metal capacitor (MIM), and more particularly to a method for integrating a damascene process to manufacture a metal-insulator-metal capacitor. Prior technology: Electric Valley is a key component of today's semiconductor integrated circuits, such as hybrid circuits, high-frequency circuits, analog and digital circuits. Typical capacitor structures in integrated circuits include metal-insulator-semiconductor (MIS) capacitors, ρν junction capacitors, and polysilicon-insulator-polysilicon— insulator- polysilicon (PIP) capacitor. These capacitors include at least one stone layer as a capacitor electrode. In the above circuit, it is necessary to have high-performance high-speed capacitors, low series resistance, and low power loss. However, using Shi Xi as the electrode of the capacitor will have the disadvantages of higher series resistance and instability in high frequency circuits. Therefore, a metal-insulator-metal (MIM) capacitor has been developed to provide a lower series resistance. In addition, in order to have high performance, today's mixed-signal circuits or high-frequency circuits need to use a copper dual damascene process. Therefore, it is necessary to integrate the production of capacitors into the metallization process of the dual damascene process. Traditionally, the copper process has been integrated into the capacitor process only in planar-type capacitors. The following describes the conventional method of integrating a mosaic process in manufacturing a capacitor with the ia to ic diagrams. First, please refer to FIG. I a to provide a semiconductor substrate, such as a semiconductor wafer. One first

0702-8995twf (nl); 91P62; SPIN.ptd page 5 200418137 V. Description of the invention (2)-" 'Intermetal dielectric (10) 10 2 system / substrate on the substrate 100 . Among them, a copper lower electrode 103 and a lower copper wire layer 104 are formed in the first metal interlayer dielectric layer 102 by a damascene process. Thereafter, a capacitor dielectric layer 106 and a metal layer 108 are sequentially deposited on the first metal interlayer dielectric layer 102 to form a MIM capacitor. Next, a complex photoresist layer 11Q is formed on the metal layer 108 to define the electrodes on the MIM capacitor. Next, referring to FIG. 1b, a photolithography process is performed on the photoresist layer to expose a part of the metal layer 108. Next, the metal layer 108 not covered by the photoresist pattern layer 110a is etched to expose the capacitor dielectric layer 106. The remaining metal layer 108a is used as the upper electrode of the MIM capacitor. Finally, referring to FIG. 1c, after the photoresist pattern layer is removed, the manufacturing of the horizontal MIM capacitor 109 is performed. Next, a second metal interlayer dielectric layer 112 is deposited over the upper electrode 108a and the dielectric layer 106. After chemical mechanical polishing (CMP) is used to planarize the first metal interlayer dielectric layer 1 and 2, the upper electrodes 108 and 115 are exposed by lithographic etching to form the interlayer holes 114 and 115 in the middle. The lower wire layer 104. However, the difference in height between the upper electrode 108a and the lower wiring layer 104 causes the depth of the via hole 114 to be different from the via hole 115. In the above case, it is very difficult to precisely control the etching of the via hole. Therefore, the upper electrode 8a is easily damaged by the last name. Furthermore, in the above-mentioned capacitor manufacturing process, more than one lithography process is required, thereby increasing the manufacturing steps and manufacturing costs. In addition, “Limited by the use space of the wafer, horizontal capacitors cannot provide a larger effective electrode area”, which will lead to the inability to obtain larger capacitance values in future generations of high-density mixed-signal circuit applications.

Page 6 200418137 V. Description of the invention (3) Summary of content: The purpose of the present invention is to provide a method for integrating grapes in the manufacture of metal-insulator-metal-type (MIM) capacitors. MIM capacitors and metal plugs, which can be used for private steps and save manufacturing costs. Another / objective of the present invention is to provide a method for integrating a metal-insulator to metal-type capacitor in a damascene process. By forming a crown-type ΜΜ capacitor, it is possible to avoid the formation of via holes with different depths in the MI capacitor and the conductor layer. And increase its capacitance. According to the above-mentioned object, the present invention provides a method for manufacturing a metal-insulator-metal capacitor by integrating mosaic. First, provide, the lower electrode and the lower wire layer are embedded on the surface. A first dielectric layer is formed on the substrate, a first opening lower electrode is formed in the first dielectric layer, and a second opening is formed to expose the lower wiring layer, and the opening width is larger than the second opening. Next, a first metal layer is formed on the inner surface of the mouth by electrochemical plating and filled in the second opening. A capacitive dielectric layer is formed on the first metal layer of the opening conformably. An opening is filled with a second metal layer as an upper electrode. A second dielectric layer is then deposited over a dielectric layer, and a first and a fourth opening are formed and located above the first and second openings, respectively. A third metal is filled in the third and fourth openings Layer, which is an upper electrode contact area and an upper metal layer. The above-mentioned lower electrode, the lower wiring layer, the first metal layer, and: the embedding process is to make a VL product on a substrate in order to expose the first VL product on the substrate in the manufacturing process. , In the third opening. Finally make a third gold

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0702-8995twf (nl); 91P62; SPIN.ptd page 7 200418137 V. Description of the invention (4)-The metal layer can be a steel metal layer and surrounded by barrier materials such as titanium nitride or nitride button. Furthermore, the second metal layer includes at least a titanium nitride layer or a nitride button layer. Furthermore, the capacitor dielectric layer may be a silicon nitride layer or a silicon carbide layer. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following 4-inch preferred embodiments will be described in detail with the accompanying drawings as follows:

The following describes the method of manufacturing a metal-insulator-metal capacitor (MIM) with the integrated inlay process of the embodiment of the present invention with reference to Figures 2a to 2h. First, please refer to FIG. 2a to provide a semiconductor substrate 2000, such as a Shixi wafer. In this embodiment, the substrate 200 includes different elements, such as transistors, diodes, and other conventional semiconductor elements (not shown). In addition, the substrate 200 also includes other metal interconnect layers. For the sake of simplification of the diagram 'here the gold edge shows a flat substrate. Then connected ~ two bases.

^ Fang, / Er product a metal interlayer dielectric layer (IMD) 2 0 2, which is embedded with a Ί 3 and a lower wire layer 2 0 4. This metal interlayer dielectric layer 202 is composed of two examples: single-layer or multi-layer * electrical materials used in: stomach ::. The interlayer dielectric layer 202 may be made of silicon dioxide or phosphosilicate glass.

), Re-drilling; sixen glass (BPSG), or fluorine-doped silica glass (FS layer m can be made of copper metal?). The lower pole 20 3 and the lower wire are formed badly and they break a barrier material ( (Not shown)

200418137

Surrounded by, for example, titanium / titanium nitride (Ti / TiN) or button / nitride button (Ta / TaN). Next, another metal interlayer dielectric layer 206 is deposited on the metal interlayer dielectric layer 2 0. Made of low dielectric materials such as silicon oxide, phosphosilicate glass (pSG), borophosphosilicate glass (BPSG), or fluorine-doped silicate glass (FSG), black diamond, etc., and its preferred thickness is 4,000. To the range of 丨 〇〇〇〇〇angstrom.

Next, referring to FIG. 2b, the interlayer dielectric layer 20 6 is etched by a photoresist mask layer (not shown), for example, using conventional reactive ion etch (RIE). In this step, a damascene trench 207 is formed to expose the lower electrode 203, and a via hole 209 is formed to expose the lower wiring layer 204. In the present invention, the width of the damascene trench 207 is larger than the via hole 209. For example, the critical dimension (CD) of the mosaic trench 207 is about 5 micrometers, and the via hole 209 is about 0.2 micrometers.

Next, "Clear Tea Photo 2c" is hunted by conventional deposition techniques, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), on the interlayer dielectric layer 206. And the compliance between the embedded trench 207 and the inner surface of the via 209 forms a barrier layer 2 1 0. The barrier layer 2 10 may be composed of titanium / titanium nitride (Ti / TiN) or a group / nitride group (Ta / TaN), and its thickness is in the range of 100 to 300 angstroms. Then, a metal layer 2 1 2 such as a copper metal layer is conformably formed on the barrier layer 2 1 0 by electrochemical plating (ECP). In the present invention, the plating process includes the following steps:

0702-8995twf (nl); 91P62; SPIN.ptd Page 9 200418137 V. Description of the invention (6) ---- PVD deposits a thickness in the range of about 100 to 300 angstroms above the barrier layer 2 100. Copper seed layer (not shown). Next, a copper metal layer 212 having a thickness of about 1000 to 8000 angstroms is deposited on the copper seed layer by ECP. Because the via hole 209 is smaller than the inlaid trench 207, the copper metal layer 2 12 will be filled by the king in the above-mentioned deposition process; the interlayer hole 209 'is conformally formed in the inlaid trench 2 〇 The resistance layer in Fig. 7 is above the 2 1 0 layer, as shown in Fig. 2c.

Next, referring to FIG. 2d, a dielectric layer 2 4 is conformably formed on the metal layer 2 1 2 by a conventional deposition technique, such as C VD. The dielectric layer 214 may be a commonly used capacitive dielectric material, such as silicon nitride or silicon carbide. Here, in order to manufacture a capacitor having a larger capacitance value in a subsequent process, a thinner dielectric layer 214 is used, for example, the thickness thereof is in a range of 100 to 1000 angstroms. Then, by a conventional deposition technique, such as c VD, a metal layer 216 is formed above the dielectric layer 2 and 4 and completely fills the damascene trench 207, as shown in FIG. In the present invention, the metal layer 216 may be composed of titanium / titanium nitride (Ti / TiN) or tantalum / nitride button (Ta / TaN), and its thickness is about 500 angstroms. Next, referring to FIG. 2e, by conventional polishing techniques such as CMP, the excess metal layer dielectric layer 214, metal layer 212, and barrier layer 21 over the metal interlayer dielectric layer 206 are sequentially removed. . The remaining metal layer 21 2a and the remaining barrier layer 2ioa in the via hole 209 serve as a metal plug 215 to make electrical contact with the lower wiring layer 204. In addition, the remaining metal layer 216a, the remaining dielectric layer 214a, the remaining metal layer 21b, and the remaining barrier layer 21 in the embedded trench 207 form a crown shape with the lower electrode 203. MIM capacitor 217, wherein the remaining metal layer 216a is used as an upper electrode and the remaining dielectric

0702-8995twf (nl); 91P62; SPIN.ptd page 10 200418137

The electrical layer 214a functions as a capacitor dielectric layer. Next, referring to FIG. 2f, another inter-metal dielectric layer 218 is deposited over the inter-metal dielectric layer 206. Preferably, the thickness of the metal interlayer dielectric layer 218 is in the range of 40,000 to 10,000 angstroms. Next, the metal interlayer dielectric layer 218 is etched by a photoresist mask curtain layer (not shown). For example, Rj E is used to form a damascene trench 2 1 9 and the dielectric hole 2 09 is exposed. Metal plug

The plug 215 and a damascene trench 221 are formed to expose the MIM capacitor 217 in the damascene trench 207.

Next, according to Fig. 2g, a metal layer 222 surrounded by a barrier P early layer 220 is formed on the interlayer dielectric layer 218 by a conventional deposition technique, such as CVD, PVD, or ECP, and Completely fill the inlaid trenches 219 and 221. In the present invention, the barrier layer 22 may be made of titanium / titanium nitride (Ti / TiN) or group / nitride (Ta / TaN), and the metal layer 22 2 may be made of copper metal. Finally, please refer to Figure 2h. Using conventional grinding techniques, such as * CMp, sequentially remove the excess metal layer 222 and barrier layer 220 over the interlayer dielectric layer 218. The remaining metal layer 222a and the remaining barrier layer 220a in the inlay trench 219 are used as an upper conductive layer 223, and are electrically contacted with the lower conductive layer 204 through the metal plug 215. In addition, the remaining metal layer 222b and the remaining barrier layer 220b in the damascene trench 2 21 serve as an upper electrode contact region 225. Compared with the conventional technology, the crown capacitor of the present invention can be formed simultaneously with the metal insert during the damascene process. Therefore, the process can be effectively simplified. Furthermore, the MEMS capacitor upper electrode of the present invention can be formed without an additional lithography step, thereby reducing the manufacturing cost. In addition, compared to the conventional horizontal capacitor

200418137 V. Description of the invention (8) The crown capacitor of the present invention provides a larger effective electrode area to obtain a larger capacitance value. Furthermore, since the interface between the lower electrode and the capacitor dielectric layer has not undergone the CMP process, it can have better interface quality. That is, the crown M IM capacitor of the present invention has a higher breakdown voltage and a lower interface leakage current. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

0702-8995twf (nl); 91P62; SPIN.ptd page 200418137 Brief description of the drawings Figures 1a to 1c are cross-sectional schematic diagrams showing a conventional integrated damascene process for manufacturing MIMO capacitors. Figures 2a to 2h are schematic cross-sectional views showing a method of integrating a mosaic process to manufacture a ML capacitor according to an embodiment of the present invention. Explanation of symbols: conventional 100 ~ semiconductor substrate; 102 ~ first metal interlayer dielectric layer; 103 ~ lower copper electrode; 104 ~ lower copper wire layer; 106 ~ capacitor dielectric layer; 108 ~ metal layer; 1 0 8a ~ upper electrode, 109 ~ capacitor; 110 ~ photoresist layer; 110a ~ photoresist pattern layer; 11 ~ 2 second interlayer dielectric layer; 114, 115 ~ via hole. In the present invention, a semiconductor substrate of 200 to 20, 2, 06, 2 18 to an intermetal dielectric layer, 230 to a lower electrode, and 204 to a lower wire layer;

0702-8995twf (nl); 91P62; SPIN.ptd page 13 200418137 Brief description of the diagram 2 0 7, 2 1 9, 2 2 1 ~ Inlaid trench; 2 0 9 ~ Via hole; 210, 220 ~ Barrier 210a, 210b, 220a, 220b ~ remaining barrier layer; 212, 216, 222 ~ metal layer; 212a, 212b, 216a, 222a, 222b ~ remaining metal layer 214 ~ dielectric layer; 214a ~ remaining The remaining dielectric layer; 215 ~ metal plug; 217 ~ capacitor; 2 2 3 ~ upper wire layer; 2 2 5 ~ upper electrode contact area.

0702-8995twf (nl); 91P62; SP] N.ptd page 14

Claims (1)

200418137 VI. Scope of patent application 1. A method for integrating a damascene process into manufacturing metal-insulator-metal capacitors, including at least the following steps: Provide a substrate with a lower electrode and a lower-layer wire base embedded in the surface. = 口 = 口 1 The bottom layer of the dielectric layer α af,; 0W layer-electrical-dielectric-first-middle-layer-line-conducting layer should be exposed under D; The first time the electrode is turned on, the first one should be exposed, it is gold-the first forming surface, the inner mouth is the first one, the second is electroplating, and the second is the second one. The upper part of the sex should be Jinyi first; the opening of the mouth should be opened first, the first entry should be filled in the stratified electrode ^ ¾ The first one is filled with the gold second first entry -δα Kai-and the first; Electricity please apply as 2 Material Marriage-The Golden Law Fang Rong Di Fan Li is a type of Li Jinzhuan I made in the process of inlay and integration, the steps are listed in the following steps and D four •, first floor Electrical and interface two open three one first product one sinking into a square on the middle layer of the dielectric layer dielectric two one helium in the first layer of gold three and the first one •, enter the middle D port 0 yuan S Khan, the 2nd, 4th, Haihaikou, Gukou, and DD Kaikai, the 1st, 3rd Haishi, 5th, and 1st, which belong to its gold in the U-story of the relocated Beshan Mountain, and the first-floor & the first law in the J-1 -The first and second electrical contact type of the storage area is extremely profitable. I applied for the product to be a perfect match. 3-It is made of gold and is manufactured by the process system. Inlaid whole • The 2nd paragraph of the description. Fan Lili's special introduction of electricity, please refer to Jianshen layer 4. Gold 0702-8995twf (nl); 91P62; SPIN.ptd page 15 200418137 6. Method of applying for a patent metal-insulator-metal capacitor, wherein the third metal layer is a copper metal layer and is blocked by a barrier material Surrounded. 5. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 4 of the scope of patent application, wherein the barrier material is titanium nitride or tantalum nitride. 6. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 1 of the scope of the patent application, further comprising forming a barrier layer between the first dielectric layer and the first metal layer . 7. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 6 of the scope of the patent application, wherein the barrier layer is a nitride layer or a nitride group layer. 8. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 6 of the scope of the patent application, wherein the thickness of the barrier layer is in the range of 100 to 300 angstroms. 9. The method of integrating a damascene process as described in item 1 of the scope of application for manufacturing a metal-insulator-metal capacitor, wherein the lower electrode and the lower wire layer are a copper metal layer. 10. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 1 of the scope of the patent application, wherein the first dielectric layer is a metal-to-metal dielectric layer. 11. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 1 of the scope of the patent application, wherein the first metal layer is a copper metal layer. 1 2.Integrate the inlay process as described in item 11 of the scope of patent application 0702-8995twf (nl); 91P62; SPIN.ptd page 16 200418137 6. Method of patent application for making a metal-insulator-metal capacitor, wherein the thickness of the metal layer is between 1 0 0 0 and 8 0 0 0 Angstroms Range. 1 3. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 1 of the scope of the patent application, wherein the capacitor dielectric layer is a nitrided layer or a carbonized layer. 1 4. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 13 of the scope of the patent application, wherein the thickness of the capacitor dielectric layer is in the range of 100 to 100 angstroms. . 1 5. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 1 of the scope of the patent application, wherein the second metal layer includes at least a nitride layer or a nitride group layer. 16. A method of integrating a damascene process into manufacturing a metal-insulator-metal capacitor, including at least the following steps: providing a substrate with a copper lower electrode and a lower copper conductor layer embedded on the surface; depositing a substrate on the substrate A metal interlayer dielectric layer; forming a first opening in the metal interlayer dielectric layer to expose the lower electrode and forming a second opening to expose the lower wiring layer, wherein the width of the first opening is greater than the second opening; A barrier layer is formed over the metal dielectric layer and the inner surfaces of the first and second openings; a first metal layer is conformably formed over the barrier layer by electrochemical plating and completely fills the second opening Compliantly forming a capacitive dielectric layer over the first metal layer; 0702-8995twf (nl); 91P62; SPIN.ptd page 17 200418137 Sixth, the scope of the application for a patent conforms to form a second metal layer above the capacitor dielectric layer; and removes the second metal layer above the interlayer dielectric layer A metal layer, the capacitor dielectric layer, the first metal layer, and the barrier layer to form a metal-insulator-metal capacitor in the first opening and a metal plug in the second opening . 1 7. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 16 of the scope of patent application, wherein the barrier layer includes at least a titanium nitride layer or a nitride button layer and the The thickness is in the range of 100 to 300 Angstroms. 1 8. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 16 of the scope of the patent application, wherein the first metal layer is a copper metal layer and has a thickness of 100 to A range of 8 0 0 0 Angstroms. 19. The method of integrating a damascene process for manufacturing a metal-insulator-metal capacitor as described in item 16 of the scope of the patent application, wherein the capacitor dielectric layer is a silicon nitride layer or a silicon carbide layer and has a thickness In the range of 100 to 100 Angstroms. 20. The method of manufacturing a metal-insulator-metal capacitor according to the integrated damascene process described in item 16 of the scope of the patent application, wherein the second metal layer includes at least a nitride layer or a nitride group layer. 2 1. The method of integrating a damascene process to manufacture a metal-insulator-metal capacitor as described in item 16 of the scope of patent application, wherein the second metal layer above the metal interlayer dielectric layer is removed by chemical mechanical polishing , The dielectric layer, the first metal layer, and the barrier layer. 0702-8995twf (nl); 91P62; SPIN.ptd page 18