CN103594415B - The forming method of semiconductor device - Google Patents
The forming method of semiconductor device Download PDFInfo
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- CN103594415B CN103594415B CN201210287337.6A CN201210287337A CN103594415B CN 103594415 B CN103594415 B CN 103594415B CN 201210287337 A CN201210287337 A CN 201210287337A CN 103594415 B CN103594415 B CN 103594415B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of forming method of semiconductor device, including: substrate is provided；Substrate is formed some discrete the first metal layers；Performing etching the sidewall of the first metal layer, the width making the first metal layer is consistent with design width；Side wall is formed on the sidewall of the first metal layer after etching；Form the second metal level, described second metal level upper surface and the first metal layer upper surface flush on substrate between discrete the first metal layer, and have side wall to isolate each other；Remove described side wall or remove described the first metal layer and the second metal level.The forming method of semiconductor device of the present invention, utilize self-alignment type double exposure photolithographic process to be formed in back-end process in semiconductor device to be spaced and interconnection line that density is bigger or connector, simplify processing step, reduce technology difficulty and manufacturing cost, and this technique is easily accurately controlled, improve the performance of formed semiconductor device.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to the forming method of a kind of semiconductor device.
Background technology
Along with the making of integrated circuit develops to super large-scale integration (ULSI), its internal current densities is increasingly
Greatly, contained number of elements is continuously increased so that the surface of wafer cannot provide enough area to make required interconnection line
(Interconnect).The interconnection line demand that increased after reducing for co-operating member, utilizes more than the two-layer that through hole realizes
The design of multiple layer metal interconnection line, becomes the method that very large scale integration technology must use.
Traditional metal interconnection is realized by aluminium, but along with device feature size in IC chip
Constantly reducing, the electric current density in metal connecting line constantly increases, and response time constantly shortens, and conventional aluminum interconnection line has reached technique
The limit.After process is less than 130nm, traditional aluminum interconnecting technology is the most gradually replaced by copper interconnecting line technology.With
Aluminum metallic matrix ratio, the resistivity of copper metal is lower, electromigration lifetime is longer, and utilizing process for copper to make metal interconnecting wires can reduce
The RC of interconnection line postpones, improves the integrity problem that electromigration etc. causes.But, use process for copper to make interconnection line and there is also two
Individual problem: one is that the diffusion velocity of copper is very fast, and two is the etching difficulty of copper, therefore, its manufacturing process being suitable for and aluminum
Technique is entirely different, it will usually use mosaic texture to realize in the way of filling.
Fig. 1 to Fig. 5 is the schematic diagram that existing technique forms interconnection line, below in conjunction with Fig. 1 to Fig. 5, forms existing technique
The forming method of interconnection line is described in detail.First, with reference to Fig. 1, it is provided that substrate 101, and interlayer Jie is formed on lining 101 surface
Matter layer 103；Then, with reference to Fig. 2, described dielectric layer 103 is formed mask layer 105, described mask layer 105 is formed with interconnection
Line chart case；Followed by, with reference to Fig. 3, with described mask layer 105 as mask, etch described interlayer dielectric layer 103, form groove
104, and remove described mask layer 105；Then, with reference to Fig. 4, in groove 104 and the inter-level dielectric of groove 104 opening both sides
Deposited copper metal material 105 on layer 103；Finally, with reference to Fig. 5, described copper metal material is planarized by chemical mechanical milling tech
Material 105, to exposing interlayer dielectric layer 103, forms copper interconnecting line 106.
But, along with the continuous reduction of semiconductor technology node, the interconnection line in semiconductor device is more and more intensive, interconnection
The critical size (CD, critical dimension) of line is more and more less, when forming interconnection line by existing technique, is formed recessed
Groove and in groove the technology difficulty of filler metal material higher, the inside of formed interconnection line is easily generated cavity, form relatively
Difference.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of semiconductor device, to form live width in back-end process
Less, density is higher and spaced interconnection line or connector, reduces the technology difficulty forming semiconductor device, improves institute's shape
Become the form of semiconductor device, and then improve the performance of formed semiconductor device.
For solving the problems referred to above, inventor provide the forming method of a kind of semiconductor device, including: substrate is provided；?
Some discrete the first metal layers are formed on substrate；The sidewall of the first metal layer is performed etching, makes the width of the first metal layer
Consistent with design width；Side wall is formed on the sidewall of the first metal layer after etching；Between discrete the first metal layer
Form the second metal level, described second metal level upper surface and the first metal layer upper surface flush on substrate, and have each other
Side wall is isolated；Remove described side wall or remove described the first metal layer and the second metal level.
Optionally, the material of described the first metal layer and the second metal level is titanium nitride or tantalum nitride.
Optionally, the material of described side wall is copper nitride, on the sidewall of the first metal layer after etching formed side wall it
After, also include: described side wall is carried out cured.
Optionally, the material of described side wall is silicon oxide, silicon nitride, silicon oxynitride or polysilicon.
Compared with prior art, technical solution of the present invention has the advantage that
First on substrate, form discrete the first metal layer, and the sidewall of the first metal layer both sides is performed etching, make the
The width of one metal level is consistent with design width, formation side wall on the sidewall of the first metal layer the most after etching, and the
Fill the second metal level making side wall on the first metal layer sidewall mutually isolated on substrate between one metal level, finally remove institute
State the first metal layer and the second metal level or remove described side wall, the interconnection that formation is spaced and density is bigger on substrate
Line or connector, simplify the processing step forming semiconductor device, reduce technology difficulty and manufacturing cost, and this technique
Easily it is accurately controlled, improves the performance of formed semiconductor device.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is the schematic diagram that existing technique forms interconnection line；
Fig. 6 is the schematic flow sheet of an embodiment of the forming method of semiconductor device of the present invention；
Fig. 7 to Figure 13 be the forming method of semiconductor device of the present invention an embodiment in form the showing of semiconductor device
It is intended to；
Figure 14 is the schematic flow sheet of another embodiment of the forming method of semiconductor device of the present invention；
Figure 15 to Figure 18 be the forming method of semiconductor device of the present invention another embodiment in formed semiconductor device
Schematic diagram.
Detailed description of the invention
Understandable, below in conjunction with the accompanying drawings to the present invention for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
Detailed description of the invention be described in detail.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention is all right
Using other to be different from alternate manner described here to implement, therefore the present invention is not limited by following public specific embodiment
System.
The most as described in the background section, along with the continuous reduction of semiconductor technology node, formed mutually by existing technique
During line, formed groove and in groove filler metal material formed interconnection line technology difficulty higher, formed interconnection line
To be easily generated cavity, form poor in inside.
For these reasons, the invention provides the forming method of a kind of semiconductor device, first formed discrete on substrate
The first metal layer, and the sidewall of the first metal layer both sides is performed etching, makes width and the design width one of the first metal layer
Cause, the sidewall of the first metal layer the most after etching is filled on formation side wall, and the substrate between the first metal layer and makes
The second metal level that on the first metal layer sidewall, side wall is mutually isolated, finally remove described the first metal layer and the second metal level or
Person removes described side wall, is formed and be spaced and interconnection line that density is bigger or connector on substrate.
The forming method of the semiconductor device that the present invention provides, in back-end process, utilizes self-alignment type double exposure light
Carving technology is formed in semiconductor device and is spaced and interconnection line that density is bigger or connector, simplifies processing step, reduces
Technology difficulty and manufacturing cost, and this technique is easily accurately controlled, and improves the performance of formed semiconductor device.
It is described in detail below in conjunction with the accompanying drawings.
With reference to Fig. 6, for the schematic flow sheet of an embodiment of the forming method of semiconductor device of the present invention, including:
Step S11, it is provided that substrate；
Step S12, forms some discrete the first metal layers over the substrate；
Step S13, performs etching the sidewall of the first metal layer, makes the width of the first metal layer and design width after etching
Unanimously；
Step S14, the sidewall of the first metal layer after etching is formed side wall；
Step S15, depositing second metal layer on substrate, side wall and the first metal layer；
Step S16, planarizes described second metal level, the first metal layer and side wall, make the first metal layer after planarization,
Side wall and the upper surface flush of the second metal level；
Step S17, removes the side wall after planarization.
Embodiment one
Fig. 7 to Figure 13 be semiconductor device of the present invention one embodiment of forming method in the schematic diagram of semiconductor device,
With reference to Fig. 7 to Figure 13, the forming method of semiconductor device of the present invention is illustrated.
With reference to Fig. 7, it is provided that substrate 201.
In the present embodiment, the material of described substrate 201 is advanced low-k materials (low k) or ultra-low dielectric constant material
(Ultra low k, ULK), such as black diamond, for by the interconnection line being subsequently formed or connector and substrate 201 lower front end
Device architecture (such as MOS transistor etc.) or the metal interconnecting wires of realization electrical connection that technique is formed are isolated, to reduce metal level
Between parasitic capacitance.Concrete, the method forming described substrate 201 can be chemical vapor deposition method.
With continued reference to Fig. 7, described substrate 201 forms some discrete the first metal layer 203a.
The material of described the first metal layer 203a is titanium nitride or tantalum nitride.The formation work of described the first metal layer 203a
Skill is chemical vapor deposition method or physical gas-phase deposition.In the present embodiment, the material of described the first metal layer 203a
For titanium nitride.
The width d of described the first metal layer 203a1Slightly larger than design width dc, described design width dcFor on the substrate 201
Form interconnection line or the live width of connector.
The step forming some discrete the first metal layer 203a on the substrate 201 is as follows:
On the substrate 201 by lower from be sequentially depositing the first metal material and photoresist layer (not shown)；
Pattern described photoresist layer, photoresist layer is formed some discrete openings, the width of described opening and
Spacing between one metal level 203a is corresponding；
With comprise opening photoresist layer as mask, etch described first metal material, form some the first discrete gold medals
Belong to layer 203a；
The photoresist layer of opening is comprised described in removal.
With reference to Fig. 8, the sidewall of the first metal layer 203a in Fig. 7 is performed etching, make the first metal layer 203b after etching
Width d2With design width dcUnanimously.
In the present embodiment, the solution performing etching the sidewall of the first metal layer 203a is hydrogen peroxide.
In the present embodiment, first pass through dry etch process and form width d in Fig. 71Slightly larger than design width dcThe first metal
Layer 203a, then by wet-etching technology, the width of the first metal layer 203a in Fig. 7 is finely adjusted, make the first gold medal after etching
Belong to the width d of layer 203b2With design width dcUnanimously, improve performance and the yield rate of formed semiconductor device.
It should be noted that design width d described in the present embodimentcRefer to discrete interconnection line or the connector desirably formed
Width.
With reference to Fig. 9, the first metal layer 203b after described substrate 201 and etching forms sacrificial material layer 205a.
The material of described sacrificial material layer 205a is silicon oxide, silicon nitride, silicon oxynitride or polysilicon.Described sacrifice material
Bed of material 205a can pass through ald (Atomic Layer Deposition, referred to as ALD) technique and be formed.The present embodiment
In, the material of described sacrificial material layer 205a is silicon nitride.
With reference to Figure 10, sacrificial material layer 205a described in etching Fig. 9, remove and be positioned at the first metal layer 203b and section substrate
Sacrificial material layer 205a on 201, forms side wall 205b on the sidewall of the first metal layer 203b.
Concrete, the method etching described sacrificial material layer 205a can be dry etching, such as plasma etching；It is alternatively
Wet etching, such as, when the material of described expendable material 205a is silicon nitride, can use hot phosphoric acid solution to described sacrifice material
Material 205a performs etching, and when the material of described expendable material 205a is silicon oxide, hydrofluoric acid solution can be used described sacrifice
Material 205a performs etching, but the invention is not restricted to this.
Concrete, described side wall 205b width in the horizontal direction is by the spacing between follow-up interconnection line or connector certainly
Fixed.
With reference to Figure 11, depositing second metal layer 207a on substrate 201, side wall 205b and the first metal layer 203b.
Concrete, the material of described second metal level 207a is titanium nitride or tantalum nitride.Described second metal level 207a
Forming method be chemical vapor deposition method or physical gas-phase deposition.In the present embodiment, described second metal level
The material of 207a is titanium nitride.
With reference to Figure 12, the second metal level 207a, the first metal layer 203b and side wall 205b described in planarization Figure 11, make to put down
The first metal layer 203c, side wall 205c after smoothization and the upper surface flush of the second metal level 207b.
In the present embodiment, planarize described second metal level 207a, the method for the first metal layer 203b and side wall 205b is
Chemical mechanical milling tech, its concrete technology is known to the skilled person, and does not repeats at this.
With reference to Figure 13, remove described side wall 205c, be positioned at the second metal level 207b and the first metal layer 203c on substrate 201
Constitute discrete interconnection line or connector.
In the present embodiment, the method removing described side wall 205c is wet etching, and the solution of described wet etching is hot phosphorus
Acid solution.
Technical scheme in the present embodiment, first forms discrete the first metal layer on substrate and is positioned at the first metal layer sidewall
On side wall, then on side wall, substrate and the first metal layer, form the second metal level, and planarize described second metal level,
One metal level and side wall, make the first metal layer after planarization, side wall and the upper surface flush of the second metal level, finally remove flat
Side wall after smoothization, is formed on substrate and is spaced and interconnection line that density is bigger or connector, simplify formation semiconductor device
In part, interconnection line or the technology difficulty of connector, reduce process costs；Further, since interconnection line or connector pass through in the present embodiment
On substrate, first deposit metal material metal material is performed etching formation again, formed interconnection line in semiconductor device or slotting
Plug is not likely to produce cavity, improves the performance of formed semiconductor device.
With reference to Figure 14, for the schematic flow sheet of another embodiment of the forming method of semiconductor device of the present invention, bag
Include:
Step S21, it is provided that substrate；
Step S22, forms some discrete the first metal layers over the substrate；
Step S23, performs etching the sidewall of the first metal layer, makes the width of the first metal layer and design width after etching
Unanimously；
Step S24, the sidewall of the first metal layer after etching is formed side wall；
Step S25, carries out cured to described side wall；
Step S26, forms the second metal level on substrate, side wall and the first metal layer；
Step S27, planarizes described second metal level, side wall and the first metal layer, make the first metal layer after planarization,
Side wall and the upper surface flush of the second metal level；
Step S28, removes the first metal layer after planarization and the second metal level.
Embodiment two
Figure 15 to Figure 18 be semiconductor device of the present invention another embodiment of forming method in the signal of semiconductor device
Figure, illustrates the forming method of semiconductor device of the present invention with reference to Figure 15 to Figure 18.
With reference to Figure 15, it is provided that substrate 301, described substrate 301 is formed some discrete the first metal layer 303b and
It is positioned at the side wall 305b on described the first metal layer 303b sidewall.
In the present embodiment, the forming method of described the first metal layer 303b and side wall 305b and the first metal in embodiment one
203b is identical with side wall 205b for layer, does not repeats at this.
In the present embodiment, the material of described side wall 305b is copper nitride, and the material of described the first metal layer 303b is nitridation
Titanium.
Side wall 305b in Figure 15 is carried out cured, makes the material of side wall 305b by copper nitride also native copper.Concrete, institute
The temperature stating cured is that the process time is 10s～600s less than 400 degrees Celsius.
With reference to Figure 16, substrate 301, side wall 305b and the first metal layer 303b form the second metal level 307a.
Concrete, the material of described second metal level 307a is titanium nitride or tantalum nitride.Described second metal level 307a
Forming method be chemical vapor deposition method or physical gas-phase deposition.In the present embodiment, described second metal level
307a is identical with the material of the first metal layer 303b, it is possible to for titanium nitride or tantalum nitride.
With reference to Figure 17, the second metal level 307a, the first metal layer 303b and side wall 305b described in planarization Figure 16, make to put down
The first metal layer 303c, side wall 305c after smoothization and the upper surface flush of the second metal level 307b.
In the present embodiment, planarize described second metal level 307a, the method for the first metal layer 303b and side wall 305b is
Chemical mechanical milling tech, its concrete technology is known to the skilled person, and does not repeats at this.
With reference to Figure 18, removing the first metal layer 303c after planarization and the second metal level 307b, residue material is copper
Side wall 305c constitutes discrete interconnection line or connector.
In the present embodiment, the method removing the first metal layer 303c after planarization and the second metal level 307b is that wet method is carved
Erosion, the solution of described wet etching is hydrogen peroxide.
The above-mentioned second metal level 307a that is initially formed, then remove part the second metal level by chemical mechanical milling tech
307a, the first metal layer 303b and side wall 305b, make the side wall 305c surfacing after planarization, the after removing planarization
After one metal level 303c and the second metal level 307b, the copper interconnecting line or the copper plug surface that are formed are smooth, improve and are formed
The performance of semiconductor device.
In the present embodiment, first on substrate, form discrete the first metal layer and be positioned on the first metal layer sidewall nitridation
Copper side wall, then make copper nitride be reduced to copper by curing process, and on copper side wall, substrate and the first metal layer, form the second gold medal
Belong to layer and planarize described second metal level, copper side wall and the first metal layer, making the second metal level after planarization, the first gold medal
Belong to layer and the upper surface flush of copper side wall, finally remove the second metal level after planarization and the first metal layer, shape on substrate
Arrangement at interval and the bigger copper interconnecting line of density or copper connector, simplify technology difficulty, reduce manufacturing cost, and due to this work
Skill is easily accurately controlled, and then improves the performance of formed semiconductor device.
Although the present invention is open as above with preferred embodiment, but it is not for limiting the present invention, any this area
Technical staff without departing from the spirit and scope of the present invention, may be by the method for the disclosure above and technology contents to this
Bright technical scheme makes possible variation and amendment, therefore, every content without departing from technical solution of the present invention, according to the present invention
Technical spirit any simple modification, equivalent variations and modification that above example is made, belong to technical solution of the present invention
Protection domain.
Claims (7)
1. the forming method of a semiconductor device, it is characterised in that including:
Substrate is provided；
Using dry etch process to form some discrete the first metal layers on substrate, the width of described the first metal layer is more than
Design width, described design width is to form interconnection line or the live width of connector over the substrate；
Use wet-etching technology that the sidewall of the first metal layer is performed etching, make width and the design width one of the first metal layer
Cause；
Side wall is formed on the sidewall of the first metal layer after etching；
The second metal level, described second metal level upper surface and the first gold medal is formed on substrate between discrete the first metal layer
Belong to layer upper surface flush, and have side wall to isolate each other；
Removing described side wall, the material of described side wall is silicon oxide, silicon nitride, silicon oxynitride or polysilicon；
Or, remove described the first metal layer and the second metal level, the material of wherein said side wall is copper nitride.
2. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described the first metal layer and the second gold medal
The material belonging to layer is titanium nitride or tantalum nitride.
3. the forming method of semiconductor device as claimed in claim 1, it is characterised in that remove described the first metal layer and the
Two metal level methods are wet etching.
4. the forming method of the semiconductor device as described in claim 1 or 3, it is characterised in that the solution of described wet etching
For hydrogen peroxide.
5. the forming method of semiconductor device as claimed in claim 4, it is characterised in that the first metal layer after etching
After forming side wall on sidewall, also include: described side wall is carried out cured.
6. the forming method of semiconductor device as claimed in claim 5, it is characterised in that the temperature of described cured is less than
400 degrees Celsius, the time is 10s～600s.
7. the forming method of semiconductor device as claimed in claim 1, it is characterised in that the material of described substrate is ultralow Jie
Permittivity material.
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| CN105575946A (en) | 2014-10-16 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
| CN106611699A (en) * | 2015-10-22 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | A dual composition method and a manufacturing method for a semiconductor device |
| CN107579001B (en) * | 2016-07-04 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN111584421B (en) * | 2019-02-15 | 2023-08-25 | 中芯国际集成电路制造(上海)有限公司 | Interconnection structure and forming method thereof |
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| CN1567564A (en) * | 2003-07-10 | 2005-01-19 | 南亚科技股份有限公司 | Method for making metallic interconnecting line |
| CN1933109A (en) * | 2005-09-14 | 2007-03-21 | 海力士半导体有限公司 | Method of forming micro patterns in semiconductor devices |
| CN102122651A (en) * | 2010-01-11 | 2011-07-13 | 海力士半导体有限公司 | Semiconductor device and method for manufacturing the same |
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| KR101200938B1 (en) * | 2005-09-30 | 2012-11-13 | 삼성전자주식회사 | Method for forming patterns of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1567564A (en) * | 2003-07-10 | 2005-01-19 | 南亚科技股份有限公司 | Method for making metallic interconnecting line |
| CN1933109A (en) * | 2005-09-14 | 2007-03-21 | 海力士半导体有限公司 | Method of forming micro patterns in semiconductor devices |
| CN102122651A (en) * | 2010-01-11 | 2011-07-13 | 海力士半导体有限公司 | Semiconductor device and method for manufacturing the same |
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