1291759 九、發明說明： 【發明所屬之技術領域】 一種電容的製作方法，尤指一種金屬-絕緣層-金屬電容 的製作方法。 【先前技術】 _ 在半導體製程中，利用金屬層、絕緣層、金屬層 (metal_insulator-metal，MIM)複合式結構所構成的金屬電容 器已廣泛地運用於極大型積體電路(ultra large scale integration，ULSI)的設計上。因為此種金屬電容器具有較低 的電阻值（resistance)以及較小的寄生電容(parasitic capacitance)，而且沒有空乏區感應電壓（induced voltage)偏 移的問題，因此目前多採用MIM構造做為金屬電容器的主 •要結構。 請參考第1圖及第2圖，第1圖及第2圖為習知於一半 導體晶片10上製作一金屬電容器26的方法示意圖。如第 1圖所示，半導體晶片10表面包含有一基底11，以及一介 電層12設於基底11之上。習知方法是先於半導體晶片10 上之介電層12表面形成一鋁等金屬層所構成之金屬下電 1291759 極(bottomplate)14圖案。接著於金屬下電極η表面依序沈 精一絕緣層以及另一紹金屬層，並利用黃光(lithography) 及蝕刻製程定義金屬上電極18的圖案，以將多餘的金屬 層、絕緣層加以去除，形成内金屬絕緣層（inter-metar insulator，IMI)16以及金屬上電極18，完成金屬電容器26 的製作。 如第2圖所示，接著於該金屬電容器26上覆蓋一平坦 化之内金屬介電層（inter-metal dielectric，IMD}20。隨後再 於内金屬介電層20表面塗佈（coating): —光阻層(未顧示）， 並利用一黃光製程來定義接觸洞(via h〇le)28 去除多餘部份之光阻層，並以殘餘之光阻層為罩幕進行一 乾姓刻製程，向下蝕刻未被罩幕覆蓋部份之内金屬介電層 20 ’形成接觸洞28。最後剝除(strip)殘餘之光阻層。 然後以機鍍(sputtering)方式將接觸洞28内填入鎢等金 屬層（未顯示），再利用一回蝕刻或化學機械研磨㈣⑽丨㈣ mechanical polishing，CMP)製程將填滿於接觸洞28内之金 屬層約略切齊至内金屬介電層2〇表面，以形成接觸插塞 22。接著再於内金屬介電層2〇表面均勻沈積_金屬層（未 顯示），並利用一蝕刻製程，以於接觸插塞22頂部表面形 1291759 成金屬導線24。接觸插塞22主要用來電連接金屬導線24 與金屬電容器26。 隨著積體電路的積集度(integration)增加以及高性能的 需求’低電阻之多重金屬内連interconnects) 的製作便逐漸成為許多半導體積體電路製程所必須採用的 方式。而銅雙鑲嵌(dual damascene)技術搭配低介電常數材 二斤構成的*屬間介電層(inter metal dielectric，IMD)是目 3 =文歡迎的金屬内連線製程組合，尤其外 gh speed)邏輯積體電路晶片製造以及〇.18微来以吓 的深次微米（d 連綠技、eep SUb-micr〇)半導體製穋，銅金屬雙鑲散内 下一世^蒙積體〒路製程中已日益重要’而且勢必將成為 鋼制妒 導體製程的標準内連線技術。因此，如何整合 扪表％以應用_目 v 器# e 4 ;具有低電阻之金屬内速線以及MIM電容 疋目月U研究的重點方向。 【發明内容】 园此本發明之± ^ ^ (MIM)電容的制 的在於提供一金屬—絕緣層·金 屬結構作枝，以彻銅雙鑲嵌技術所構成 能。眷習知金屬電容與導線間之金屬效應與整 1291759 根據本發明之申請專利範圍所揭露之MIM電容的製作 方法，其係先提供一基底，且該基底上覆蓋有一介電層。 隨後於該介電層中形成至少一雙鑲嵌開口以及至少一電容 開口。其次形成一第一導電層，覆蓋於該介電層表面以及 該電容開口之側壁與底部並填滿該雙鑲嵌開口。然後於該 第一導電層表面形成一絕緣層，接著形成一第二導電層於 該絕緣層表面，並填滿該電容開口。最後進行一平坦化製 ❿程，去除於該介電層表面之該第二導電層、該絕緣層與該 第一導電層，以於該電容開口中形成一電容並於該雙鑲嵌 開口中形成一雙鑲嵌導體。 由於本發明係提供一利用鋼雙鑲嵌技術來形成金屬· 絕緣層-金屬（MIM)電容之製作方法，因此可有效降低電容 與金屬導線之間的接觸電卩且(contact resistance)與整合問 •題，並大幅簡化製程，提昇產品運作效能。 【實施方式】 請參考第3圖至第7圖。第3圖至第7圖為形成本發 明之金屬-絕緣層-金屬（MIM)電容的製作方法示意圖。 如第3圖所示，首先提供一半導體晶片30，且半導體 1291759 晶片30表面包含有一基底31，以及一介電層33覆蓋於基 底31之上。其中，基底31與介電層3 3中另包含有一以雙 鑲傲（ dual damascene )製程所製備之金廣連接層34，用以 電連接後續形成之電容與雙鑲嵌導體與半導體晶片30上 之其他元件。隨後於介電層36中形成至少一雙鑲嵌（ dual damascene)開口 40以及至少一電容開口 38。值得注意的 是，雙鑲嵌開口 40及電容開口 38可利用一般傳統製作雙 修鑲嵌之方法，如同習知該項技藝者所熟知，典型的雙鑲嵌 技術包括有：⑴接觸窗優先(via-first)製程；(2)自行對準 (self_aligned)製程；以及（3)溝渠優先(trench-first)製程。例 如，先形成一圖案化第一光阻層（未顯.示）於介電層36上並 定義一雙鑲嵌結構之上層溝槽圖案以及雙鑲嵌開口圖案， 接著利用一非等向性蝕刻製輕蝕刻一溝槽41與部分之雙 鑲嵌開口 4〇於介電層36中。然後形成一圖案化第二光阻 鲁層(未顯示)於溝槽41上並於溝槽41中定義一開孔42，最 後赖刻開孔42直至金屬連接層34表面。除此之外，雙鑲 嵌開口 40又可利用一第一光阻層（未顯示）於介電層36上 定義並蝕刻一開孔42，然後利用一第二光阻層（未顯示）於 介電層36上定義一溝糟41，並蝕刻溝槽41至介電層36 中與蝕刻開孔42至金屬連接層34表面，而不侷限於上述 之方法。 1291759 如第4圖所示，其次形成-第-導電層I覆蓋於介 電層36表面以及電免叫， 復盍於；1 」 38之側壁與底部並填滿雙鑲彼 計，覆蓋_口38之第％ «之顧電容之下電極板，且覆蓋電容_ 弟一導電層44南度係低於介電層36之高度。 依據本發明之最佳實施例’第—導電魏 層（未顯示)，覆蓋於介電層％表面、電容開口?对 底部與雙鑲«口 4〇,以防止銅金屬層之銅離子向外遷移 (migration)而擴散至介電層36内。其中广 (Ta)、氮化钽(tantalum，TaN)、鈦(Ti)、或氮化鈦(TiN)等不 同組合所組成。隨後形成一晶種層（未顧示)並覆蓋於該阻 障層上，用以附著銅金屬層之銅離子於介電層 該阻障層與晶種層皆可利用北學氣相沈積 最後再電鍍一銅金屬層並覆蓋於介電層36表面以及電容 開口 38之侧壁與底部並填滿雙鑲嵌開口 4〇。 然後如第5周所示，於第一導電層44表面形成一絕緣 層45，接著再形成一第二導電層46於絕緣層45表面，並 填滿電容開〇 38。其中，絕緣層45係甩來當作本發明mim 12 1291759 電容之電容介電層，其可為氧化/氮化/氧化 (oxide-nitride_oxide，ΟΝΟ)、氧化鋁(ai2〇3)、氧化叙 (Ta2〇5)、或氧化铪(Hf〇2)介電層等之絕緣物，而覆蓋於絕 緣層45表面並填滿電容開口 38之第士導電層46則係為本 發明MIM電容之上電極板。此外，本發明之 於銅製程之整合，在不同產品規格或其他因素的考量，第 一導電層44與第二導電層46亦可選用其 鲁或鋁銅合金所組成之導電材料。 . .. . . ... ... . _ .. . . .... 如第6圖所示’最後進行一平坦化製程，去除於介電 層36表面之第二導電層46、絕緣層45與第一導電層44 , 以於電容開口 38中形成一電容39並於雙鑲嵌開口 4〇中形 成一雙鑲嵌導體47。其中該平坦化製轾係為一化學機械| 磨(CMP)製程。最後如第7圖所示，在電容39與雙镶嵌導 之上電極板與雙鑲嵌導體47電連接至丰導體晶片中各層 間之雙鑲嵌導體48 ’以藉由雙鑲嵌導體48與與晶片中各 層間之不同元件與導線相連接，構戍完整之多重金屬内連 線0 1291759 有別於習知製作一金屬電容器之製作方法，本發明係 提供一利用整合式銅雙鑲散技衡來同時形成金屬内連線以 及金屬-絕緣層_金屬（MIM)電容之製作方法，以有效降低電 容與金屬導線之間的無觸電阻，並大幅簡化製程。此外， 由於銅金屬具有較鋁金屬低約40%的電阻率，而低介電常 數材料又可降低金屬導線之間的電容效應，因此總體說 來，本發明更可以有效降低電子訊號傳遞時所產生& RC 鲁延遲(RC delay) ’並大幅增加產品運作效能 以上所述僅為本發明之較佳實施例，凡依本發明申請 in 〇1291759 IX. Description of the invention: [Technical field to which the invention pertains] A method of fabricating a capacitor, especially a metal-insulating layer-metal capacitor. [Prior Art] _ In the semiconductor process, a metal capacitor composed of a metal layer, an insulating layer, and a metal-insulator-metal (MIM) composite structure has been widely used for ultra large scale integration (ultra large scale integration, ULSI) is designed. Because such metal capacitors have lower resistance and less parasitic capacitance, and there is no problem of induced voltage shift in the depletion region, MIM structures are currently used as metal capacitors. The main structure. Referring to Figures 1 and 2, Figs. 1 and 2 are schematic views showing a method of fabricating a metal capacitor 26 on a half conductor wafer 10. As shown in Fig. 1, the surface of the semiconductor wafer 10 includes a substrate 11 and a dielectric layer 12 is disposed over the substrate 11. The conventional method is to form a bottom plate 14 pattern of a metal formed by forming a metal layer such as aluminum on the surface of the dielectric layer 12 on the semiconductor wafer 10. Then, an insulating layer and another metal layer are sequentially deposited on the surface of the metal lower electrode η, and the pattern of the metal upper electrode 18 is defined by a lithography and etching process to remove excess metal layer and insulating layer. An inter-meta insulator (IMI) 16 and a metal upper electrode 18 are formed to complete the fabrication of the metal capacitor 26. As shown in FIG. 2, the metal capacitor 26 is then covered with a planarized inter-metal dielectric (IMD) 20. Subsequently, the surface of the inner metal dielectric layer 20 is coated: - a photoresist layer (not shown), and uses a yellow light process to define a contact hole (via h〇le) 28 to remove excess portion of the photoresist layer, and to use the residual photoresist layer as a mask for a dry name The process etches down the inner metal dielectric layer 20' which is not covered by the mask to form the contact hole 28. Finally, the residual photoresist layer is stripped. Then the contact hole 28 is filled in by sputtering. Into a metal layer such as tungsten (not shown), and then using an etching or chemical mechanical polishing (4) (10) 四 (4) mechanical polishing, CMP) process will fill the metal layer in the contact hole 28 approximately tangentially to the inner metal dielectric layer 2〇 The surface is formed to form a contact plug 22. Then, a metal layer (not shown) is uniformly deposited on the surface of the inner metal dielectric layer 2, and an etching process is used to form a metal wire 24 on the top surface of the contact plug 22. The contact plug 22 is mainly used to electrically connect the metal wire 24 and the metal capacitor 26. With the increase in the integration of integrated circuits and the need for high performance, the fabrication of low-resistance multi-metal interconnects has become a must for many semiconductor integrated circuit processes. The dual damascene technology combined with the low dielectric constant material consisting of two kilograms of intermetallic dielectric (IMD) is the metal interconnecting process combination of the 3rd text, especially the outer gh speed Logic integrated circuit chip fabrication and 〇.18 micro to scare the deep micron (d green technology, eep SUb-micr〇) semiconductor system, copper metal double inlays in the next generation ^ 积 〒 〒 〒 制It has become increasingly important and will inevitably become the standard interconnect technology for steel tantalum conductor processes. Therefore, how to integrate the 扪 table% to apply _目 v器# e 4 ; the metal internal speed line with low resistance and the MIM capacitor focus on the U research. SUMMARY OF THE INVENTION The ± ^ ^ (MIM) capacitor of the present invention is constructed by providing a metal-insulating layer and a metal structure as a branch, and is constructed by a copper double damascene technique. The metal effect between the metal capacitor and the wire and the method of fabricating the MIM capacitor disclosed in the patent application of the present invention is to provide a substrate, and the substrate is covered with a dielectric layer. At least one dual damascene opening and at least one capacitive opening are then formed in the dielectric layer. A first conductive layer is formed to cover the surface of the dielectric layer and the sidewalls and bottom of the capacitor opening and fill the dual damascene opening. Then forming an insulating layer on the surface of the first conductive layer, and then forming a second conductive layer on the surface of the insulating layer and filling the capacitor opening. Finally, a planarization process is performed to remove the second conductive layer, the insulating layer and the first conductive layer on the surface of the dielectric layer to form a capacitor in the capacitor opening and form in the dual damascene opening. A pair of mosaic conductors. Since the present invention provides a method for fabricating a metal-insulator-metal (MIM) capacitor using a steel dual damascene technique, the contact between the capacitor and the metal wire can be effectively reduced and contact resistance and integration are required. Problem, and greatly simplify the process, improve product performance. [Embodiment] Please refer to Figures 3 to 7. 3 to 7 are schematic views showing a method of fabricating the metal-insulator-metal (MIM) capacitor of the present invention. As shown in Fig. 3, a semiconductor wafer 30 is first provided, and the surface of the semiconductor 1291759 wafer 30 includes a substrate 31, and a dielectric layer 33 overlies the substrate 31. The substrate 31 and the dielectric layer 33 further comprise a gold-gap connection layer 34 prepared by a dual damascene process for electrically connecting the subsequently formed capacitor and the dual damascene conductor to the semiconductor wafer 30. Other components. At least one dual damascene opening 40 and at least one capacitive opening 38 are then formed in the dielectric layer 36. It should be noted that the dual damascene opening 40 and the capacitor opening 38 can utilize the conventional conventional method of double repairing, as is well known to those skilled in the art. Typical dual damascene techniques include: (1) contact-first (via-first) Process; (2) self-aligned process; and (3) trench-first process. For example, a patterned first photoresist layer (not shown) is formed on the dielectric layer 36 and defines a double damascene structure upper trench pattern and a dual damascene opening pattern, followed by an anisotropic etching process. A trench 41 and a portion of the dual damascene opening 4 are lightly etched into the dielectric layer 36. A patterned second photoresist layer (not shown) is then formed over the trench 41 and defines an opening 42 in the trench 41, and finally the opening 42 is formed to the surface of the metal tie layer 34. In addition, the dual damascene opening 40 can define and etch an opening 42 on the dielectric layer 36 by using a first photoresist layer (not shown), and then utilize a second photoresist layer (not shown). A trench 41 is defined on the electrical layer 36, and the trench 41 is etched into the dielectric layer 36 and the etched opening 42 to the surface of the metal connection layer 34 is not limited to the above method. 1291759, as shown in FIG. 4, the second formation-first conductive layer I covers the surface of the dielectric layer 36 and is electrically free of charge, and is entangled in the side wall and the bottom of the 1" 38 and filled with double inlays, covering _ mouth The first part of 38 «the lower electrode of the capacitor, and the cover capacitance _ the first conductive layer 44 is lower than the height of the dielectric layer 36. According to a preferred embodiment of the present invention, the first conductive conductive layer (not shown) covers the surface of the dielectric layer, the opening of the capacitor, and the bottom and the double-layered opening 4 to prevent the copper ions of the copper metal layer from outward. Migrating and diffusing into the dielectric layer 36. Among them, Ta (Ta), Tantalum (TaN), Titanium (Ti), or Titanium Nitride (TiN) are composed of different combinations. Subsequently, a seed layer (not shown) is formed and overlaid on the barrier layer for attaching copper ions to the copper metal layer to the dielectric layer. The barrier layer and the seed layer can be deposited by using the northern vapor deposition layer. A layer of copper metal is then electroplated and overlying the surface of the dielectric layer 36 and the sidewalls and bottom of the capacitor opening 38 and filling the dual damascene opening 4〇. Then, as shown in the fifth week, an insulating layer 45 is formed on the surface of the first conductive layer 44, and then a second conductive layer 46 is formed on the surface of the insulating layer 45, and the capacitor opening 38 is filled. The insulating layer 45 is used as a capacitor dielectric layer of the mim 12 1291759 capacitor of the present invention, which may be oxide-nitride_oxide (氧化铝), alumina (ai2〇3), and oxidized ( An insulator of Ta2〇5), or a hafnium oxide (Hf〇2) dielectric layer, and the conductive layer 46 covering the surface of the insulating layer 45 and filling the capacitor opening 38 is the upper electrode of the MIM capacitor of the present invention. board. In addition, in the integration of the copper process of the present invention, the first conductive layer 44 and the second conductive layer 46 may also be made of a conductive material composed of a ruthenium or an aluminum-copper alloy, depending on various product specifications or other factors. . . . . . . . . . . . . . . . . . . . . . . . As shown in Fig. 6 'finalizing a planarization process, removing the second conductive layer 46 on the surface of the dielectric layer 36, insulating The layer 45 and the first conductive layer 44 form a capacitor 39 in the capacitor opening 38 and form a dual damascene conductor 47 in the dual damascene opening 4A. Wherein the planarization system is a chemical mechanical | grinding (CMP) process. Finally, as shown in FIG. 7, the capacitor 39 and the dual damascene upper electrode plate and the dual damascene conductor 47 are electrically connected to the dual damascene conductor 48' between the layers in the conductor wafer to be used in the dual damascene conductor 48 and the wafer. The different components between the layers are connected to the wires, and the complete multi-metal interconnects 0 1291759 is different from the conventional method for fabricating a metal capacitor. The present invention provides an integrated copper double-insert balance to simultaneously A metal interconnect and a metal-insulator-metal (MIM) capacitor are formed to effectively reduce the contactless resistance between the capacitor and the metal conductor, and greatly simplify the process. In addition, since the copper metal has a resistivity lower than that of the aluminum metal by about 40%, and the low dielectric constant material can reduce the capacitance effect between the metal wires, the present invention can effectively reduce the electronic signal transmission. Producing & RC delay ' and greatly increasing product operating efficiency. The above is only a preferred embodiment of the present invention, and is applied for in accordance with the present invention.
14 1291759 【圖式簡單說明】 第1圖及第2圖為習知製作一金屬電容器的方法示意圖。 第3圖至第7圖為形成本發明之金屬-絕緣層V金屬電容的 製作方法示意圖。 主要元件符號說明14 1291759 [Simple description of the drawings] Figs. 1 and 2 are schematic views showing a method of fabricating a metal capacitor. 3 to 7 are schematic views showing a method of fabricating the metal-insulator V metal capacitor of the present invention. Main component symbol description
10半導體晶片 12介電層 16金屬絕緣層 20内金屬介電層 24金屬導線 28接鱗洞 31基底 34金屬連接層 38電容開口 41溝槽 42開孔 45絕緣層 47雙鑲嵌導體 11基底 14 金屬下電極 18 金屬上電極 22 接觸揷塞 26 金孱電容器 30 半導體晶片 33介電層 36介電層 40 雙鑲嵌開口 39 電容 44 第一導電層 46 第二導電層 48 雙鑲嵌導體 1510 semiconductor wafer 12 dielectric layer 16 metal insulating layer 20 metal dielectric layer 24 metal wire 28 squama hole 31 substrate 34 metal connection layer 38 capacitor opening 41 trench 42 opening 45 insulating layer 47 dual damascene conductor 11 substrate 14 metal Lower electrode 18 metal upper electrode 22 contact plug 26 gold germanium capacitor 30 semiconductor wafer 33 dielectric layer 36 dielectric layer 40 dual damascene opening 39 capacitor 44 first conductive layer 46 second conductive layer 48 dual damascene conductor 15