JPH11274428A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow application to analog/digital mixed type for improved yield and lower cost, with a capacity element mounted. SOLUTION: On a silicon substrate 1, a lower part electrode 13 is formed. Further an inter-layer insulating film 4 comprising an hole 5 and a dielectrics film 6 are sequentially deposited, after that, a connection hole 7 and a wiring groove are opened at the same time and a tungsten film is deposited. Then, the tungsten film is polished by CMP(chemical mechanical polish) method with the dielectrics film as a polishing stopper, an upper part electrode 15, a connection plug 9, a wiring 8, etc., are formed at the same time, while these are metal- wired.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device equipped with a capacitive element, and more particularly to a mixed analog / digital semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a capacitive element, a manufacturing process in which upper and lower electrodes are formed of polysilicon has been adopted. However, recently, CODEC (Coder-d
An analog circuit and a digital circuit are mixed in a semiconductor device used for mobile communication, digital broadcasting equipment, and the like using an (ecoder) circuit, and a high-precision, stable voltage characteristic without voltage dependency is required for the analog circuit configuration. There is a need for a capacitive element having the same.

In order to eliminate the dependency on the applied voltage of the capacitive element and improve the capacitance accuracy, a semiconductor device having a two-layer structure of polysilicon and metal silicide as a lower electrode and a process device using an aluminum wiring as an upper electrode has also been proposed. Have been. Also, when forming an analog circuit and a digital circuit in the same semiconductor chip, high-precision capacitive elements are not required in the semiconductor device manufacturing process without increasing the number of processes, and the yield and reliability are high, and the cost is low. One of the important issues is whether or not it can be built in.

There is also a demand to reduce the occupied area of the capacitive element as much as possible while securing the capacitance required for high integration of the element.

[0005]

However, the CMO
In the S process, when a conventional technique is applied to a mixed analog / digital type semiconductor device as it is to form a capacitive element, the following problem occurs. The problem will be described with reference to FIGS. 1 and 2 both show an example in which a capacitor and a buried plug are formed in a connection hole on the same semiconductor chip.

FIG. 1 shows that a lower electrode 3 is formed on a silicon substrate 1 with a silicon oxide film 2 interposed therebetween, and a BPSG (Boro) is formed.
An interlayer insulating film 4 made of a PhosphoSilicate Glass film is formed by atmospheric pressure CVD (Chemical V).
apor Deposition method,
An opening 5 is formed in a portion where a capacitor is to be formed in the interlayer insulating film, and a capacitor insulating film 6 made of a silicon nitride film is deposited by a plasma CVD method. Then, the connection hole 7
And an aluminum film 8 is simultaneously deposited by sputtering as an upper electrode as a capacitive element and a plug buried in the connection hole 7. At this time, when the aspect ratio of the connection hole 7 is large (3 to 4 or more), cavities are formed, the electric resistance is increased, or the wire may be disconnected, and an unexpected obstacle may be caused.

FIG. 2 shows an example in which tungsten is deposited by metal CVD using tungsten instead of aluminum as the plug material to be buried in the connection hole 7 and formed by etch back. Metal CVD of tungsten
Since the embedding property is excellent when deposited by the method, even when the aspect ratio is large, the cavity as shown in FIG. 1 does not occur in the embedded plug 9 of the connection hole 7.

However, in a capacitive element region having a large-area opening 5, an etching residue 10 is formed on the side wall of the opening 5 by etch-back. Since the etching residue 10 is easily peeled off and has conductivity, if it re-adheres to a semiconductor device during a manufacturing process, it may cause a defect such as a short circuit between wirings. In addition, peeling of the etching residue 10 causes contamination inside the semiconductor manufacturing apparatus, and significantly reduces the semiconductor device manufacturing yield. In the case of an analog / digital hybrid type semiconductor device, the number of manufacturing steps tends to increase inevitably by, for example, forming a capacitive element. However, in order to reduce manufacturing costs, the number of steps must be reduced as much as possible. In general, a large area is required, but from the viewpoint of improving the degree of integration, it is also an important issue to manufacture a large-capacity capacitive element with a smaller occupied area.

[0009]

In order to achieve the above object, the present invention relates to a semiconductor device having a capacitor, wherein a lower electrode of the capacitor is formed of a conductive film formed on a semiconductor substrate; An interlayer insulating film having an opening hole thereon,
A semiconductor device comprising: a dielectric film covering a bottom surface and a side wall of the opening; and a conductor filling the opening as an upper electrode of the capacitor, wherein the conductor and another element are connected by metal wiring. To provide.

According to the present invention, in a method of manufacturing a semiconductor device, a first step of forming a lower electrode of a capacitor made of a first conductive film on a semiconductor substrate, and an interlayer insulating film is deposited on the lower electrode. A second step, a third step of forming an opening in the interlayer insulating film so as to expose the lower electrode, and a step of forming a dielectric film on the semiconductor substrate so as to cover the bottom and side walls of the opening. A fourth step of depositing; a fifth step of depositing a second conductive film to fill the opening hole;
And a sixth step of forming an upper electrode by polishing the conductive film using the dielectric film as a stopper.

Further, the above-mentioned problem is solved by adding a seventh step of removing the dielectric film on the surface of the semiconductor substrate after the sixth step. The present invention further provides a method of manufacturing a semiconductor device, comprising: forming a top electrode by polishing the second conductive film in a sixth step using the interlayer insulating film as a stopper; and removing the dielectric film. This problem is solved by having an eighth step of performing the seventh step simultaneously with the seventh step.

Further, the present invention is intended to reduce the manufacturing cost.
In order to reduce the number of steps, a connection plug made of a conductor connecting upper and lower wirings via an interlayer insulating film and / or a wiring groove is formed in the interlayer insulating film and formed by embedding a conductor in the wiring groove. The wiring is formed by the same step as the step of forming the upper electrode of the capacitive element according to claim 2.

After this dielectric film is formed, it can be used as a hard mask in the subsequent steps. Furthermore, in order to reduce the manufacturing cost, the present invention uses the dielectric film formed as a capacitor insulating film also as an etching stopper film to form a self-aligned plug hole in a specific portion of a wiring groove formed in an interlayer insulating film. It is characterized by forming.

The present invention also provides a semiconductor device according to claim 1, wherein a conductor is buried in an interlayer insulating film for a multilayer wiring as a lower electrode. In view of the improvement in the degree of integration, the present invention provides a semiconductor device having a large-capacitance element by repeatedly applying the capacitance element according to claim 3 to a semiconductor device using multilayer wiring and increasing the area of the opposing electrode. It is.

[0015]

Embodiments of the present invention will be described with reference to the drawings. FIGS. 3 to 9 are cross-sectional views showing a series of manufacturing steps of a first embodiment according to the present invention, mainly focusing on the formation of a capacitor element of a semiconductor device. It is formed. [1] A silicon oxide film 2 having a thickness of 300 to 500 μm is deposited as a device isolation film on a silicon substrate 1 by thermal oxidation. [2] A polysilicon film 11 having a thickness of 150 to 200 nm is deposited on the surface of the silicon oxide film 2 by a low pressure CVD method. [3] A polysilicon film is patterned by ordinary photolithography and dry etching in accordance with the shape and size of a capacitor to be formed later. [4] A titanium film having a thickness of 20 to 40 nm is deposited by a sputtering method, and rapidly heated by lamp annealing at a temperature of 650 to 800 ° C. to form a titanium silicide film 12.
To form [5] An unnecessary portion of the titanium film is selectively etched to form a polysilicon film 11 and a titanium silicide film 12 of the capacitor.
The lower electrode 13 having a two-layer structure is formed (FIG. 3). [6] A BPSG film having a thickness of 1 to 2 μm is deposited as an interlayer insulating film (1) 4 by a normal pressure CVD method, and 800 to 900 ° C.
The reflow process is performed at the temperature of. [7] CMP (Chemical Mechanical)
lPolish) method and the BPS on the lower electrode 13
The BPSG film is polished until the G film thickness becomes 0.8 to 1.5 μm, and is further planarized. [8] An opening 5 is formed in the BPSG film in a region where a capacitor is to be formed by ordinary photolithography and dry etching. [9] A silicon nitride film is formed as a dielectric film having a thickness of 60 to 100 nm by a low pressure CVD method. It is deposited to form the capacitance insulating film 6 (FIG. 4). [10] A connection hole 7 is formed in the interlayer insulating film (1) 4 by ordinary photolithography and dry etching (FIG. 5). [11] A tungsten film 14 is deposited by a metal CVD method. The film thickness is not less than the opening hole depth, that is, the above BPSG
The thickness is not less than the film thickness. Here, the thickness is set to 0.8 to 1.5 μm or more (FIG. 6). [12] Polish tungsten film by CMP method,
Polishing is performed until the silicon nitride film on the SG film is exposed. Since the silicon nitride film has a function as a stopper when polishing the tungsten film, controllability of the polishing amount is secured without excessive polishing. In this way, the embedded plug 9 and the upper electrode 15 of the capacitor are formed in a self-aligned manner (FIG. 7). [13] A portion of the silicon nitride film exposed on an unnecessary surface is removed by dry etching (FIG. 8).

When the unnecessary portion of the silicon nitride film is removed, the silicon nitride film required for forming the capacitor is not removed because it is buried between the silicon nitride film and the upper electrode 15. That is, since unnecessary portions are etched and removed in a self-aligned manner, a mask for selectively etching the silicon nitride film is unnecessary, and therefore, a photolithography process accompanying the mask can be omitted.

Further, by removing the portion exposed on the surface of the silicon nitride film, the upper electrode 15 and the like have a shape protruding from the interlayer insulating film (1) 4, so that the protruding portion is used as a target in the subsequent photolithography. This can help to improve the alignment accuracy. In the step of polishing the tungsten film by the CMP method, the silicon nitride film on the BPSG film may be continuously polished and removed after the tungsten film is polished and removed. In this case, a dry etching step for removing an unnecessary silicon nitride film can be omitted.

When polishing is performed using the interlayer insulating film below the dielectric film as a stopper, the step of forming the upper electrode of the capacitor and the step of removing the dielectric film can be performed simultaneously, which is advantageous in terms of manufacturing cost. become. However, in this case, since the protruding portion is not formed, alignment using the target as a target cannot be performed. [1
4] A semiconductor circuit is formed by connecting the upper electrode 15 and the buried plug 9 with aluminum wiring (FIG. 9).

The semiconductor device of the present invention is completed through the above steps. In this embodiment, the lower electrode of the capacitive element has a two-layer structure of a polysilicon film and a titanium silicide film. Other metals that react with silicon to form metal silicide may be deposited and formed of metal silicide or simply a metal film. In the present embodiment, in the step of polishing the tungsten film 14 of [12] by the CMP method, BPSG as the interlayer insulating film (1) 4 is used.
Although the stopper is used for polishing the silicon nitride film on the film, when the BPSG film is used as a stopper, the silicon nitride film exposed on the surface, which is a subsequent step, can be removed at the same time, thereby reducing the manufacturing cost. be able to.

Further, a silicon oxide film formed by thermal oxidation, an BPSG film as an interlayer insulating film, and a silicon nitride film as a capacitive element insulating film are used as an element isolation film. BPSG
A silicon oxide film deposited by a low-pressure CVD method as a film and an interlayer insulating film, and another dielectric insulating material (for example, tantalum pentoxide, a silicon oxide film) may be used as a capacitive element insulating film.

FIGS. 10 to 18 show a second embodiment according to the present invention. In addition to the formation of the capacitive element and the like described with reference to FIGS. This is an embodiment in which wiring for electrically connecting each element such as a capacitive element is expanded to a buried wiring.
It is formed by sequentially performing the following manufacturing steps. Note that this manufacturing process is partially common to the first embodiment, so that the description thereof will be omitted. The steps [1] to [9] of the first embodiment are common to this embodiment (FIGS. 10 to 10).
It is omitted because it is up to FIG. 12). Therefore, the following [1]
0]. However, in this embodiment, since the gate electrode of the MOS transistor is also formed, a sidewall 16 is formed around the lower electrode 13 at the same time. [10] A wiring groove 18 for embedding a metal wiring is formed by ordinary photolithography (resist pattern (1) 17) and dry etching (FIG. 13). [11]
Resist pattern (2) 19 for forming connection holes
Is formed (FIG. 14). [12] Further, a connection hole 20 for connecting the upper and lower wirings is formed by dry etching. At this time, other connection holes and the like other than those shown in FIG. At this time, the difference between the etching rates of the silicon nitride film and the BPSG film (the etching rate of the silicon nitride film is about 1/20 of that of the BPSG film) causes the silicon nitride film itself to act as a mask, and the BPSG film is self-aligned. Connection holes are drilled (FIG. 15). [13] After removing the resist film, a titanium nitride film (40 to 60 nm in thickness) is deposited as the barrier metal 21. [14] A tungsten film 14 is deposited by a metal CVD method. The film thickness is not less than the opening hole depth, that is, the above BPSG
The thickness is not less than the film thickness. Here, the thickness is 0.8 to 1.5 μm or more (FIG. 16). [15] The tungsten film is polished by a CMP method using a dual damascene process until the silicon nitride film on the BPSG film is exposed. Since this silicon nitride film has a function as a stopper when polishing the tungsten film similarly to the first embodiment, controllability of the polishing amount is secured without excessive polishing. In this manner, the embedded wiring (tungsten) 22, the embedded plug 23 for connection, and the upper electrode 15 of the capacitor are formed in a self-aligned manner. In addition, since the wiring for connecting the upper electrode 15 and the like is also formed by this polishing process, a semiconductor circuit is formed at this time (FIG. 17). [16] A portion of the silicon nitride film exposed on an unnecessary surface is removed by dry etching (FIG. 18).

At this time, unnecessary portions are removed by etching in a self-aligned manner, and a mask for selectively etching the silicon nitride film is not required. Therefore, the photolithography step accompanying this can be omitted. Same as the example. FIG. 19 shows a metal film (for example, aluminum, copper, gold, silver, platinum or an alloy containing these as a main component) in which a lower electrode is embedded in an interlayer insulating film (2) 24 of a multilayer wiring as a third embodiment. May be configured. At this time, a circuit is formed by appropriately connecting the buried wiring 22. FIG. 20 shows a fourth embodiment in which the second and third embodiments are repeatedly applied to a multi-layer wiring forming process to increase the electrode area of the opposing capacitance element to form a large-capacity capacitance element. It is. In FIG. 20, the upper electrode 1 of the capacitive element
5. An intermediate electrode 25 is provided between metal films as the lower electrode 13 to increase the size of the capacitive element. It goes without saying that a circuit is formed using the buried wiring 22 as these electric wirings. In this way, the upper electrode and the lower electrode of the capacitor can be formed simultaneously with the connection plugs connecting the upper and lower wirings and other wirings, and an arbitrary capacitor can be formed by alternately connecting each wiring layer as an electrode. And the degree of freedom in element design can be expanded.

[0023]

As described above, according to the present invention, the CM
In an analog / digital hybrid semiconductor device in an OS process and a method of manufacturing the same, a highly accurate capacitive element having no voltage dependency can be manufactured. In addition, since the capacitive element insulating film and the interlayer insulating film thereunder can be used as a stopper film for CMP polishing, and unnecessary portions of the capacitive element insulating film can be removed in a self-aligned manner, so that the photolithography process for these can be omitted. In addition, since the capacitor element electrode, the connection plug, and other wirings can be formed at the same time, it can contribute to cost reduction. Further, the present invention provides a highly reliable semiconductor device and a method for manufacturing the same, which prevents a conventional semiconductor device having a high aspect ratio from being buried in a connection hole having a high aspect ratio and a yield reduction due to a short circuit between wirings due to an etching residue such as tungsten.

[Brief description of the drawings]

FIG. 1 is a semiconductor device mainly showing a capacitor element portion manufactured by applying a conventional manufacturing process.

FIG. 2 is another semiconductor device mainly showing a capacitor element portion manufactured by applying a conventional manufacturing process.

FIG. 3 is a cross-sectional view in which a lower electrode is formed on an element isolation film in a manufacturing process according to a first embodiment of the present invention.

FIG. 4 is a cross-sectional view in which an opening is formed in an interlayer insulating film and a capacitor element insulating film is deposited in a manufacturing process of the first embodiment according to the present invention.

FIG. 5 is a cross-sectional view in which connection holes are formed in the manufacturing process of the first embodiment according to the present invention.

FIG. 6 is a cross-sectional view in which a tungsten film is deposited in the manufacturing process of the first embodiment according to the present invention.

FIG. 7 is a cross-sectional view in which a connection plug 9, an upper electrode 15, and the like are formed by polishing a tungsten film in a manufacturing process according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view in which a capacitive element insulating film on a surface is removed in a manufacturing process according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view in which an upper electrode, a buried plug, and the like are connected by aluminum wiring in the manufacturing process of the first embodiment according to the present invention.

FIG. 10 is a cross-sectional view in which a lower electrode is formed on an element isolation film in a manufacturing process according to a second embodiment of the present invention.

FIG. 11 is a cross-sectional view in which an opening is formed in an interlayer insulating film in a manufacturing process according to a second embodiment of the present invention.

FIG. 12 is a cross-sectional view in which a capacitor insulating film is deposited in a manufacturing process according to a second embodiment of the present invention.

FIG. 13 is a cross-sectional view in which wiring grooves are formed in a manufacturing process according to a second embodiment of the present invention.

FIG. 14 is a sectional view in which a resist pattern for forming a connection hole is formed in a manufacturing process of a second embodiment according to the present invention.

FIG. 15 is a cross-sectional view in which connection holes are formed in a manufacturing process according to a second embodiment of the present invention.

FIG. 16 is a cross-sectional view in which a barrier metal is deposited and a tungsten film is further deposited in a manufacturing process according to a second embodiment of the present invention.

FIG. 17 illustrates a process of manufacturing a second embodiment according to the present invention, in which a tungsten film is polished to form a buried wiring 22 and a connection plug 2;
3 is a cross-sectional view after an upper electrode 15 and the like have been formed and wiring has been formed on them.

FIG. 18 is a cross-sectional view in which a capacitive element insulating film on a surface is removed in a manufacturing process according to a second embodiment of the present invention.

FIG. 19 is a cross-sectional view of a third embodiment according to the present invention, particularly using a buried metal film of a multilayer wiring as a lower electrode.

FIG. 20 is a cross-sectional view of a fourth embodiment according to the present invention, in which a large-capacity capacitive element is formed by repeatedly performing the capacitive element forming method of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Silicon oxide film 3 Lower electrode 4 Interlayer insulating film (1) 5 Opening hole 6 Capacitive insulating film 7 Connection hole 8 Aluminum wiring 9 Embedded plug 10 Etching residue 11 Polysilicon film 12 Titanium silicide film 13 Lower electrode 14 Tungsten film Reference Signs List 15 upper electrode 16 sidewall 17 resist pattern (1) 18 wiring groove 19 resist pattern (2) 20 connection hole 21 barrier metal 22 buried wiring 23 buried plug 24 interlayer insulating film (2) 25 intermediate electrode

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/822

Claims (8)

[Claims] 1. A semiconductor device having a capacitor, a lower electrode of the capacitor formed of a conductive film formed on a semiconductor substrate, an interlayer insulating film having an opening on the lower electrode,
A semiconductor device comprising: a dielectric film that covers a bottom surface and a side wall of the opening; and a conductor that fills the opening as an upper electrode of the capacitor, and the conductor and another element are connected by metal wiring. 2. A first step of forming a lower electrode of a capacitor made of a first conductive film on a semiconductor substrate, a second step of depositing an interlayer insulating film on the lower electrode, and A third step of forming an opening in the film so as to expose the lower electrode, a fourth step of depositing a dielectric film on the semiconductor substrate so as to cover the bottom and side walls of the opening, A fifth step of depositing a second conductive film to fill the opening; and a sixth step of forming an upper electrode by polishing the second conductive film using the dielectric film as a stopper. A method for manufacturing a semiconductor device. 3. A method of manufacturing a semiconductor device, comprising: after the sixth step of claim 2, a seventh step of removing the dielectric film on the surface of the semiconductor substrate. 4. The method according to claim 2, wherein the second step is performed in a sixth step.
A method of manufacturing a semiconductor device, comprising: forming an upper electrode by polishing the conductive film using the interlayer insulating film as a stopper to form an upper electrode; and simultaneously performing a seventh step of removing the dielectric film. . 5. A wiring formed by forming a wiring groove in a connection plug made of a conductor for connecting upper and lower wirings via an interlayer insulating film and / or a wiring groove in the interlayer insulating film and embedding a conductor in the wiring groove. 3. A method for manufacturing a semiconductor device, comprising: forming a capacitor element at the same time as forming the upper electrode of the capacitor element. 6. A method for manufacturing a semiconductor device, wherein the dielectric according to claim 2 is used as a hard mask in the steps after the fourth step of claim 2. 7. The semiconductor device according to claim 1, wherein a conductor is embedded in an interlayer insulating film for a multilayer wiring as a lower electrode. 8. A semiconductor device having a large-capacitance element by repeatedly applying the capacitance element according to claim 3 to a semiconductor device using multilayer wiring and increasing the area of the opposing electrode.