JP4740071B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4740071B2
JP4740071B2 JP2006236810A JP2006236810A JP4740071B2 JP 4740071 B2 JP4740071 B2 JP 4740071B2 JP 2006236810 A JP2006236810 A JP 2006236810A JP 2006236810 A JP2006236810 A JP 2006236810A JP 4740071 B2 JP4740071 B2 JP 4740071B2
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formed
film
wiring
plug
copper
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JP2008060415A (en
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明広 梶田
勇人 那須
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東芝マイクロエレクトロニクス株式会社
株式会社東芝
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Priority to JP2006236810A priority Critical patent/JP4740071B2/en
Priority claimed from US11/848,978 external-priority patent/US20080054466A1/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a wiring conductor such as a wiring and a plug.

  In recent semiconductor devices having a fine wiring structure, different conductive materials are sometimes used as main components for wiring, plugs, and the like in order to meet various demands such as speeding up and miniaturization.

  However, in such a semiconductor device, when low resistance copper is used as the wiring material, the copper in the wiring easily diffuses into a different material other than copper used for the plug, such as tungsten, Reliability may be deteriorated.

  On the other hand, a conventional technique is known in which a copper diffusion barrier film such as a TaN film or a Ta film is formed between a copper wiring and a plug to prevent copper diffusion from the copper wiring to the plug (for example, Patent Documents). 1).

However, in the diffusion barrier film according to this prior art, when miniaturization proceeds and further thinning is required, the continuity of the film cannot be maintained, and copper diffusion prevention cannot be sufficiently prevented, There is a risk of reducing the reliability of the semiconductor device.
JP 2004-207281 (FIG. 6)

  The present invention has been made to solve the above-described problems, and effectively prevents copper from being diffused between wiring conductors such as plugs and wirings using different materials other than copper and copper as main components. Thus, an object is to provide a semiconductor device with improved reliability.

In order to achieve the above object, a semiconductor device according to one embodiment of the present invention includes a first wiring conductor, a conductive cobalt-containing cap film formed over the first wiring conductor, and the first wiring conductor. A second wiring conductor formed on the one wiring conductor via the cap film, and only one of the first and second wiring conductors is mainly composed of copper, and The first wiring conductor has a concave portion on its surface, and a nitrogen-containing metal (M) silicide film containing at least the metal (M) on the surface of the first wiring conductor is formed on the inner wall surface of the concave portion. is a semiconductor device, characterized in that said cap layer is formed so as not to fill completely the concave portion.

  According to the present invention, a semiconductor device with improved reliability by effectively preventing copper diffusion between a wiring conductor such as a plug and a wiring each using copper and a different material other than copper as a main component. Can be provided.

  A semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described below with reference to the drawings.

  In the semiconductor device according to this embodiment, an interlayer insulating layer composed of a silicon oxide film or the like is laminated on a semiconductor substrate such as a silicon substrate, and a wiring conductor such as a plug or a wiring is provided in each interlayer insulating layer. Is formed based on a predetermined design, and has a multilayer wiring structure in which upper and lower wirings are electrically connected by plugs.

  In this embodiment, in order to reduce the resistance of the semiconductor device, copper or copper alloy having a low electrical resistivity is used as the wiring material. On the other hand, a conductive material different from copper is used as the plug material, and in this embodiment, tungsten, which has excellent step coverage characteristics as compared with aluminum and the like and has a good filling characteristic in fine holes having a high aspect ratio, is used as a main component. As described above, the semiconductor device according to the present embodiment includes the copper wiring and the tungsten plug using different materials other than copper and copper as the main components. However, the plug may be added with a small amount of copper as an impurity. .

  First, the configuration of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view illustrating a configuration of a main part of the semiconductor device according to the present embodiment.

  As shown in FIG. 1A, in the semiconductor device according to this embodiment, a tungsten plug 101a (first electrode) disposed in a predetermined design position on a predetermined interlayer insulating layer 100 (first interlayer insulating layer 100). The wiring conductor 101) penetrates vertically. In this embodiment, the plug diameter is about 30 nm to about 100 nm, and the aspect ratio (plug depth / plug diameter) represented by the ratio of the plug diameter to the plug depth is about 5.

On the side surface of the plug 101a, a thin antioxidant film 102 made of TiN, Ti, TaN, Ta or the like having a film thickness of about 3 nm to 10 nm is formed, and this antioxidant film 102 leads to the surface of the tungsten plug 101a. It is possible to prevent exposure to oxidizing gas or intrusion of moisture. The antioxidant film 102 also has an effect of suppressing diffusion of tungsten from the tungsten plug 101a to the interlayer insulating layer 100 adjacent to the plug 101a.

A cap film 103 is formed on the plug 101a in order to prevent diffusion of impurity components mainly from the upper surface of the plug 101a into the plug 101a. The cap film 103 is a refractory metal having a thin film thickness of about 5 nm containing cobalt formed by an electroless plating method. For example, a cobalt compound obtained by adding a metal component such as tungsten to cobalt, that is, CoWB, It is a thin film of CoWP, CoWBP, CoBP, CoB, CoP or the like.

An upper interlayer insulating layer 104 (second interlayer insulating layer 104) is formed on the first interlayer insulating layer 100, and a copper wiring 105a (second wiring conductor) is formed in the second interlayer insulating layer 104. 105) is formed. The copper wiring 105a is formed on the plug 101a through the cap film 103, and is electrically connected to the lower wiring (not shown) through the plug 101a.

The cobalt-containing cap film 103 formed by the electroless plating method in the semiconductor device according to the present embodiment will be described in detail later, but TiN formed by a sputtering method (PVD method: Physical Vapor Deposition) or the like, Compared to a general diffusion barrier film made of Ti, TaN, Ta or the like, the film quality can be continuously and uniformly formed, and the film thickness can be reduced to about 10 nm or less. Is possible. Thus, by reducing the film thickness of the cap film 103 formed between the wiring 105a and the plug 101a and making the film quality uniform, the electrical resistance between the wiring 105a and the plug 101a is reduced, and the wiring 105a. From the copper to the plug 101a can be prevented.

Further, the cap film 103 in this embodiment is compared with a thin diffusion barrier film such as TiN, Ti, TaN, and Ta formed by using a CVD method (Chemical Vapor Deposition) or an ALD method (Atomic Layer Deposition). However, since the adhesiveness with the copper wiring 105a is excellent, the diffusion of copper from the copper wiring 105a into the plug 101a can be effectively prevented.

Furthermore, in this embodiment, the MnSiO film 106 is formed in a self-aligned manner at the interface between the copper wiring 105a and the first and second interlayer insulating layers 100 and 104 adjacent to each other on the side and bottom surfaces of the copper wiring 105a. The MnSiO film 106 is a thin diffusion barrier film 106 having a thickness of about 2 nm to 4 nm for preventing copper from diffusing from the copper wiring 105a to the first and second interlayer insulating layers 100 and 104. Compared with diffusion barrier films such as TiN, Ti, TaN, and Ta used as diffusion barrier films, the adhesion to copper is high, and the film quality is uniform and stable. In addition, it is possible to effectively avoid exposure of oxidizing gas to the wiring surface or intrusion of moisture.

  Next, with reference to FIG. 2, a method of manufacturing plugs and wirings formed in the interlayer insulating layer of the semiconductor device according to this embodiment as described above will be described. FIG. 2 is a process cross-sectional view illustrating the manufacturing method of the main part of the semiconductor device according to the present embodiment.

First, as shown in FIG. 2A, an interlayer insulating layer such as a silicon oxide film is laminated on a semiconductor substrate (not shown) such as single crystal silicon by a CVD method or the like, and then a predetermined interlayer is formed by photolithography. A resist film (not shown) is formed on the insulating layer 100 (first interlayer insulating layer 100), and an opening for plug formation is formed in the resist film. Further, by RIE (Reactive Ion Etching), the first interlayer insulating layer 100 is removed by etching using the resist film as a mask, and a hole 107 for forming a plug in the first interlayer insulating layer 100 is formed. The hole has a hole diameter of, for example, about 50 nm to 120 nm, and an aspect ratio (hole depth / hole diameter) of, for example, about 5. Although not shown here, the hole 107 is formed at a predetermined design position on the lower wiring.

  Next, as shown in FIG. 2B, an anti-oxidation film 102 such as TiN or TaN is formed on the first interlayer insulating layer 100 and on the inner wall of the hole 107 for plug formation by sputtering, Further, a conductive plug material such as tungsten is buried in the plug forming hole 107 by using CVD, ALD, or sputtering. Subsequently, the plug material and the barrier film material formed outside the hole 107 for forming the plug are polished and removed in order by CMP (Chemical Mechanical Polishing), and the plug 101a (first film) is formed inside the first interlayer insulating layer 100. A wiring conductor 101) and an antioxidant film 102 are formed.

  Next, as shown in FIG. 2C, a cap film 103 containing cobalt for preventing diffusion of impurities into the plug 101a on the plug 101a by using an electroless plating method, for example, CoWP, CoBP, or the like. Are formed in a self-aligning manner. Here, a specific method for forming the cap film 103 will be described below.

First, the surface of the first interlayer insulating layer 100 where the plug 101a is exposed is immersed in an aqueous solution of palladium chloride containing a metal element having a lower ionization tendency than tungsten, for example, palladium, so that tungsten atoms on the surface of the plug 101a become palladium atoms. A palladium plating layer is formed in a self-aligned manner only on the surface of the tungsten plug 101a. This palladium plating layer functions as a catalyst active layer, and the process of forming the substitution metal plating layer on the surface of the plug 101a in this way is the activation process of the surface of the plug 101a.

Further, after the surface of the plug 101a is activated, a cap film containing cobalt as a constituent component in the catalytically active layer forming portion on the surface of the plug 101a by an electroless plating method using a plating solution containing a cobalt chloride aqueous solution or the like. 103 is formed in a self-aligning manner.

At this time, the catalytic active layer is not formed on the surface of the first interlayer insulating layer 100 that does not contain the metal to be replaced, and the catalytic active layer is formed only on the surface of the plug 101a. It is formed only on 101a. Usually, when a conductive cap film is formed on a plug by using a sputtering method or a CVD method, the cap film on the insulating layer is removed by, for example, photolithography and RIE after the film formation to form a gap between the plugs. Although it is necessary to insulate, since the cap film 103 according to the present embodiment is selectively formed only on the plug 101a, it is possible to reduce the cap film removing process and simplify the manufacturing process.

The cap film 103 can also be formed by other electroless plating methods. That is, after the plug 101a is formed, the surface of the plug 101a is oxidized by using a chemical solution that reacts with an acid chemical solution, for example, a tungsten oxide such as citric acid, hydrochloric acid, or dilute sulfuric acid, and does not damage tungsten. After activating the surface of the plug 101a by removing substances, etc., a sulfuric acid-based cobalt (Co) chemical solution containing boron or phosphorus at a temperature of about 50 ° C. to 150 ° C. is applied on the surface of the tungsten plug 101a under a nitrogen forming gas. Supply.

At this time, for example, when boron (B) is used as a catalyst, the boron oxide becomes B 3+ by giving trivalent electrons to tungsten (W), and the surface of the plug 101a is negative by electrons given by boron. Charge accumulates. Co 2+ in the sulfuric acid chemical solution is attracted and accumulated on the surface of the plug 101a, and a cobalt film 103 (cap film 103) is formed on the surface of the plug 101a. On the other hand, since boron cannot give electrons to the insulating layer 100, the cobalt film 103 is not formed on the insulating layer 100, and the film can be selectively formed only on the surface of the plug 101a.

After forming the high melting point cap film 103 containing cobalt in this way, the surface is washed with an acid chemical solution (sulfuric acid, hydrofluoric acid, phosphoric acid, hydrochloric acid, etc.) at a temperature of about room temperature, Removal of the plating solution residue and stabilization of the cobalt-containing cap film 103 surface are achieved.

Next, as shown in FIG. 2D, an interlayer insulating layer 104 (second interlayer insulating layer 104) such as a silicon oxide film is stacked on the first interlayer insulating layer 100 and the plug 101a by a CVD method or the like. After that, the wiring groove 108 is formed at a predetermined position of the second interlayer insulating layer 104 by photolithography and RIE as in the hole 107 forming step. Here, the wiring trench 108 is formed so as to expose the cap film 103 on the plug 101a.

Next, as shown in FIG. 2E, a CuMn alloy layer 109 is formed on the second interlayer insulating layer 104 and on the inner wall of the wiring groove 108. Here, the CuMn alloy layer 109 functions as a seed layer for electrolytic plating described later, and is formed to a thickness of 5 to 20 nm by, for example, a sputtering method. The Mn content in the CuMn alloy layer 109 is about 0.05 to 20 at%. Subsequently, heat treatment is performed at 200 ° C. to 400 ° C. for about 5 minutes to 60 minutes to deposit Mn of the CuMn alloy layer 109 at the interface between the CuMn alloy layer 109 and the first and second interlayer insulating layers 100 and 104. Then, a MnSiO film that is a copper diffusion barrier film is formed in a self-aligning manner. That is, an extremely stable oxide film is formed at the interface with the first and second interlayer insulating layers 100 and 104.

Here, since Mn in the CuMn alloy layer 109 is diffused to the vicinity of the interface with the first and second interlayer insulating layers 100 and 104 by the heat treatment, the first and second interlayers of the CuMn alloy layer 109 are diffused. The portion on the opposite side of the interface with the insulating layers 100 and 104 is a CuMn alloy layer 109 or a Cu layer with a low Mn content. Further, the portion of the CuMn alloy layer 109 located on the cap film 103 is changed into a Cu film as a whole by Mn diffusing near the insulating layers 100 and 104 by heat treatment.

However, in FIG. 2E, illustration of the MnSiO film formed at the interface between the first and second interlayer insulating layers 100 and 104 of the wiring trench 108, the Cu film on the cap film 103, etc. is omitted and summarized. A CuMn alloy layer 109 is shown.

Next, as shown in FIG. 2 (f), copper 105 a is embedded in the second interlayer insulating layer 104 and in the wiring groove 108 by electroplating or the like, and then the copper on the second interlayer insulating layer 104 is formed. 105a and the CuMn alloy layer 109 are removed by polishing. At this time, since the CuMn alloy layer 109 formed on the cap film 103 is changed to a Cu film by the heat treatment, Mn does not intervene between the tungsten plug 101a and the buried copper wiring 105a, and the thin film Only the cap film 103 is interposed. Accordingly, the formation of the CuMn alloy layer 109 can avoid the risk of an increase in electrical resistance between the plug 101a and the wiring 105a.

On the other hand, since a copper diffusion barrier film 106 (MnSiO film 106) is formed in a self-aligned manner at the interface between the copper wiring 105a and the first and second interlayer insulating layers 100 and 104, the copper wiring 105a Copper diffusion into the first and second interlayer insulating layers 100, 104 is prevented.

Through the above steps, the semiconductor device according to this embodiment can be manufactured. In the semiconductor device according to the present embodiment, a thin cobalt-containing cap film 103 having high adhesion to copper is formed in a self-aligned manner between the copper wiring 105a and the plug 101a. A thin, stable MnSiO film 106 is formed between the interlayer insulating layers 100 and 104 in a self-aligning manner. Therefore, according to the semiconductor device of this embodiment, the first and second interlayer insulating layers 100 adjacent to the plug 101a and the wiring 105a from the copper wiring 105a are kept low while the resistance value between the copper wiring 105a and the plug 101a is kept low. , 104 can be sufficiently prevented from diffusing, and its reliability can be improved.

In this embodiment, in the step shown in FIGS. 2E and 2F, after heating the CuMn alloy layer 109 formed inside the wiring groove 108 and the like, copper 105a is embedded in the wiring groove 108 and formed. However, after the CuMn alloy layer 109 and the copper 105a are formed in the wiring groove 108, the semiconductor device may be subjected to heat treatment.

Even in such a manufacturing process, it is possible to manufacture a semiconductor device having the same structure as described above, and the tungsten plug 101a and the copper wiring 105a are formed through the thin film cap film 103 having high adhesion to copper. Since it is electrically connected, an increase in the resistance value between the copper wiring 105a and the plug 101a is suppressed, and at the same time, the copper to the first and second interlayer insulating layers 100 and 104 adjacent to the plug 101a and the wiring 105a is suppressed. Can be effectively prevented.

In the semiconductor device according to the present embodiment, tungsten having a good embedding characteristic is used as the plug material. However, other metal materials than copper, such as aluminum and cobalt, may be used. When cobalt is used as the plug material, tungsten or the like is added to the cap film 103 in order to improve the adhesion of the cap film 103.

Further, although a compound film of Mn, Si, and O is used for the diffusion barrier film 106 formed at the interface between the copper wiring 105a and the first and second interlayer insulating layers 100, 104, other metal elements, Si, O Alternatively, a compound film of Mn or other metal element and O may be used. That is, for example, oxides such as Nb, Zr, Cr, V, Y, Tc, and Re are easy to form, are highly wettable with an interlayer insulating layer such as a silicon oxide film, and exist stably at the insulating layer interface. A metal element that easily precipitates or forms a compound rather than being dissolved in copper and a compound of Si and O can be used as the diffusion barrier film.

In the semiconductor device according to the present embodiment, the cap film 103 is formed on the plug 101a and the wiring is further formed on the cap film 103. However, as shown in FIG. A cobalt-containing cap film 103 similar to the above is formed on one wiring conductor 101) by an electroless plating method, and a tungsten plug 105b (second wiring conductor 105) is embedded on the cap film 103. Even in this case, the diffusion of copper from the copper wiring 101b to the tungsten plug 105b can be effectively prevented by the cap film 103. In such a structure, since the cap film 103 is formed in a self-aligned manner on the entire upper surface of the copper wiring 101b, the interlayer insulating layer 104 (second interlayer insulating layer) located above the copper wiring 101b is formed. Copper diffusion into the layer 104) can also be prevented at the same time.

The configuration of the semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a cross-sectional view showing a main part of the semiconductor device according to the second embodiment of the present invention.

The semiconductor device according to the present embodiment is the semiconductor device according to the first embodiment in that the plug surface portion has a recess and the nitrogen-containing metal silicide film is formed on the inner wall (side portion and bottom) surface of the recess. And different. Therefore, hereinafter, in the description of the semiconductor device according to the present embodiment, the same reference numerals are given to the same parts as those of the configuration and the manufacturing method of the semiconductor device according to the first embodiment, and detailed description thereof is omitted.

Similar to the semiconductor device according to the first embodiment, the semiconductor device according to the present embodiment has a multilayer wiring structure in which a tungsten plug and a copper wiring are respectively formed in an interlayer insulating layer stacked on a semiconductor substrate.

As shown in FIG. 3, the cap film 103 containing cobalt shown in Example 1 is formed on the tungsten plug 101a by the electroless plating method, and the copper wiring 105a is further formed on the cap film 103. Yes. An anti-oxidation film 102 such as TiN or TaN is formed between the tungsten plug 101a and a predetermined interlayer insulating layer 100 (first interlayer insulating layer 100), and a copper wiring 105a and an interlayer insulating layer 104 (second interlayer insulating layer) are formed. A stable diffusion barrier film 106 such as a MnSiO film is formed between the layers 104).

In this embodiment, the plug diameter is about 30 nm to 100 nm, and the aspect ratio is about 5 or more. As described above, when the diameter of the plug formed in the semiconductor device is reduced and the aspect ratio is increased, a void or a seam (recess 110) may be generated on the surface of the embedded plug 101a as shown in FIG. is there.

The recess 110, which is a fine gap on the surface of the plug 101a, is difficult to completely cover with the cap film 103 in the step of forming the cap film 103 on the plug 101a by the electroless plating method described later. When the CuMn alloy layer 109 is formed on the 101a or the copper wiring 105a is embedded, the CuMn alloy layer 109 or the copper wiring 105a may be embedded to the inside of the recess 110 such as a void or a seam. In such a case, copper may diffuse into the plug 101a from the CuMn alloy layer 109 or the copper wiring 105a that has entered the recess 110 on the surface of the plug 101a.

On the other hand, in the semiconductor device according to the present embodiment, in order to prevent copper from diffusing from the recess 110 on the surface of the plug 101a into the plug 101a, nitrogen-containing tungsten containing tungsten as a metal component on the surface of the plug 101a. A silicide film 111 (nitrogen-containing metal silicide film 111) is formed on the inner wall surface of the recess 110 of the plug 101a.

The nitrogen-containing tungsten silicide film 111 is a thin film obtained by nitriding the tungsten component on the surface of the plug 101a by nitriding, and exposing the inner wall surface of the recess 110 of the plug 101a to a reactive gas containing silicon, for example, silane gas. Further, the thin film is formed by performing plasma treatment on the inner wall surface of the recess 110 using a reactive gas containing nitrogen, for example, ammonia gas. The nitrogen-containing tungsten silicide film 111 can be easily formed even in a very narrow gap inside a void or seam, and is a thin film having good film quality.

Therefore, by forming the nitrogen-containing tungsten silicide film 111 on the surface of the recess 110 that is not covered with the cap film 103, the entire surface of the plug 101 a including the recess 110 can be reliably covered with the cap film 103 and the nitrogen-containing tungsten silicide film 111. Therefore, it is possible to effectively prevent copper diffusion from the copper wiring 105a into the plug 101a.

Next, with reference to FIGS. 4A and 4B, a method for manufacturing plugs and wirings formed in the interlayer insulating layer of the semiconductor device according to this embodiment as described above will be described. FIG. 4 is a process cross-sectional view illustrating the manufacturing method of the main part of the semiconductor device according to the present embodiment.

First, as shown in FIG. 4A, a hole 107 for forming a plug 101a is formed in a predetermined interlayer insulating layer 100 (first interlayer insulating layer 100) by photolithography and RIE. The hole 107 has a hole diameter of about 50 nm to 150 nm and an aspect ratio of about 5 or more.

Next, as shown in FIG. 4B, an anti-oxidation film 102 such as a TiN film is formed on the first interlayer insulating layer 100 and inside the hole 107 by sputtering, and then tungsten is used as a plug material by electroplating. Is embedded in the first interlayer insulating layer 100 and in the hole 107.

At this time, it is very difficult to reliably fill the plug 101a material into the fine hole 107 having a high aspect ratio, and a recess 110 such as a void or a seam is formed in a part of the surface of tungsten. A part of the recess 110 is formed so that the bottom reaches the inside of the hole 107.

Next, a nitrogen-containing tungsten silicide film 111 is formed as a barrier film on the surface of the plug 101 a including the inner wall surface of the recess 110. Specifically, after the recess 110 is formed, first, the semiconductor device is held in a low-pressure chamber maintained at a constant high temperature atmosphere of about 200 ° C. to 400 ° C., and the exposed tungsten surface is exposed to silane gas to form tungsten. A silicide film is formed. Further, while maintaining a constant low-pressure state, ammonia gas is supplied, a high-frequency electric field is applied, ammonia plasma treatment is performed, and the tungsten silicide film on the tungsten surface including the inner wall of the recess 110 is nitrided in a self-aligned manner. A thin nitrogen-containing tungsten silicide film 111 is formed.

Next, as shown in FIG. 4C, the nitrogen-containing tungsten silicide film 111, tungsten, and the antioxidant film 102 on the first interlayer insulating layer 100 are polished and removed in order by CMP to obtain a first interlayer insulating layer. 100 is exposed.

Next, as shown in FIG. 4D, diffusion of impurities into the plug 101a on the plug 101a using the electroless plating method in the same manner as the step shown in FIG. 2C of the first embodiment. A cap film 103 containing cobalt, for example, CoWP, CoBP, or the like is formed in a self-aligned manner. At this time, the cap film 103 is not completely formed on the inner wall and the upper part of the recess 110 such as a void or a seam.

Next, as shown in FIG. 4E, after the interlayer insulating layer 104 (second interlayer insulating layer 104) is formed on the first interlayer insulating layer 100 and the cap film 103 by CVD or the like, A part of the second interlayer insulating layer 104 is processed by photolithography and RIE to form a wiring groove 108.

Further, a CuMn alloy layer 109 having a thickness of about 5 to 100 nm is formed in the wiring trench 108 and on the second interlayer insulating layer 104. Subsequently, heat treatment is performed to deposit Mn of the CuMn alloy layer 109 on the interface between the first and second interlayer insulating layers 100 and 104, and a MnSiO film (not shown in FIG. 4E) is formed on the interface. ) In a self-aligning manner. Similarly to Example 1, the CuMn alloy layer 109 located on the cap film 103 changes to a Cu film (not shown) as Mn diffuses to the vicinity of the insulating layer by heat treatment.

At this time, the CuMn alloy layer 109 may enter a part of the recess 110 on the surface of the plug 101a. However, since the nitrogen-containing tungsten silicide film 111 is formed on the inner wall surface of the recess 110, the CuMn alloy layer 109 enters the recess 110. Copper in the CuMn alloy layer 109 does not diffuse from the surface of the recess 110 of the plug 101a into the plug 101a.

  Next, as shown in FIG. 4 (f), copper 105a, which is a wiring material, is embedded and formed on the CuMn alloy layer 109 and in the wiring groove 108 by electroplating or the like, and further, the second interlayer is formed by CMP. The copper wiring 105a and the CuMn alloy layer 109 on the insulating layer 104 are polished and removed to expose the second interlayer insulating layer 104.

Even when the copper wiring 105a is buried, the copper wiring 105a may enter a part of the recess 110 on the surface of the plug 101a. However, since the nitrogen-containing tungsten silicide film 111 is formed on the inner wall surface of the recess 110. The copper that has entered the recess 110 does not diffuse from the surface of the recess 110 of the plug 101a into the plug 101a.

Through the above steps, the plugs and wirings of the semiconductor device according to this embodiment can be formed. According to the semiconductor device of this embodiment, even when the recesses 110 such as voids and seams are formed on the surface of the plug 101a, the cap film 103 and the plug 101a are formed on the plug 101a as a copper diffusion barrier film. Since the MnSiO film 106 is formed at the interface between the nitrogen-containing tungsten silicide film 111 and the copper wiring 105a and the first and second interlayer insulating layers 100 and 104 on the inner wall surface of the recess 110, the plug 101a or plug The copper can be sufficiently prevented from diffusing from the CuMn alloy layer 109 or the copper wiring 105a formed inside the recess 101a into the plug 101a and further to the insulating layers 100 and 104, and reliability can be ensured. .

(Modification of Example 2)
The configuration of the semiconductor device according to the modification of the second embodiment will be described below with reference to FIG. FIG. 5 shows a configuration of a main part of a semiconductor device according to a modification of the second embodiment.

The semiconductor device according to the modification of the second embodiment has substantially the same configuration as that of the semiconductor device according to the second embodiment. However, as shown in FIG. 5, in addition to the inner wall of the recess 110 on the surface of the plug 101a, the plug The difference is that a nitrogen-containing tungsten silicide film 111 is also formed on the upper surface of 101a, and further a cap film 103 is formed thereon.

Below, with reference to FIG. 6, the manufacturing method of this modification is demonstrated. FIG. 6 is a process cross-sectional view illustrating a method for manufacturing the main part of the semiconductor device according to this variation.

The manufacturing method of this modification is almost the same as the manufacturing method of the semiconductor device according to the second embodiment, but mainly differs in the process of forming the nitrogen-containing tungsten silicide film 111.

That is, as shown in FIG. 6A, after the hole 107 for forming the plug 101a is formed in the interlayer insulating layer (first interlayer insulating layer 100) stacked on the semiconductor substrate 100, it is shown in FIG. 6B. As described above, the anti-oxidation film 102 such as TiN and the tungsten 101a which is the material of the plug 101a are embedded by sputtering or the like. Here, a recess 110 is formed in the plug 101a.

Next, as shown in FIG. 6C, the tungsten 101 a and the antioxidant film 102 on the first interlayer insulating layer 100 are sequentially polished and removed by CMP to expose the first interlayer insulating layer 100. Further, after a silane gas is exposed to the surface of the plug 101a to form a tungsten silicide film, an ammonia gas is supplied to perform plasma treatment to form a thin film nitrogen-containing tungsten silicide film 111 in a self-aligned manner on the surface of the plug 101a. At this time, the nitrogen contained in the tungsten silicide film is reduced to a certain concentration or less by ammonia plasma treatment, so that the inner wall of the recess 110 of the plug 101a and the upper surface of the plug 101a are covered with the conductive nitrogen-containing copper silicide film 114. It becomes possible.

Subsequently, as shown in FIG. 6D, a cobalt-containing cap film 103 such as CoWP is formed on the nitrogen-containing tungsten silicide film 111 formed on the surface of the plug 101a by electroless plating.

Thereafter, as shown in FIG. 6E, as in Example 2, an upper interlayer insulating layer 104 (second interlayer insulating layer 104) is stacked and a wiring groove is formed in the second interlayer insulating layer 104. Thereafter, a diffusion barrier film 106 such as a MnSiO film is formed in a self-aligned manner at the interface of the insulating layer 104 in the wiring trench. Further, copper is embedded in the wiring groove 108 by electroplating or the like, and the copper and the diffusion barrier film 106 on the second interlayer insulating layer 104 are polished and removed by CMP, and the cap film 103 is interposed on the plug 101a. Copper wiring 105a is formed.

According to the semiconductor device according to this modification manufactured as described above, unlike the semiconductor device according to the second embodiment, since the nitrogen-containing tungsten silicide film 111 is also present under the cap film 103, the semiconductor device is formed on the cap film 103. Since the copper diffusion from the copper wiring 105a to the plug 101a can be prevented by the double diffusion barrier film of the cap film 103 and the nitrogen-containing tungsten silicide film 111, the diffusion preventing effect can be further enhanced.

Note that, in the semiconductor device according to the second embodiment and the present modification, as in the first embodiment, tungsten having a good embedding characteristic is used as the material of the plug 101a. However, for example, aluminum, cobalt, or the like is used. May be.

In the semiconductor device according to the present embodiment, a nitrogen-containing copper silicide film is formed on the upper surface of the copper wiring 105a by the same method as described above, and a cobalt-containing cap is further formed on the surface of the wiring 105a on which the nitrogen-containing copper silicide film is formed. It is also possible to form a film and then form a plug on the cobalt-containing cap film. In such a structure, since the nitrogen-containing copper silicide film and the cap film are formed in a self-aligned manner on the entire upper surface of the copper wiring 105a, copper diffusion from the copper wiring 105a to the interlayer insulating layer formed thereon is performed. Can be effectively prevented.

Sectional drawing which shows the structure of the principal part of the semiconductor device which concerns on Example 1 of this invention. Process sectional drawing which shows the manufacturing method of the principal part of the semiconductor device which concerns on Example 1 of this invention. Sectional drawing which shows the structure of the principal part of the semiconductor device which concerns on Example 2 of this invention. Process sectional drawing which shows the manufacturing method of the principal part of the semiconductor device which concerns on Example 2 of this invention. Sectional drawing which shows the structure of the principal part of the semiconductor device which concerns on the modification of Example 2 of this invention. Process sectional drawing which shows the manufacturing method of the principal part of the semiconductor device which concerns on the modification of Example 2 of this invention.

Explanation of symbols

100: first interlayer insulating layer
101: First wiring conductor
101a: Plug
101b: Wiring 102: Antioxidation film
103: Cap film
104: Second interlayer insulating layer
105: Second wiring conductor
105a: Wiring
105b: Plug
106: Barrier film
107: Hall
108: wiring trench 109: CuMn alloy layer 110: recess 111: nitrogen-containing metal silicide film

Claims (5)

  1. A first wiring conductor;
    A conductive cobalt-containing cap film formed on the first wiring conductor;
    A second wiring conductor formed on the first wiring conductor via the cap film;
    With
    Only one of the first and second wiring conductors is mainly composed of copper, the first wiring conductor has a recess on the surface, and at least the first wiring on the inner wall surface of the recess. A semiconductor device characterized in that a nitrogen-containing metal (M) silicide film containing metal (M) on the surface of a conductor is formed and the cap film is formed so as not to completely fill the recess. .
  2. The semiconductor device according to claim 1, wherein the recess is formed in a part of the surface of the first wiring conductor.
  3. The semiconductor device according to claim 2, wherein the first wiring conductor and the cap film are in contact with each other.
  4. It said first wiring conductors is a plug, said second wiring conductors semiconductor device of any one of claims 1 to 3, characterized in that a copper wire.
  5. The copper wiring is adjacent to an interlayer insulating layer through a film containing at least one metal element and O among Mn, Nb, Zr, Cr, V, Y, Tc, and Re. 4. The semiconductor device according to 4.
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US9997457B2 (en) * 2013-12-20 2018-06-12 Intel Corporation Cobalt based interconnects and methods of fabrication thereof

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JP2000058544A (en) * 1998-08-04 2000-02-25 Matsushita Electron Corp Semiconductor device and manufacture of the same
JP2003332422A (en) * 2002-05-13 2003-11-21 Sony Corp Semiconductor device and its manufacturing method
JP2005277390A (en) * 2004-02-27 2005-10-06 Handotai Rikougaku Kenkyu Center:Kk Semiconductor device and its manufacturing method
JP2006216690A (en) * 2005-02-02 2006-08-17 Renesas Technology Corp Semiconductor device

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KR100232506B1 (en) * 1995-06-27 1999-12-01 포만 제프리 엘. Copper alloys for chip and package interconnections and method of making
JP4355039B2 (en) * 1998-05-07 2009-10-28 東京エレクトロン株式会社 The method of manufacturing a semiconductor device and a semiconductor device
US6635528B2 (en) * 1999-12-22 2003-10-21 Texas Instruments Incorporated Method of planarizing a conductive plug situated under a ferroelectric capacitor
JP2006073635A (en) * 2004-08-31 2006-03-16 Renesas Technology Corp Semiconductor device and its manufacturing method
US7189626B2 (en) * 2004-11-03 2007-03-13 Micron Technology, Inc. Electroless plating of metal caps for chalcogenide-based memory devices

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JP2000058544A (en) * 1998-08-04 2000-02-25 Matsushita Electron Corp Semiconductor device and manufacture of the same
JP2003332422A (en) * 2002-05-13 2003-11-21 Sony Corp Semiconductor device and its manufacturing method
JP2005277390A (en) * 2004-02-27 2005-10-06 Handotai Rikougaku Kenkyu Center:Kk Semiconductor device and its manufacturing method
JP2006216690A (en) * 2005-02-02 2006-08-17 Renesas Technology Corp Semiconductor device

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