USRE46335E1 - Switching device having a non-linear element - Google Patents

Switching device having a non-linear element Download PDF

Info

Publication number
USRE46335E1
USRE46335E1 US14612025 US201514612025A USRE46335E US RE46335 E1 USRE46335 E1 US RE46335E1 US 14612025 US14612025 US 14612025 US 201514612025 A US201514612025 A US 201514612025A US RE46335 E USRE46335 E US RE46335E
Authority
US
Grant status
Grant
Patent type
Prior art keywords
voltage
cell
non
conductive state
top electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US14612025
Inventor
Wei Lu
Sung Hyun Jo
Hagop Nazarian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Crossbar Inc
Original Assignee
Crossbar Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/24Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures
    • H01L27/2409Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures comprising two-terminal selection components, e.g. diodes
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/003Cell access
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/004Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0069Writing or programming circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0097Erasing, e.g. resetting, circuits or methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/24Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures
    • H01L27/2463Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/08Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H01L45/085Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/122Device geometry
    • H01L45/1233Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/145Oxides or nitrides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/148Other compounds of groups 13-15, e.g. elemental or compound semiconductors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10Resistive cells; Technology aspects
    • G11C2213/15Current-voltage curve
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50Resistive cell structure aspects
    • G11C2213/56Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/73Array where access device function, e.g. diode function, being merged with memorizing function of memory element
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/76Array using an access device for each cell which being not a transistor and not a diode

Abstract

Method for a memory including a first, second, third and fourth cells include applying a read, program, or erase voltage, the first and second cells coupled to a first top interconnect, the third and fourth cells coupled to a second top interconnect, the first and third cells coupled to a first bottom interconnect, the second and fourth cells are to a second bottom interconnect, each cell includes a switching material overlying a non-linear element (NLE), the resistive switching material is associated with a first conductive threshold voltage, the NLE is associated with a lower, second conductive threshold voltage, comprising applying the read voltage between the first top and the first bottom electrode to switch the NLE of the first cell to conductive, while the NLEs of the second, third, and the fourth cells remain non-conductive, and detecting a read current across the first cell in response to the read voltage.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Reissue of U.S. Pat. No. 8,767,441 B2 issued Jul. 1, 2014 that claims priority to and is a continuation-in-part of U.S. application Ser. No. 13/149,757, filed May 31, 2012. This application also 2011, now issued as U.S. Pat. No. 8,502,185 on Aug. 6, 2013, and that claims priority to U.S. application Ser. No. 13/290,024, filed Nov. 4, 2011, now issued as U.S. Pat. No. 8,467,227 on Jun. 18, 2013, which is a non-provisional of U.S. Application No. 61/410,035, filed Nov. 4, 2010, U.S. Application No. 61/712,171, filed Oct. 10, 2012, and U.S. application No. 61/786,100, filed Mar. 15, 2013. These cited documents are incorporated by reference herein, for all purposes.

JOINT RESEARCH AGREEMENT

The presently claimed invention was made by or on behalf of the below listed parties to a joint university-corporation research agreement. The joint research agreement was in effect on or before the date the claimed invention was made and the claimed invention was made as a result of activities undertaken within the scope of the joint research agreement. The parties to the joint research agreement are The University of Michigan and Crossbar, Incorporated.

BACKGROUND

The present invention is related to switching devices. More particularly, the present invention provides a structure and a method for forming non-volatile resistive switching memory devices characterized by a suppression of current at low bias and a high measured ON/OFF resistance ratio.

The success of semiconductor devices has been mainly driven by an intensive transistor down-scaling process. However, as field effect transistors (FET) approach sizes less than 100 nm, problems such as short channel effect start to prevent proper device operation. Moreover, such sub 100 nm device size can lead to sub-threshold slope non-scaling and increased power dissipation. It is generally believed that transistor based memories such as those commonly known as Flash memory may approach an end to scaling within a decade. Flash memory is one type of non-volatile memory device.

Other non-volatile random access memory (RAM) devices such as ferroelectric RAM (Fe RAM), magneto-resistive RAM (MRAM), organic RAM (ORAM), and phase change RAM (PCRAM), among others, have been explored as next generation memory devices. These devices often require new materials and device structures to couple with silicon based devices to form a memory cell, which lack one or more key attributes. For example, Fe-RAM and MRAM devices have fast switching characteristics and good programming endurance, but their fabrication is not CMOS compatible and size is usually large. Switching for a PCRAM device uses Joules heating, which inherently has high power consumption. Organic RAM or ORAM is incompatible with large volume silicon based fabrication and device reliability is usually poor.

As integration of memory devices increases, the size of elements is reduced while the density of elements in a given area is increased. As a result, dark current or leakage current becomes more of a problem, where leakage current can return a false result for a read operation or cause an unintentional state change in a cell. The problem of leakage current is particularly acute in two-terminal devices, in which multiple memory cells can form leakage paths through interconnecting top and bottom electrodes.

Conventional approaches to suppressing leakage current in switching devices include coupling a vertical diode to a memory element. However, the external diode approach has several disadvantages. In general, the diode fabrication process is a high temperature process, typically conducted above 500 degrees Celsius. Because most diodes rely on a P/N junction, it is difficult to scale the diode height to achieve a memory and diode structure with a desirable aspect ratio. And finally, a conventional diode is only compatible with a unipolar switching device, and not a two-way bipolar device. It is therefore desirable to have a robust and scalable method and structure for a highly integrated memory that is not adversely affected by leak currents.

BRIEF SUMMARY OF THE INVENTION

The present invention is generally related to switching devices. More particularly, the present invention provides a structure and a method for forming a non-volatile memory cell using resistive switching. It should be recognized that embodiments according the present invention have a much broader range of applicability.

In a specific embodiment, a switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

The switching device includes a RRAM in an embodiment.

The switching device include a PCRAM in an embodiment.

The present invention has a number of advantages over conventional techniques. For example, embodiments of the present invention allow for a high density non-volatile memory characterized by high switching speed, low leakage current characteristic, and high device yield. Depending on the embodiment, one or more of these may be achieved. These and other advantages will be described below in more detail in the present specification.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments will hereinafter be described in conjunction with the appended drawings, wherein like designations denote like elements, and wherein:

FIG. 1 illustrates a non-volatile memory device including a memory cell that has a bottom electrode, a switching medium, and a top electrode according to an embodiment of the present invention;

FIG. 2 illustrates I-V resistance switching characteristics of a resistive memory cell;

FIG. 3A illustrates a two-terminal memory cell that is placed in an ON state by applying a program voltage VPROGRAM to the top electrode;

FIG. 3B illustrates a two-terminal memory cell that is placed in an OFF state by applying an erase voltage VERASE to the top electrode;

FIG. 4 illustrates a memory array including a leakage current;

FIG. 5 illustrates a non-volatile memory cell including a nonlinear element according to an embodiment of the present invention;

FIG. 6A illustrates I-V characteristics of a digital nonlinear element subjected to a voltage sweep;

FIG. 6B illustrates I-V characteristics of a switch combined with a digital nonlinear element in an initially OFF state subjected to a positive voltage sweep;

FIG. 6C illustrates I-V characteristics of a switch combined with a digital nonlinear element in an initially OFF state subjected to a negative voltage sweep;

FIG. 6D illustrates I-V characteristics of a switch combined with a digital nonlinear element in an initially ON state subjected to a positive voltage sweep;

FIG. 6E illustrates I-V characteristics of a switch combined with a digital nonlinear element in an initially ON state subjected to a negative voltage sweep;

FIG. 7A illustrates I-V characteristics of an analog nonlinear element subjected to a positive voltage sweep;

FIG. 7B illustrates I-V characteristics of a switch combined with an analog nonlinear element in an initially OFF state subjected to a positive voltage sweep;

FIG. 7C illustrates I-V characteristics of a switch combined with an analog nonlinear element in an initially OFF state subjected to a negative voltage sweep;

FIG. 7D illustrates I-V characteristics of a switch combined with an analog nonlinear element in an initially ON state subjected to a positive voltage sweep;

FIG. 7E illustrates I-V characteristics of a switch combined with an analog nonlinear element in an initially ON state subjected to a negative voltage sweep; and

FIG. 8A illustrates I-V characteristics of a non-volatile memory cell including a nonlinear element according to an embodiment of the present invention; and

FIG. 8B illustrates a memory array including leakage currents.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

The present invention is generally directed to a memory device. More particularly, the present invention provides a structure and a method for a resistive switching cell having a nonlinear element. The switching cell may be used in a Resistive Random Access Memory (RRAM) or any highly integrated device. It should be recognized that embodiments of the present invention can have a broader range of applicability. Although the present invention is described with respect to specific embodiments, the embodiments are only used for illustrative purposes and should not be considered limiting.

RRAM is typically a two terminal device in which a switching element is sandwiched between a top electrode and a bottom electrode. The resistance of the switching element is varied by applying a voltage to the electrodes or a current through the switching element. Resistive switching can be bipolar or unipolar. In bipolar switching, the change in resistance of the switching element depends on polarity and a magnitude of a current or voltage based applied electrical signal. In the case of unipolar switching, the change in resistance of the switching element depends only on the magnitude of the applied voltage or current and typically is a result of Joule heating within the switching element. Embodiments of the present invention are explained with respect to a two-terminal RRAM device using bipolar switching, but are not limited thereto. As used herein, the terms “RRAM” or “resistive memory cell” refer to a memory cell or memory device that uses a switching medium whose resistance can be controlled by applying an electrical signal without ferroelectricity, magnetization, and phase change of the switching medium. The present invention is not limited to implementation in RRAM, e.g., the invention may be implemented using the phase change RAM.

FIG. 1 illustrates a resistive memory cell 100 in a non-volatile memory device, e.g., a semiconductor memory chip. The memory cell includes a bottom electrode 102, a switching medium 104, and a top electrode 106 according an embodiment of the present invention. The switching medium 104 exhibits a resistance that can be selectively set to various values and reset using appropriate control circuitry. The memory cell 100 is a two-terminal resistive memory device, e.g., RRAM, in the present embodiment. Terms such as “top” or “bottom” are used for illustrative purpose only and should not construe to be limiting.

In the present embodiment, the memory cell 100 is an amorphous-silicon-based resistive memory cell and uses amorphous silicon (a-Si) as the switching medium 104. The resistance of the switching medium 104 changes according to formation or retrieval of a conductive filament inside the switching medium 104 according to a voltage applied to the electrodes. In an embodiment, the switching medium 104 is substantially free of dopants. In another embodiment, the switching medium 104 is a-Si doped with boron. In some embodiments, the resistive switching layer includes a silicon oxide, e.g. a silicon sub oxide, (e.g SixOy, where x 0<y<=1, 0<x<2,) or sub-oxide material such as Ge, SixGey, and SixGeyOz. It should be understood that any such sub-oxide refers to a non-stoichiometric oxide. An example of this is silicon oxide: stoichiometric silicon oxide is SiO2, and non-stoichiometric oxide may be SiOx where 0<x<2. In various embodiments, other forms of non-stoichiometric oxide may be formed or grown using various fabrication techniques.

The top electrode 106 is a conductive layer containing silver (Ag) and acts as the source of filament-forming ions in the a-Si structure. Although silver is used in the present embodiment, it will be understood that the top electrode 106 can be formed from various other suitable metals, such as gold (Au), nickel (Ni), aluminum (Al), chromium (Cr), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), and cobalt (Co). In certain embodiments, the bottom electrode 102 is pure metal, a boron-doped electrode, or other p-type polysilicon or silicon-germanium, which is in contact with a lower-end face of the a-Si structure. In an embodiment, the memory cell 100 is configured to store more than a single bit of information, e.g., by adjusting the external circuit resistance, as explained in application Ser. No. 12/575,921, filed on Oct. 9, 2009, which is entitled “Silicon-Based Nanoscale Resistive Device with Adjustable Resistance” and is incorporated by reference in its entirety.

FIG. 2 illustrates resistance switching characteristics of the memory cell 100 according to an embodiment of the present invention. The switching medium 104 displays a bipolar switching effect. The resistance of the switching medium 104 changes depending on the polarity and magnitude of the voltage signal applied to the switching medium 104 via the top electrode 106 and the bottom electrodes 102. The memory cell 100 is changed into an ON state (low resistance state) when a positive voltage equal to or greater than a threshold program voltage (also referred to as a “program voltage”) VPROGRAM is applied. In an embodiment, the program voltage ranges between 1 volt to 5 volts depending on the materials used for the switching medium 104 and the top electrode 106. In another embodiment, the program voltage ranges between 1 volt and 3 volts. The memory cell 100 is switched back to an OFF state (high resistance state) when a negative voltage equal to or greater than a threshold erase voltage (also referred to as “erase voltage”) VERASE is applied. In an embodiment, the erase voltage ranges from −2 volts to −5 volts. The cell state is not affected if the voltage applied is between two threshold voltages VPROGRAM and VERASE, which enables a low-voltage read process. Once the memory cell 100 is set to a specific resistance state, the memory cell 100 retains the information for a certain period (or retention time) without electrical power.

FIG. 2 illustrates a current-voltage (I-V) relationship through a switching operation of a non-rectifying memory cell 100. Electrical current flows from the top electrode 106 to the bottom electrode 102 when the potential applied to the top electrode 106 is positive potential with respect to the bottom electrode 102. On the other hand, current flows in the reverse direction if the potential applied to the top electrode 106 is negative with respect to the bottom electrode 102.

FIGS. 3A and 39 illustrate a switching mechanism of the memory cell 100 during the ON and OFF states according to an embodiment of the present invention. The switching in the switching medium 104 is based on formation and retrieval of a conductive filament, or a plurality of filaments, in a filament region in the switching medium 104 according to the program and the erase voltages applied to the bottom electrode 102 and the top electrode 106 of the memory cell 100.

FIG. 3A illustrates the memory cell 100 that is placed in an ON state by applying the program voltage VPROGRAM to the top electrode 106. The switching medium 104, made of a-Si, is provided between the bottom electrode 102 and the top electrode 106. An upper portion of the switching medium 104 includes a metallic region (or conductive path) 302 that extends from the top electrode 106 to approximately 10 nm above the bottom electrode 102. The metallic region 302 is formed during an electroforming process when a slightly larger voltage than a subsequent switching voltage, e.g., 3˜5 V, is applied to the top electrode 106. This large voltage causes the electric field-induced diffusion of the metal ions from the top electrode 106 toward the bottom electrode 102, thereby forming a continuous conductive path 312. A lower portion of the switching medium 104 defines a filament region 304, wherein the filament 310 is formed when the program voltage VPROGRAM is applied after the electroforming process. The continuous conductive path 312 and the filament 310 can also be formed together during the electroforming process. The filament 310 comprises a series of metal particles, which are trapped in defect sites in a lower portion of the switching medium 104 when the program voltage VPROGRAM applied provides sufficient activation energy to push a number of metal ions from the metallic region 302 toward the bottom electrode 102.

The filament 310 is believed to be comprised of a collection of metal particles that are separated from each other by the non-conducting switching medium 104 and that do not define a continuous conductive path, unlike the continuous conductive path 312 in the metallic region 302. The filament 310 extends about 2 to 10 nm depending on implementation. The conduction mechanism in an ON state is electrons tunneling through the metal particles in the filament 310. The cell resistance is dominated by the tunneling resistance between the metal particle 306 and the bottom electrode 102. The metal particle 306 is a metal particle in the filament region 304 that is closest to the bottom electrode 102 and that is the last metal particle in the filament region 304 in an ON state.

FIG. 3B illustrates the memory cell 100 that is placed in an OFF state by applying an erase voltage VERASE to the top electrode 106. The erase voltage exerts sufficient electromagnetic force to dislodge the metal particles trapped in the defects sites of the a-Si and retrieves at least part of the filament 310 from the filament region 304. The metal particle 308 that is closest to the bottom electrode 102 in an OFF state is separated from the bottom electrode 102 by a distance greater than the metal particle 306 during an ON state. This increased distance between the metal particle 308 and the bottom electrode 102 places the memory cell 100 in a high resistance state compared to an ON state. In an embodiment, the resistance ratio between ON/OFF states ranges from 10E3 to 10E7. Memory cell 100 behaves like a resistor in an ON state and a capacitor in an OFF state (i.e., the switching medium 104 does not conduct a current in any meaningful amount and behaves as a dielectric in an OFF state). In an implementation, the resistance is 10E5 Ohm in an ON state and 10E10 Ohm in an OFF state. In another implementation, the resistance is 10E4 Ohm in an ON state and 10E9 Ohm in an OFF state. In yet another implementation, the resistance is at least 10E7 Ohm in an OFF state.

FIG. 4 illustrates a portion of an array 400 that is in a crossbar configuration in which the (common) top electrodes and the (common) bottom electrodes are arranged in an orthogonal manner according to an embodiment of the present invention. An array of such crossbar structures includes a plurality of parallel (common) top electrodes and a plurality of parallel (common) bottom electrodes with switching elements disposed between the intersection regions of the (common) top electrodes and the (common) bottom electrodes. Certain limitations may exist in such a configuration, as described below.

Four memory cells 402, 404, 406, and 408 are shown. Memory cells 404 and 406 share a common first top electrode 410, while cells 402 and 408 share a common second top electrode 418. The first top electrode 410 and the second top electrode 418 are arranged parallel to each other. Memory cells 402 and 404 share a common first bottom electrode 412 and cells 406 and 408 share a common second bottom electrode 420. The first bottom electrode 412 and the second bottom electrode 420 are spatially arranged parallel to each other. In addition, each of the top electrodes is configured to be non-parallel to each of the bottom electrodes.

To determine a state of a target cell which has a high resistance state, a voltage is applied and a current flowing through the target cell is measured. If some cells in the crossbar array are in low resistance states, the voltage applied to the target cell can cause a leakage current to flow through the untargeted cells instead. In this case the cells causing the leakage, including the target cell, are interconnected through shared electrodes. The leakage current can form a current path, commonly known as a sneak current or a sneak current path, through these untargeted cells. Such a sneak current can cause undesirable behavior in a switching array.

For example, in an exemplary array, cells 402, 404, and 406 are at a low resistance ON state, and cell 408 is at a high resistance OFF state. Because the ON state is characterized by a low resistance, a sneak path 416 may be formed allowing current to flow through cells 402, 404, and 406. Thus, when a read voltage is applied to target cell 408, leakage current flowing along sneak path 416 may cause an erroneous reading of an ON state result.

In some embodiments, a sneak path can be very short, existing in as few as two forward biased cells and one reverse biased cell. In addition, once started, a sneak path can propagate throughout the array through cells in the ON state. The most common conductive path in a switching array is the shared top and bottom electrodes. Sneak path 416 is only one example of a sneak path passing leakage current through an array.

To mitigate problems caused by leakage current in a switching array, a nonlinear element (NLE) may be included in a resistive switching device. NLEs can be generally divided into two categories: an NLE that exhibits digital-like behavior, or “digital NLE,” and an NLE that exhibits analog-like behavior, or an “analog NLE,” both of which are described in detail separately below. The categories of digital and analog behavior are not strictly defined, so it is possible for a particular NLE to have properties that are characteristic of both digital and analog behavior, or somewhere in between. In its most basic form, an NLE is an element that has a nonlinear response with respect to voltage, for instance, with a nonlinear I-V relationship. In most embodiments, the relationship is characterized by a high resistance state at low amplitude voltages and a lower resistance state at higher amplitude voltages, with a nonlinear transition from the high resistance state to the low resistance state. Unlike a switching medium, an NLE does not have a memory characteristic; an NLE returns to an original state when a voltage is no longer applied. An NLE that is suitable for suppressing leak currents is characterized by a high resistance state at a low bias, a lower resistance state at a higher bias, and a threshold between the states.

In an embodiment, an NLE is a two terminal device which shows an apparent threshold effect such that the resistance measured below a first voltage is significantly higher than the resistance measured above a second voltage. In a typical embodiment, the resistance below the first voltage is more than 100 times greater than the resistance above the second voltage. In other embodiments, the ratio may be in the range of about 100 to about 500 times, in the range of about 500 times to about 1000 times, in the range of about 1000 times to about 10,000 times, or the like, depending upon specific engineering requirements of the NLE material. In some embodiments, the first and second voltages are different, and are typically referred to as a hold voltage VHOLD and threshold voltage VTH, respectively. In other embodiments, the first voltage and second voltage may be the same. In various embodiments, these relationships may exist in both polarities of voltage, or only in one polarity, and the NLE can be a single material or multiple layers of different materials.

As shown in FIG. 5, to mitigate the effects of leakage current in a memory cell 500, an NLE 504 is electrically coupled in series to the top electrode 508, bottom electrode 502, and switching medium 506. An NLE 504 may be disposed between the bottom electrode 502 and switching medium 506. In other embodiments, the NLE is disposed between the top electrode 508 and the switching medium 506. Higher temperatures may be experienced by the lower portions of a semiconductor device during various semiconductor processes, so an NLE that is located lower in a stack structure may be designed to withstand higher temperatures than an NLE located further from the substrate.

The behavior of a digital NLE is characterized by abrupt changes in current at certain voltages, which may be referred to as threshold voltages. Such behavior is illustrated in FIG. 6A, which shows the results of a voltage sweep in an embodiment with respect to current on an NLE that is not coupled to a resistive switching device. As positive bias voltage is applied to the NLE, the NLE is in a resistive state characterized by high resistance until it reaches the threshold voltage VTH1. After this threshold has been reached, the NLE will retain its conductive state until the applied voltage drops below a hold voltage VHOLD1. Thus a NLE that is in a conductive state by having a voltage applied above VTH1 will continue to have a low resistance so long as a voltage above VHOLD1 is supplied to the NLE, after which it reverts to the original high-resistance state. An NLE does not have a memory characteristic, so the same I-V relationship is experienced every time a voltage is applied from an original state.

Referring back to FIG. 6A, when a negative bias voltage is applied that is more negative than a threshold voltage VTH2, an abrupt transition is experienced, and the resistance in the NLE is significantly reduced. The NLE retains its low resistance state until the voltage becomes less negative than a value VHOLD2, at which point the NLE reverts to an original high resistance state. Although FIG. 6A shows an embodiment with symmetrical I-V behavior between positive and negative bias performance, in other embodiments the relationship is not symmetrical.

FIGS. 6B to 6E show I-V relationships of an embodiment where an NLE is coupled to a memory cell (“combined device”), in this case a digital NLE. Memory cell 500 is an example of such a combined device. If the memory cell depicted in those figures was not coupled to the NLE, it would have an I-V response according to FIG. 2. Turning to FIG. 6B, an I-V curve showing a program operation switching a cell from an initially OFF state to an ON state is shown. To establish a conductive ON state in a cell, a voltage above VPROGRAMC is applied. VPROGRAMC is the program voltage for the combined device, which switches the combined device from an OFF state to an ON state. VHOLDC1 is the hold voltage of a combined device, which performs in essentially the same way as VHOLDC1 described above. In a preferred embodiment, VHOLD1 is less than VTH1, which is less than VPROGRAM.

The relationships between I-V performance in a memory cell, an NLE, and a combined device can also be explained through equations. The equations assume that both the NLE and the switching medium switch instantly (e.g., a few ns{tilde over ( )}a few hundreds of ns) when experiencing a threshold voltage. In addition to the definitions given above, the following variables are designated:

  • RMOFF=The OFF state resistance of a memory element
  • RMON=The ON state resistance of a memory element
  • RNOFF=The OFF state resistance of an NLE
  • RNON=The ON state resistance of an NLE

Using these variables, the relationship between the hold voltage of a combined device and the hold voltage of an NLE can be expressed as:
VHOLDC1=((RMON+RNON)/RNON)VHOLD1

The value for the program voltage of the combined device can be expressed as:
VPROGRAMC≃small{large((RMOFF+RNOFF)/RNOFF)VTH1,VPROGRAM),large(VTH1,((RMOFF+RNOFF)/RMOFF)VPROGRAM)}
Where “small” indicates the smaller of two values in a set, and “large” indicates the larger of two values in a set. In most embodiments, the VPROGRAM is significantly higher than VTH1, and VPROGRAMC is thus similar to VPROGRAM.

FIG. 6C shows the result of a negative voltage sweep of the same switch in an OFF state. Because it is already in the OFF state, a negative voltage does not cause an erase operation, and the cell remains in a high resistance OFF state.

FIGS. 6D and 6E show I-V relationships of a combined device (e.g. memory cell 500) where the memory cell is initially in a low-resistance ON state. FIG. 6D shows a read operation, where the read voltage must be greater than threshold voltage VTHC1 to return an accurate read value. As the read voltage drops below the hold voltage VHOLDC1, the resistance in the cell increases substantially. The threshold voltage of the combined device is related to the threshold voltage of the NLE through the following equation:
VTHC1=((RMON+RNOFF)/RNOFF)VTH1≃VTH1
Thus, the read threshold voltage of the combined device is approximately the same as the threshold voltage of the NLE, or VTHC1≅VTH1.

Similarly, as seen in FIG. 6E, an erase operation must overcome a second threshold value VTHC2 to allow current to start flowing through the cell, and the switch is changed to a high-resistance OFF state at voltage VERASEC Like the positive threshold voltage, the negative threshold voltage of the combined device is about the same as the negative threshold voltage of the NILE. The value of the erase voltage VERASEC in a combined device can be expressed as:
VERASEC≃large((RMON+RNON)/RMON)VERASE,VTH2)
The relationship between the negative threshold voltages of a discrete and combined device can be expressed as:
VTHC2=((RMON+RNOFF)/RNOFF)VTH2≃VTH2.
So that in most embodiments, VTHC2≅VTH2.

Various embodiments of a digital NLE can be made of many different materials. For example, a digital NLE can be a threshold device such as a film that experiences a field-driven metal-insulating (Mott) transition. Such materials are known in the art, and include VO2 and doped semiconductors. Other threshold devices include material that experiences resistance switching due to electronic mechanisms observed in metal oxides and other amorphous films, or other volatile resistive switching devices such as devices based on anion or cation motion in oxides, oxide heterostructures, or amorphous films. A digital NLE can also be in the form of a breakdown element exhibiting soft breakdown behavior such as SiO2, HfO2, and other dielectrics. Examples of such breakdown elements are described in further detail by application Ser. No. 12/826,653, filed on Jun. 29, 2010, which is entitled “Rectification Element for Resistive Switching for Non-volatile Memory Device and Method,” and is incorporated by reference in its entirety. In other embodiments, the NLE may be a solid electrolyte material. The solid electrolyte material can include be chalcogenide based such as GexSy, GexSey, SbxTey, AgxSey, and CuxSy, or can be metal oxide based such as WOx, TiOx, AlOx, HfOx, CuOx, and TaOx, where 0<x<appropriate stoichiometric value (e.g. 2, 3, etc.) (e.g. GeS, GeSe, WO3, or SbTe, and the like).

As is known in the art, the precise values of threshold, hold, program and erase can be adjusted for different embodiments by changing the form of and materials used for the NLE and the memory cell. In various embodiments the threshold voltage for the NLE can be about the same as the hold voltage, the program voltage, or both. In other embodiments the threshold voltage for the NLE can exceed the program and erase voltages of a resistive switching device.

An analog NLE differs from a digital NLE in that its I-V relationship is characterized by a more gradual transition when current starts to flow through the element. As shown in FIG. 7A, which illustrates the response of an analog NLE to a voltage sweep, the current transition follows an exponential-like curve. The transition or threshold is therefore less abrupt than a digital NLE. Threshold voltage values where substantial current starts to flow through an analog NLE are designated as VA and VB for positive and negative bias values, respectively. Another significant difference between an analog and digital NLE is that an analog NLE does not experience the hysteretic hold voltage characteristic of a digital NLE.

FIGS. 7B to 7E show I-V characteristics of a combined device with an analog NLE. As shown in FIG. 7B, when a program voltage VPROGRAMC is applied to a combined device where the switch is initially in an OFF state, the switch changes to a low resistance ON state. The VPROGRAMC is approximately the sum of the VA of the NLE and the VPROGRAM of the switch as shown in FIG. 2, or VPROGRAMC≈VA+VPROGRAM. As a result, the programming voltage of a combined device with an analog NLE is typically higher than the programming voltage of a switching element alone.

Turning now to FIG. 7C, a negative voltage sweep of a combined device in an OFF state is shown. Because the switch is already in an OFF state, the negative voltage does not induce a state change, and the switch remains in a high resistance state.

FIG. 7D shows the result of a read operation in a combined switch that is in an ON state. In the present embodiment, VAC<VREAD<VPROGRAMC. Because the switch is already in a low-resistance ON state, current flow above the threshold voltage VAC is characterized by low resistance. Circuitry can detect the current flow, resulting in a positive read result. The value tier VA is not affected by the switching apparatus in most embodiments, so typically VAC≈VA.

FIG. 7E shows an I-V curve for an erase operation in a combined device. To change the switch from the ON state to the OFF state, a voltage of VERASEC is applied to the combined device, thereby increasing the resistance of the switch. The voltage required to complete an erase operation in a combined device is normally the sum of the erase value of the discrete switch and the threshold value of the analog NLE, or VERASEC≈VERASE+VB.

An analog NLE can be any element that exhibits the above described behavior. Examples of suitable materials include a punch-through diode, a Zener diode, an impact ionization (or avalanche) element, and a tunneling element such as a tunneling barrier layer. Such elements can be fabricated using standard fabrication techniques.

In most embodiments, |VA, VB|<|VPROGRAM, VERASE|. As is known in the art, the precise threshold values of VA, VB, program, and erase can be adjusted for different embodiments by changing the form of and materials used for the NLE and the memory cell. In various embodiments the threshold voltage for the NLE can be about the same as the program voltage. In other embodiments the threshold voltage can exceed the program and erase voltages.

In other embodiments, a resistive switching cell may be configured to retain multiple resistive states. That is, rather than being configured to have binary states of ON and OFF, a cell can retain a plurality of resistance states. An array of such switches has the same limitations regarding leakage current, and would similarly benefit from the inclusion of an NLE.

FIGS. 8A-B illustrate examples according to various embodiments of the present invention. In various embodiments of the present invention, as discussed in FIG. 4, when a program (or read or erase) voltage is applied to a target cell 408, e.g. across second top electrode 418 and second bottom electrode 420, a sneak path 416 may allow a sneak path current to flow through cells 402, 404 and 406. To reduce this, a non-linear element, described above (e.g. NLE 504 in FIG. 5), was incorporated in each memory cell. The characteristics of an example NLE was illustrated in FIG. 6A. More particularly, when a voltage across the NLE exceeded VTH1 the resistance for the NLE switched from a relatively non-conductive state to a relatively conductive state. Accordingly, in an example, to program target cell 408, a program voltage would be applied to target cell 408 that would exceed VTH1 and exceed the programming voltage of target cell 408 (VProgram, FIG. 8A). In another example, to read target cell 408, a read (or program) voltage would be applied to target cell 408 that would exceed VTH1, but would be less than the programming voltage of target cell 408 (VProgram, FIG. 8A).

In an example described in co-pending application Ser. No. 13/290,024, filed Nov. 4, 2011, incorporated by reference above, the read voltage to the target cell was limited to be no greater than three times the threshold voltage of the nonlinear element. This three times number assumed that unselected top electrodes and unselected bottom electrodes in the memory array were allowed to float. By way of explanation, using the numbering of FIG. 4 above, in FIG. 8B, the read voltage would not only be applied across target cell 408, but also across sneak path 416 through cells 402, 404 and 406. In such a configuration, if the read (or program) voltage exceeded three times the voltage threshold (e.g. 3×VTH1) of the non-linear element, the voltage across non-linear element of 402, for example, would also exceed VTH1. Accordingly, the NLE of 402 would switch to a relatively-conductive state, and significant current could flow through the sneak path 416. It was recognized in the above incorporated patent application, that to reduce sneak path current, unselected cells, e.g. 402, 404 and 406 had to have voltages applied that were lower than the threshold voltage (e.g. VTH1) of the non-linear elements. For example, when the read (or program) voltage (V408) is applied across target cell 408, the resultant relationships should be met: voltage across cell(s) V402<VTH1, voltage across cell(s) V404<VTH1, and voltage across cell(s) 406<VVTH1. Additionally, the voltages across these unselected cells should be greater than VTH2 (FIG. 8A). By observing such conditions, it is understood that NLEs of unselected cells (along sneak paths) should have voltages across hem such that they remained non-conductive, see suppressed region 800 in FIG. 8A.

In various embodiments of the present invention, in the example of FIG. 4, during a read operation (for example), when the read voltage Vread is applied to target cell 408, the voltage Vread (e.g. VTH1<Vread (V408)<Vprogram, e.g. Vread=2 volts) is applied to second top electrode 418 and ground (e.g. Vg, e.g. Vg=0 volts) is applied to the second bottom electrode 420. In the case of a program operation V408>Vprogram. To reduce power consumption/requirements of the memory, the inventors have recognized that it is advantageous to set unselected bit lines (e.g. top electrodes/conductors) and unselected word lines (e.g. bottom conductors/electrodes) to voltages other than floating during a read operation. The specific voltages may vary, and are generally guided by the following concepts.

For a read (or program or erase) operation, for memory cells, e.g. memory cells 402, that share second top electrode 418 (e.g. selected bit line), the difference (V402) between the voltage across second top electrode 418 (VSBL) and unselected word lines, (e.g. first bottom electrode 412) (VUSWL) should be less than the voltage threshold of the NLE of memory cells such as memory cell 402. In variable format: VSBL−VUSWL<VTH1 or V402<VTH1 (FIG. 8A). This condition would inhibit the NLE memory cells such as memory cell 402 from entering into relatively non-conductive states. It should be noted that, depending upon the polarity of V402, to inhibit the NLE of memory cells, such as memory cell 402 from become relatively non-conductive in a reverse-bias condition, the relationship maybe VTH2<V402<VTH1. This was graphically illustrated by the flat region in FIG. 6D (0 to VTHC1), and the flat region in FIG. 6E (VTHC2 to 0), illustrated together in region 800 in FIG. 8A. These restrictions are desirable also in program or erase operations upon memory cell 408. In other memory configurations, these specific relationships and polarities may be changed.

For a read (or program or erase) operation, for memory cells, e.g. memory cells 406, that share second bottom electrode 420 (e.g. selected word line), the difference V406 between the voltage across unselected bit lines (e.g. first top electrode 410) (VUSBL) and second bottom electrode 420 (e.g. selected word line) (VSWL) should be less than the voltage threshold of the NLE of memory cells such as memory cell 406. In variable format: VUSBL−VSWL<VTH1 V406<VTH1. This condition would inhibit the NLE of memory cells such as memory cell 406 from entering into relatively non-conductive states. It should be noted that, depending upon the polarity of V406, to inhibit the NLE of memory cells, such as memory cell 406 from become relatively non-conductive in a reverse-bias, the relationship maybe VTH2<V406<VTH1. This was graphically illustrated by the flat region in FIG. 6D (0 to VTHC1), and the flat region in FIG. 6E (VTHC2 to 0), illustrated together in region 800 in FIG. 8A. These restrictions are desirable also in program or erase operations upon memory cells 404. In various embodiments, VTH1 and |VTH2| may be different, or similar. In other memory configurations, these specific relationships and polarities may be changed.

For a read (or program or erase) operation, for memory cells, e.g. memory cells 404, that share unselected word lines (e.g. first bottom electrode 412), the difference (V404) between the voltage across unselected bit lines (e.g. first top electrode 410) (VUSBL) and unselected word lines (e.g. first bottom electrode 412) (VUSWL) should be less than the voltage threshold of the NLE of memory cells such as memory cells 404. In variable format: VUSBL−VUSWL<VTH1 or V404<VTH1. This condition would inhibit the NLE of memory cell 404 from entering into a relatively non-conductive state. It should be noted that depending upon the polarity of V404, to inhibit the NLE of memory cells, such as memory cell 404 from become relatively non-conductive in a reverse-bias, the relationship maybe VTH2<V404<VTH1. This was graphically illustrated by the flat region in FIG. 6D (0 to VTHC1), and the flat region in FIG. 6E (VTHC2 to 0), illustrated together in region 800 in FIG. 8A. These restrictions are desirable also in program or erase operations upon memory cells 404. In other memory configurations, these specific relationships and polarities may be changed.

FIGS. 8A-B illustrate an example according to various embodiments of the present invention. In one example of the above, the programming voltage Vprogram=2 volts, the positive threshold voltage (VTH1) of the NLE=1 volt, and the negative threshold voltage (VTH2) of the NLE=−2 volts. In such a configuration, to perform a program operation, the selected word line (e.g. second bottom electrode 420) is grounded (VSWL=0 volts), and selected bit line (e.g. second top electrode 418) (VSBL) is greater than the positive threshold voltage (e.g. VTH1 (1 volt)<VSBL, Vprogram (2 volts)). Thus, Vprogram=V408. Additionally, the unselected word lines (e.g. first bottom electrode 412) are set to about 1.5 volts (VUSWL=1.5 volts), accordingly, the voltage across memory cells such as memory cells 402 are less than the NLE switching voltage (e.g. VTH2 (˜2 volts)<V402 (2 volts−1.5 volts=0.5 volts)<VTH1 (1 volts). Further, the unselected bit lines (e.g. first top electrode 410) (VUSBL) are set to about 0.5 volts, accordingly, the voltage across memory cells such as memory cells 406 are thus less than the NLE switching voltage (e.g. VTH2 (−2 volts)<V406 (0.5 volts−0 volts=0.5 volts)<VTH1 (1 volts). Still further, from above the unselected bit lines (e.g. first top electrode 410) are set to about 0.5 volts (VUSBL=0.5 volts), and the unselected word lines (e.g. first bottom electrode 412.) (VUSWL) are set to about 1.5 volts (VUSWL=1.5 volts). In such a configuration, because the bottom electrodes (e.g. 412) have a higher voltage than the top electrodes (e.g. 410), memory cells, such as memory cells 404 are in a reverse bias voltage region. Accordingly, the voltage across memory cells such as memory cell 404 are less than the NLE switching voltage VTH1, but also need to be greater than VTH2: (e.g. VTH2 (−2 volts)<V404 (0.5 volts−1.5 volts=−1.0 volts)<VTH1 (1 volts). As mentioned above, these restrictions are also desirable in write and erase operations. For example in a read case VTH1<Vread (V408)<Vprogram; and in an erase case Verase (V408)<VTH2.

In various embodiments, based upon the voltages V408, V402, V406, V404, and the like, the current requirements of memory cells may be computed during read, program, or erase operations. For example, power consumption for memory cells such as memory cells 402 (along the selected bit line second top electrode 418) is the number of cells times the current across memory cells (V402 (e.g. 0.5 volts)/resistance of NLE in relatively non-conductive state); plus power consumption for memory cells such as memory cells 406 (along unselected bit lines, first top electrode 410) is the number of cells times the current across memory cells (V406 (e.g. 0.5 volts)/resistance of NLE in relatively non-conductive state); plus power consumption for memory cells such as memory cells 404 (along unselected bit lines, first top electrode 410, and along unselected word lines, first bottom electrode 412) is the number of cells times the current across the memory cells (V404 (e.g. −1 volt)/resistance of NLE in relatively non-conductive state). In some embodiments, setting of the bias voltages of unselected bit lines 410 (VUSBL) and unselected word lines may 412 (VUSWL) be made considering the power consumption described above.

In one example, using a large array (e.g. 100×100) of memory cells, if the voltage of the unselected bit lines (e.g. first top electrode 410) (VUSBL) and the unselected word lines (e.g. first bottom electrode 412) (VUSWL) are substantially the same the voltages, V404 is small (e.g. about 0). Accordingly, the power consumption of these memory cells (99 cells×99 cells=9801 cells) is small (e.g. about 0), and power consumed/required is computed, consumed, mainly from the memory cells along the selected bit line 418 (99 cells along the second top electrode 418) and from the memory cells along the selected word line 420 (99 cells along the second bottom electrode 420). In one example of this VSBL=4V, VSWL=0V, VUSBL=2V, VUSWL=2V.

Although certain of the above passages have been described with respect to a read operation, it should be understood that the above also apply to other operations, such as programming operations and erase operations. In each of these situations, embodiments of the present invention incorporating NLE elements within a memory cell help to reduce sneak paths/currents through unselected memory cells. More particularly, for memory cells 402, 404 and 406 along sneak path 416, the voltages across these cells should be within a NLE non-conductive (suppressed) region 800, illustrated in FIG. 8A, to reduce sneak path current. This is in comparison with the graph illustrated in FIG. 2, for embodiments without NLE-type elements.

In other embodiments, NLEs with different threshold voltages may be used, resistive switching material having different program and erase voltages may be used, different voltages may be applied to bias unselected word lines and/or unselected bit lines, different polarity materials may be used, and the like. Still other embodiments may be applied to unipolar-type memory cells.

In light of the present patent disclosure, one of ordinary skill in the art will recognize that in other embodiments, the voltages for selected bit lines, unselected bit lines, selected word lines, unselected word lines, NLE threshold voltages, read voltages, and the like may vary from those illustrated above, depending upon specific engineering requirements, e.g. power consumption, performance, and the like

The examples and embodiments described herein are for illustrative purposes only and are not intended to be limiting. Various modifications or alternatives in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.

Claims (34)

We claim:
1. Method for operating a memory comprising:
applying a read voltage to the memory, wherein the memory comprising a plurality of cells including at least a first cell, a second cell, a third cell, and a fourth cell,
wherein the first cell and the second cell are coupled to a first top electrode,
wherein the third cell and the fourth cell are coupled to a second top electrode,
wherein the first cell and the third cell are coupled to a first bottom electrode,
wherein the second cell and the fourth cell are coupled to a second bottom electrode,
wherein each cell of the plurality of cells comprises a resistive switching material stack comprising a resistive switching material overlying a non-linear switching element material,
wherein the resistive switching material is characterized by a first voltage associated with switching from a non-conductive state to a conductive state,
wherein the non-linear switching element material is characterized by a second voltage associated with switching from a non-conductive state to a conductive state,
wherein the second voltage is less than the first voltage,
wherein the read voltage is between the first voltage and the second voltage, and
wherein applying the read voltage to the memory comprises applying the read voltage to the first top electrode while grounding the first bottom electrode to thereby cause non-linear switching element material of the first cell to be in the conductive state, while maintaining non-linear switching element material of the second cell, the third cell, and the fourth cell to remain in the non-conductive state; and
detecting a read current across the first cell in response to the read voltage.;
wherein the resistive switching material is characterized by a third voltage associated with switching from the conductive state to the non-conductive state;
wherein the non-linear switching element material is characterized by a fourth voltage associated with switching from the non-conductive state to the conductive state; and
wherein the third voltage is less than the fourth voltage.
2. The method of claim 1 wherein a resistance of the non-conductive state is related to a resistance of the conductive state in a range of ratios selected from a group consisting of: about 100 to about 500 times greater, about 500 to about 1000 times greater, about 1000 times to about 10,000 times greater.
3. The method of claim 1 wherein while applying the read voltage to the first top electrode while grounding the first bottom electrode, a voltage across the second cell is maintained at less than the second voltage.
4. The method of claim 1
wherein the resistive switching material is characterized by a third voltage associated with switching from the conductive state to the non-conductive state;
wherein the non-linear switching element material is characterized by a fourth voltage associated with switching from the non-conductive state to the conductive state; and
wherein the third voltage is less than the fourth voltage.
5. The method of claim 4 1 wherein while applying the read voltage to the first top electrode while grounding the first bottom electrode, a voltage across the fourth cell is maintained at greater than the fourth voltage to thereby maintain the non-linear switching element material of the third cell in the non-conductive state.
6. The method of claim 4 1 wherein while applying the read voltage to the first top electrode while grounding the first bottom electrode, the method further comprises applying a fifth voltage between ground and the read voltage to the second bottom electrode.
7. The method of claim 6 wherein while applying the read voltage to the first top electrode while grounding the first bottom electrode, the method further comprises applying a sixth voltage between ground and the read voltage to the second top electrode.
8. The method of claim 7 wherein a difference between the sixth voltage and the fifth voltage is greater than the fourth voltage.
9. The method of claim 1 further comprising:
applying a write voltage to the memory, wherein the write voltage exceeds the first voltage, wherein applying the write voltage to the memory comprises applying the write voltage to the first top electrode while grounding the first bottom electrode to thereby cause the resistive switching material of the first cell to be in the conductive state.
10. The method of claim 9 wherein applying the write voltage to the first top electrode comprises applying the write voltage to the first top electrode while grounding the first bottom electrode to thereby cause the non-linear switching element material of the first cell to switch from the non-conductive state to the conductive state.
11. A memory operated according to the method described in claim 1.
12. A memory comprising:
a plurality of cells including at least a first cell, a second cell, a third cell, and a fourth cell, wherein each cell of the plurality of cells comprises a resistive switching material stack comprising a resistive switching material overlying a non-linear switching element material, wherein the resistive switching material is characterized by a first voltage associated with switching from a non-conductive state to a conductive state, wherein the non-linear switching element material is characterized by a second voltage associated with switching from a non-conductive state to a conductive state, wherein a second voltage is less than the first voltage;
a plurality of top electrodes including a first top electrode and a second top electrode, wherein the first cell and the second cell are coupled to the first top electrode, and wherein the third cell and the fourth cell are coupled to the second top electrode;
a plurality of bottom electrodes including a first bottom electrode and a second bottom electrode, wherein the first cell and the third cell are coupled to the first bottom electrode, and wherein the second cell and the fourth cell are coupled to the second bottom electrode, wherein a read current path is associated with the first cell, wherein non-read current paths are associated with the second cell, the third cell, and the fourth cell, wherein the non-linear switching element material of the first cell is configured to reduce resistance of the read current path, and wherein the non-linear switching element material of the second cell, the third cell, and the fourth cell are configured to increase resistance of the non-read current; and
a voltage source coupled to the plurality of top electrodes and to the plurality of bottom electrodes, wherein the voltage source is configured to provide a plurality of voltages to the plurality of top electrodes and to the plurality of bottom electrodes.;
wherein the resistive switching material is characterized by a third voltage associated with switching from the conductive state to the non-conductive state;
wherein the non-linear switching element material is characterized by a fourth voltage associated with switching from the non-conductive state to the conductive state; and
wherein the third voltage is less than the fourth voltage.
13. The memory of claim 12
wherein the non-linear switching element material of the first cell is configured to be in the conductive state dependent upon a read voltage that is greater than the second voltage but less than the first voltage, that is applied to the first top electrode while grounding the first bottom electrode; and
wherein the voltage source is configured to provide the read voltage.
14. The memory of claim 12
wherein the non-linear switching element material of the second cell is configured to be in the non-conductive state dependent upon a read voltage that is greater than the second voltage but less than the first voltage, is applied to the first top electrode while grounding the first bottom electrode; and
wherein the voltage source is configured to provide the read voltage.
15. The memory of claim 14 wherein when the read voltage is applied to the first top electrode while grounding the first bottom electrode, a voltage greater than ground is applied to the second bottom electrode such that a voltage across the second cell is less than the second voltage.
16. The memory of claim 12 wherein the resistive switching material is selected from a group consisting of: an amorphous silicon material, a silicon sub-oxide, a silicon germanium sub-oxide.
17. The memory of claim 12 wherein each of the plurality of bottom electrodes comprises a metal or a conductive silicon material selected from a group consisting of: a doped polysilicon, and a doped silicon germanium material.
18. The memory of claim 12
wherein the resistive switching material is characterized by a third voltage associated with switching from the conductive state to the non-conductive state;
wherein the non-linear switching element material is characterized by a fourth voltage associated with switching from the non-conductive state to the conductive state; and
wherein the third voltage is less than the fourth voltage.
19. The memory of claim 12
wherein the non-linear switching element material of the fourth cell is configured to be in the non-conductive state dependent upon a read voltage that is greater than the second voltage but less than the first voltage, that is applied to the first top electrode while grounding the first bottom electrode; and
wherein a voltage difference greater than the fourth voltage is applied to the fourth cell.
20. The memory of claim 12
wherein the voltage source is configured to provide a read voltage to the first top electrode, wherein the voltage source is configured to provide a fifth voltage to the second bottom electrode and a sixth voltage to the second top electrode, wherein a voltage difference between the second top electrode and the second bottom electrode is greater than the fourth voltage.
21. The memory of claim 12 wherein a ratio between the resistance of the first cell compared to a resistance of the second cell is greater than 1:1000.
22. The memory cell of claim 12 wherein the non-linear switching material is selected from a group consisting of: a solid electrolyte material and a metal sub-oxide.
23. The memory cell of claim 12 wherein the non-linear switching material is bi-polar.
24. The memory cell of claim 12 wherein the non-linear switching material consists of multiple layers of materials.
25. A method for operating a memory comprising:
applying a program voltage to the memory, wherein the memory comprising a plurality of cells including at least a first cell, a second cell, a third cell, and a fourth cell,
wherein the first cell and the second cell are coupled to a first top electrode,
wherein the third cell and the fourth cell are coupled to a second top electrode,
wherein the first cell and the third cell are coupled to a first bottom electrode,
wherein the second cell and the fourth cell are coupled to a second bottom electrode,
wherein each cell of the plurality of cells comprises a resistive switching material stack comprising a resistive switching material having crystal defect regions and a non-linear switching element material,
wherein each cell is characterized by a first first-polarity voltage associated with the resistive switching material switching from a non-conductive state to a conductive state and a first second-polarity voltage associated with the resistive switching material switching from the conductive state to the non-conductive state,
wherein each cell is characterized by a second first-polarity voltage and a second second-polarity voltage associated with the non-linear switching element material switching from a second non-conductive state to a second conductive state,
wherein the second first-polarity voltage is less than the first first-polarity voltage,
wherein the first second-polarity voltage is less than the second second-polarity voltage,
wherein the program voltage is greater than or equal to the first first-polarity voltage, and
wherein applying the program voltage to the memory comprises applying the program voltage to the second top electrode;
grounding the second bottom electrode;
applying a first bias to the first top electrode and applying a second bias to the first bottom electrode;
causing a non-linear switching element material of the fourth cell to enter the conductive state and causing a resistive switching material of the fourth cell to enter the conductive state,
maintaining non-linear switching element materials of the first cell, the second cell, and the third cell in the non-conductive state in response to the applying the program voltage, grounding the second bottom electrode, the applying the first bias and the applying the second bias; and
removing the program voltage from the second top electrode, whereby the non-linear switching element material of the fourth cell returns to the non-conductive state, and wherein the resistive switching material of the fourth cell remains in the conductive state.
26. The method of claim 25
wherein applying the program voltage to the second top electrode while grounding the second bottom electrode causes metal particles from the second top electrode to diffuse into crystal defect regions of the resistive switching material of the fourth cell; and
wherein after removing the program voltage from the second top electrode, the metal particles from the second top electrode remain trapped in the crystal defect regions of the resistive switching material of the fourth cell.
27. The method of claim 25 wherein while applying the program voltage to the second top electrode while grounding the second bottom electrode, a voltage across the second cell is maintained at less than the second first-polarity voltage.
28. The method of claim 25
wherein the first and second first-polarity voltages are positive; and
wherein the first and second second-polarity voltage are negative.
29. The method of claim 28 wherein
applying the first bias to the first top electrode comprises applying a first bias voltage less than the second first-polarity voltage to the first top electrode; and
wherein a voltage across the second cell in response to the applying the first bias voltage is less than the second first-polarity voltage.
30. The method of claim 29
wherein applying the second bias to the first bottom electrode comprises applying a second bias voltage to the first bottom electrode;
wherein a voltage difference between the program voltage and the second bias voltage is less than the second first-polarity voltage; and
wherein a voltage across the third cell is less than the second first-polarity voltage.
31. The method of claim 30
wherein a voltage across the first cell comprises a third second-polarity voltage; and
wherein the second second-polarity voltage is less than the third second-polarity voltage.
32. The method of claim 25 wherein a resistance ratio between the second conductive state to the second non-conductive state of the non-linear switching element material is within a range of about 1,000 to about 10,000.
33. The method of claim 25 further comprising:
applying an erase voltage to the second top electrode;
further grounding the second bottom electrode;
further biasing the first top electrode;
further biasing the first bottom electrode to thereby cause the non-linear switching element material of the fourth cell to enter the conductive state and cause the resistive switching material of the fourth cell to enter the non-conductive state, while maintaining non-linear switching element materials of the first cell, the second cell, and the third cell in the non-conductive state; and
removing the erase voltage from the second top electrode, whereby the non-linear switching element material of the fourth cell returns to the non-conductive state, and wherein the resistive switching material of the fourth cell remains in the non-conductive state.
34. The method of claim 33, wherein:
the further biasing the first top electrode comprises applying a first bias voltage less than the second first-polarity voltage to the first top electrode; and
a voltage across the second cell in response to the applying the first bias voltage is greater than the second second-polarity voltage and less than the second first-polarity voltage.
US14612025 2010-11-04 2015-02-02 Switching device having a non-linear element Active USRE46335E1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US41003510 true 2010-11-04 2010-11-04
US13149757 US8502185B2 (en) 2011-05-31 2011-05-31 Switching device having a non-linear element
US13290024 US8467227B1 (en) 2010-11-04 2011-11-04 Hetero resistive switching material layer in RRAM device and method
US201261712171 true 2012-10-10 2012-10-10
US201361786100 true 2013-03-14 2013-03-14
US13921157 US8767441B2 (en) 2010-11-04 2013-06-18 Switching device having a non-linear element
US14612025 USRE46335E1 (en) 2010-11-04 2015-02-02 Switching device having a non-linear element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14612025 USRE46335E1 (en) 2010-11-04 2015-02-02 Switching device having a non-linear element

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US13921157 Reissue US8767441B2 (en) 2010-11-04 2013-06-18 Switching device having a non-linear element

Publications (1)

Publication Number Publication Date
USRE46335E1 true USRE46335E1 (en) 2017-03-07

Family

ID=58161671

Family Applications (1)

Application Number Title Priority Date Filing Date
US14612025 Active USRE46335E1 (en) 2010-11-04 2015-02-02 Switching device having a non-linear element

Country Status (1)

Country Link
US (1) USRE46335E1 (en)

Citations (423)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US680652A (en) 1897-11-08 1901-08-13 Leonard L Elden Circuit-breaker.
US4433468A (en) 1980-03-26 1984-02-28 Nippon Electric Co., Ltd. Method for making semiconductor device having improved thermal stress characteristics
US4684972A (en) 1981-08-07 1987-08-04 The British Petroleum Company, P.L.C. Non-volatile amorphous semiconductor memory device utilizing a forming voltage
US4741601A (en) 1984-10-08 1988-05-03 Nec Corporation Non-linear device for driving liquid crystal display
US4994866A (en) 1988-01-07 1991-02-19 Fujitsu Limited Complementary semiconductor device
US5139911A (en) 1989-01-04 1992-08-18 Fuji Xerox Co., Ltd. Electrophotographic photoreceptor with two part surface layer
US5242855A (en) 1991-09-30 1993-09-07 Nec Corporation Method of fabricating a polycrystalline silicon film having a reduced resistivity
US5278085A (en) 1992-08-11 1994-01-11 Micron Semiconductor, Inc. Single mask process for forming both n-type and p-type gates in a polycrystalline silicon layer during the formation of a semiconductor device
US5315131A (en) 1990-11-22 1994-05-24 Matsushita Electric Industrial Co., Ltd. Electrically reprogrammable nonvolatile memory device
US5335219A (en) 1991-01-18 1994-08-02 Ovshinsky Stanford R Homogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements
US5360981A (en) 1989-05-11 1994-11-01 British Telecommunications Public Limited Company Amorphous silicon memory
US5457649A (en) 1994-08-26 1995-10-10 Microchip Technology, Inc. Semiconductor memory device and write-once, read-only semiconductor memory array using amorphous-silicon and method therefor
US5499208A (en) 1994-09-12 1996-03-12 At&T Corp. Integrated circuit memory device
US5538564A (en) 1994-03-18 1996-07-23 Regents Of The University Of California Three dimensional amorphous silicon/microcrystalline silicon solar cells
US5541869A (en) 1991-10-22 1996-07-30 British Telecommunications, Plc Resistive memory element
US5594363A (en) 1995-04-07 1997-01-14 Zycad Corporation Logic cell and routing architecture in a field programmable gate array
US5596214A (en) 1994-05-30 1997-01-21 Nec Corporation Non-volatile semiconductor memory device having a metal-insulator-semiconductor gate structure and method for fabricating the same
US5614756A (en) 1990-04-12 1997-03-25 Actel Corporation Metal-to-metal antifuse with conductive
US5627451A (en) 1993-04-28 1997-05-06 Fujitsu Limited Control method and control apparatus for secondary battery charging in constant current charging method
US5645628A (en) 1994-07-14 1997-07-08 Matsushita Electric Industrial Co., Ltd. Electroless plating bath used for forming a wiring of a semiconductor device, and method of forming a wiring of a semiconductor device
US5673223A (en) 1995-06-09 1997-09-30 Samsung Electronics Co., Ltd. Nonvolatile semiconductor memory device with multiple word line voltage generators
US5707487A (en) 1991-01-22 1998-01-13 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5751012A (en) 1995-06-07 1998-05-12 Micron Technology, Inc. Polysilicon pillar diode for use in a non-volatile memory cell
US5840608A (en) 1996-11-22 1998-11-24 United Microelectronics Corporation High density ROM and a method of making the same
US5923587A (en) 1996-09-21 1999-07-13 Samsung Electronics, Co., Ltd. Multi-bit memory cell array of a non-volatile semiconductor memory device and method for driving the same
US5970332A (en) 1995-03-28 1999-10-19 U.S. Philips Corporation Method of manufacturing a semiconductor device with a BiCMOS circuit
US5973335A (en) 1994-12-22 1999-10-26 U.S. Philips Corporation Semiconductor memory devices with amorphous silicon alloy
US5998244A (en) 1996-08-22 1999-12-07 Micron Technology, Inc. Memory cell incorporating a chalcogenide element and method of making same
US6002268A (en) 1993-01-08 1999-12-14 Dynachip Corporation FPGA with conductors segmented by active repeaters
US6037204A (en) 1998-08-07 2000-03-14 Taiwan Semiconductor Manufacturing Company Silicon and arsenic double implanted pre-amorphization process for salicide technology
US6122318A (en) 1996-10-31 2000-09-19 Kabushiki Kaisha Toshiba Video encoding apparatus and video decoding apparatus
US6128214A (en) 1999-03-29 2000-10-03 Hewlett-Packard Molecular wire crossbar memory
US6143642A (en) 1997-12-22 2000-11-07 Vlsi Technology, Inc. Programmable semiconductor structures and methods for making the same
US6180998B1 (en) 1998-03-30 2001-01-30 Lsi Logic Corporation DRAM with built-in noise protection
US6181587B1 (en) 1999-11-24 2001-01-30 Mitsubishi Denki Kabushiki Kaisha Analog signal detecting circuit, and AC side current detector of semiconductor power conversion device
US6181597B1 (en) 1999-02-04 2001-01-30 Tower Semiconductor Ltd. EEPROM array using 2-bit non-volatile memory cells with serial read operations
EP1096465A2 (en) 1999-10-26 2001-05-02 Sel Semiconductor Energy Laboratory Co., Ltd. Gradation control of an electro-optical display device
US6259116B1 (en) 1997-10-22 2001-07-10 U.S. Philips Corporation Multiple memory element semiconductor memory devices
US6288435B1 (en) 1999-12-28 2001-09-11 Xerox Corporation Continuous amorphous silicon layer sensors using doped poly-silicon back contact
US6291836B1 (en) 1996-06-05 2001-09-18 U. S. Philips Corporation Method of operating a programmable, non-volatile memory device
US20020048940A1 (en) 1998-09-03 2002-04-25 Garo J. Derderian Chemical vapor deposition for smooth metal films
US6436818B1 (en) 1997-02-19 2002-08-20 Micron Technology, Inc. Semiconductor structure having a doped conductive layer
US6436765B1 (en) 2001-02-09 2002-08-20 United Microelectronics Corp. Method of fabricating a trenched flash memory cell
US6492694B2 (en) 1998-02-27 2002-12-10 Micron Technology, Inc. Highly conductive composite polysilicon gate for CMOS integrated circuits
US20030006440A1 (en) 2001-07-03 2003-01-09 Matsushita Electric Industrial Co., Ltd. Integrated circuit device including a layered superlattice material with an interface buffer layer
US20030036238A1 (en) 2000-12-22 2003-02-20 The Regents Of The University Of California Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction
US20030052330A1 (en) 2001-09-20 2003-03-20 Klein Rita J. Electro-and electroless plating of metal in the manufacture of PCRAM devices
US6552932B1 (en) 2001-09-21 2003-04-22 Sandisk Corporation Segmented metal bitlines
WO2003034498A1 (en) 2001-10-16 2003-04-24 Midwest Research Institute Stacked switchable element and diode combination
US20030141565A1 (en) 2002-01-28 2003-07-31 Fumihiko Hirose Diode
US20030174574A1 (en) 2002-03-12 2003-09-18 Perner Frederick A. Write pulse circuit for a magnetic memory
US6627530B2 (en) 2000-12-22 2003-09-30 Matrix Semiconductor, Inc. Patterning three dimensional structures
US20030194865A1 (en) 2002-04-10 2003-10-16 Gilton Terry L. Method of manufacture of programmable conductor memory
US20030206659A1 (en) 1998-09-08 2003-11-06 Canon Kabushiki Kaisha Image processing apparatus including an image data encoder having at least two scalability modes and method therefor
US20040026682A1 (en) 2002-06-17 2004-02-12 Hai Jiang Nano-dot memory and fabricating same
US20040036124A1 (en) 2001-09-25 2004-02-26 Matrix Semiconductor, Inc. Inverted staggered thin film transistor with salicided source/drain structures and method of making same
US6724186B2 (en) 2000-06-27 2004-04-20 Brown & Sharpe Tesa Sa Measuring device with magneto-resistive electrodes, and measuring method
US6731535B1 (en) 2002-12-10 2004-05-04 Renesas Technology Corp. Nonvolatile semiconductor memory device
US6740921B2 (en) 2002-02-01 2004-05-25 Hitachi, Ltd. Semiconductor memory cell and method of forming same
US6762474B1 (en) 1998-06-10 2004-07-13 Agere Systems Inc. Method and apparatus for temperature compensation of read-only memory
US6768157B2 (en) 2001-08-13 2004-07-27 Advanced Micro Devices, Inc. Memory device
US20040159835A1 (en) 2001-08-13 2004-08-19 Krieger Juri Heinrich Memory device
US20040170040A1 (en) 2002-08-02 2004-09-02 Unity Semiconductor Corporation Rewritable memory with non-linear memory element
US20040192006A1 (en) 2002-02-20 2004-09-30 Campbell Kristy A. Layered resistance variable memory device and method of fabrication
US20040194340A1 (en) 1998-10-14 2004-10-07 Tokyo Electron Limited Method and apparatus for surface treatment
US20040202041A1 (en) 2003-04-11 2004-10-14 Sharp Kabushiki Kaisha Memory cell, memory device and manufacturing method of memory cell
US6816405B1 (en) 2003-06-02 2004-11-09 International Business Machines Corporation Segmented word line architecture for cross point magnetic random access memory
US6821879B2 (en) 2002-10-30 2004-11-23 Xerox Corporation Copper interconnect by immersion/electroless plating in dual damascene process
US6838720B2 (en) 2001-08-13 2005-01-04 Advanced Micro Devices, Inc. Memory device with active passive layers
US6848012B2 (en) 2002-09-27 2005-01-25 Broadcom Corporation Method and system for an adaptive multimode media queue
US20050019699A1 (en) 2001-02-08 2005-01-27 Moore John T. Non-volatile resistance variable device
US20050020510A1 (en) 2002-08-29 2005-01-27 Benedict Dale L. D-mannose contraceptives
US6849891B1 (en) 2003-12-08 2005-02-01 Sharp Laboratories Of America, Inc. RRAM memory cell electrodes
US20050029587A1 (en) 1995-06-07 2005-02-10 Harshfield Steven T. Method and apparatus for forming an integrated circuit electrode having a reduced contact area
US6858481B2 (en) 2001-08-13 2005-02-22 Advanced Micro Devices, Inc. Memory device with active and passive layers
US20050041498A1 (en) 2003-06-16 2005-02-24 Claudio Resta Writing circuit for a phase change memory device
US6864127B2 (en) 1997-04-25 2005-03-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US20050052915A1 (en) 2002-12-19 2005-03-10 Matrix Semiconductor, Inc. Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states
US6867618B2 (en) 2001-11-19 2005-03-15 Broadcom Corporation Voltage mode differential driver and method
US20050062045A1 (en) 2002-10-02 2005-03-24 Arup Bhattacharyya Processes of forming stacked resistor constructions
US20050073881A1 (en) 2003-10-06 2005-04-07 Tran Lung The Magnetic memory device including groups of series-connected memory elements
US6881994B2 (en) 2000-08-14 2005-04-19 Matrix Semiconductor, Inc. Monolithic three dimensional array of charge storage devices containing a planarized surface
US20050101081A1 (en) 2003-09-30 2005-05-12 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and a fabrication method thereof
US6897519B1 (en) 2003-02-26 2005-05-24 Dialog Semiconductor Tunneling floating gate APS pixel
US6927430B2 (en) 2001-06-28 2005-08-09 Sharp Laboratories Of America, Inc. Shared bit line cross-point memory array incorporating P/N junctions
US20050175099A1 (en) 2004-02-06 2005-08-11 Nokia Corporation Transcoder and associated system, method and computer program product for low-complexity reduced resolution transcoding
US6939787B2 (en) 1999-12-28 2005-09-06 Fujitsu Limited Method for fabricating semiconductor device having gate electrode with polymetal structure of polycrystalline silicon film and metal film
US6946719B2 (en) 2003-12-03 2005-09-20 Matrix Semiconductor, Inc Semiconductor device including junction diode contacting contact-antifuse unit comprising silicide
WO2005124787A2 (en) 2004-06-16 2005-12-29 Koninklijke Philips Electronics N.V. Electrical device having a programmable resistor connected in series to a punch-through diode and method of manufacturing therefor
US20060017488A1 (en) 2004-07-21 2006-01-26 Sharp Laboratories Of America, Inc. Mono-polarity switchable PCMO resistor trimmer
US20060054950A1 (en) 2004-09-10 2006-03-16 In-Gyu Baek Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer and methods of manufacturing the same
US7020006B2 (en) 2002-08-02 2006-03-28 Unity Semiconductor Corporation Discharge of conductive array lines in fast memory
US7023093B2 (en) 2002-10-24 2006-04-04 International Business Machines Corporation Very low effective dielectric constant interconnect Structures and methods for fabricating the same
US20060134837A1 (en) 1998-11-16 2006-06-22 Vivek Subramanian Vertically stacked field programmable nonvolatile memory and method of fabrication
US20060154417A1 (en) 2005-01-11 2006-07-13 Sharp Kabushiki Kaisha Semiconductor memory device
US7087454B2 (en) 2002-08-29 2006-08-08 Micron Technology, Inc. Fabrication of single polarity programmable resistance structure
US7102150B2 (en) 2001-05-11 2006-09-05 Harshfield Steven T PCRAM memory cell and method of making same
US20060215445A1 (en) 2005-03-28 2006-09-28 In-Gyu Baek Magneto-resistive memory cells and devices having asymmetrical contacts and methods of fabrication therefor
US7122853B1 (en) 2004-08-17 2006-10-17 Fasl, Inc. Method to improve yield and simplify operation of polymer memory cells
US20060231910A1 (en) 2005-04-15 2006-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming silicide and semiconductor device formed thereby
US20060246606A1 (en) 2005-05-02 2006-11-02 Sharp Laboratories Of America, Inc. Self-aligned cross point resistor memory array
US20060279979A1 (en) 2005-06-13 2006-12-14 Tyler Lowrey Method of reading phase-change memory elements
US20060281244A1 (en) 2005-06-08 2006-12-14 Masayuki Ichige Nonvolatile semiconductor memory device and method of manufacturing the same
US20060286762A1 (en) 2005-06-15 2006-12-21 Winbond Electronics Corp. Method for non-volatile memory fabrication
US20070008773A1 (en) 2005-07-11 2007-01-11 Matrix Semiconductor, Inc. Nonvolatile memory cell comprising switchable resistor and transistor
US20070015348A1 (en) 2005-07-18 2007-01-18 Sharp Laboratories Of America, Inc. Crosspoint resistor memory device with back-to-back Schottky diodes
US7167387B2 (en) 2003-10-23 2007-01-23 Matsushita Electric Industrial Co., Ltd. Variable resistance element, method of manufacturing the element, memory containing the element, and method of driving the memory
US20070025144A1 (en) 2005-07-29 2007-02-01 International Business Machines Corporation Write operations for phase-change-material memory
US20070035990A1 (en) 2005-08-15 2007-02-15 Micron Technology, Inc. Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
US20070042612A1 (en) 2005-08-22 2007-02-22 Hirotaka Nishino Method for manufacturing semiconductor device
US20070045615A1 (en) 2005-08-31 2007-03-01 Samsung Electronics Co., Ltd. Non-volatile organic resistance random access memory device and method of manufacturing the same
US7187577B1 (en) 2005-11-23 2007-03-06 Grandis, Inc. Method and system for providing current balanced writing for memory cells and magnetic devices
US20070069119A1 (en) 2005-09-23 2007-03-29 Massachusetts Institute Of Technology Optical trapping with a semiconductor
US20070087508A1 (en) 2003-12-03 2007-04-19 Herner S B Method for making a p-i-n diode crystallized adjacent to a silicide in series with a dielectric antifuse
US20070090425A1 (en) 2005-09-28 2007-04-26 Matrix Semiconductor, Inc. Memory cell comprising switchable semiconductor memory element with trimmable resistance
US20070091685A1 (en) 2004-01-27 2007-04-26 Guterman Daniel C Efficient verification for coarse/fine programming of non-volatile memory
US20070105284A1 (en) 2003-12-03 2007-05-10 Herner S B Method for forming a memory cell comprising a semiconductor junction diode crystallized adjacent to a silicide
US20070105390A1 (en) 2005-11-09 2007-05-10 Oh Travis B Oxygen depleted etching process
US7221599B1 (en) 2004-11-01 2007-05-22 Spansion, Llc Polymer memory cell operation
US20070133250A1 (en) 2005-12-08 2007-06-14 Juhan Kim Phase change memory including diode access device
US20070133270A1 (en) 2005-09-05 2007-06-14 Samsung Electronics Co., Ltd. Phase-change random access memory device and method of operating the same
US7238607B2 (en) 2002-12-19 2007-07-03 Sandisk 3D Llc Method to minimize formation of recess at surface planarized by chemical mechanical planarization
US7238994B2 (en) 2005-06-17 2007-07-03 Macronix International Co., Ltd. Thin film plate phase change ram circuit and manufacturing method
US20070159869A1 (en) 2006-01-09 2007-07-12 Samsung Electronics Co., Ltd. Multi-state resistive memory element, multi-bit resistive memory cell, operating method thereof, and data processing system using the memory element
US20070159876A1 (en) 2006-01-06 2007-07-12 Tadahiko Sugibayashi Magnetic ramdom access memory and operating method of the same
US20070171698A1 (en) 2005-12-23 2007-07-26 Heinz Hoenigschmid Memory circuit including a resistive memory element and method for operating such a memory circuit
US7251152B2 (en) 2004-08-26 2007-07-31 Infineon Technologies Ag Memory circuit having memory cells which have a resistance memory element
US20070205510A1 (en) 2006-03-03 2007-09-06 Lavoie Adrien R Noble metal barrier layers
US7274587B2 (en) 2004-11-10 2007-09-25 Kabushiki Kaisha Toshiba Semiconductor memory element and semiconductor memory device
US20070228414A1 (en) 2006-03-31 2007-10-04 Sandisk 3D, Llc Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride
JP2007281208A (en) 2006-04-07 2007-10-25 Matsushita Electric Ind Co Ltd Multilayer resistance variable element array, resistance variable device, multilayer nonvolatile storage element array, and nonvolatile storage device
US7289353B2 (en) 2004-08-17 2007-10-30 Spansion, Llc Systems and methods for adjusting programming thresholds of polymer memory cells
US20070284575A1 (en) 2005-07-18 2007-12-13 Sharp Laboratories Of America, Inc. Metal/semiconductor/metal current limiter
JP2007328857A (en) 2006-06-07 2007-12-20 Sony Corp Storage device
US20070290186A1 (en) 2006-05-04 2007-12-20 El Mostafa Bourim Non-volatile variable resistance memory device and method of fabricating the same
US20070297501A1 (en) 2006-06-08 2007-12-27 Via Technologies, Inc. Decoding Systems and Methods in Computational Core of Programmable Graphics Processing Unit
US20070295950A1 (en) 2006-06-27 2007-12-27 Samsung Electronics Co., Ltd. Variable resistance random access memory device and a method of fabricating the same
US20080002481A1 (en) 2002-12-20 2008-01-03 Dietmar Gogl Integrated Circuit, Method of Operating an Integrated Circuit, Method of Manufacturing an Integrated Circuit, Memory Module, Stackable Memory Module
US20080007987A1 (en) 2003-09-22 2008-01-10 Daisaburo Takashima Semiconductor integrated circuit device
US20080006907A1 (en) 2006-07-06 2008-01-10 Samsung Electronics Co., Ltd Non-volatile memory device including a variable resistance material
US20080019163A1 (en) 2006-07-21 2008-01-24 Heinz Hoenigschmid Method and memory circuit for operating a resistive memory cell
US7324363B2 (en) 2005-12-12 2008-01-29 Synopsys, Inc. SPICE optimized for arrays
US20080043521A1 (en) 2006-08-21 2008-02-21 Corvin Liaw Method of determining a memory state of a resistive memory cell and device measuring the memory state of a resistive memory cell
US20080048164A1 (en) 2006-07-11 2008-02-28 Matsushita Electric Industrial Co., Ltd. Electro-resistance element, method of manufacturing the same and electro-resistance memory using the same
US7345907B2 (en) 2005-07-11 2008-03-18 Sandisk 3D Llc Apparatus and method for reading an array of nonvolatile memory cells including switchable resistor memory elements
US20080083918A1 (en) 2004-07-22 2008-04-10 Sony Corporation Storage Element
US20080089110A1 (en) 2006-10-16 2008-04-17 Warren Robinett Crossbar-memory systems and methods for writing to and reading from crossbar memory junctions of crossbar-memory systems
US20080090337A1 (en) 2006-10-03 2008-04-17 Williams R Stanley Electrically actuated switch
US7365411B2 (en) 2004-08-12 2008-04-29 Micron Technology, Inc. Resistance variable memory with temperature tolerant materials
CN101170132A (en) 2006-10-27 2008-04-30 奇梦达股份公司 Modifiable gate stack memory element
US20080106925A1 (en) 2006-11-08 2008-05-08 Symetrix Corporation Correlated electron memory
US20080106926A1 (en) 2006-11-08 2008-05-08 Symetrix Corporation Non-volatile resistance switching memories and methods of making same
JP2008147343A (en) 2006-12-08 2008-06-26 Sharp Corp Nonvolatile semiconductor memory
US20080165571A1 (en) 2007-01-09 2008-07-10 Macronix International Co., Ltd. Method, Apparatus and Computer Program Product for Read Before Programming Process on Multiple Programmable Resistive Memory Cell
US7405418B2 (en) 2004-02-17 2008-07-29 Infineon Technologies Ag Memory device electrode with a surface structure
US20080185567A1 (en) 2007-02-05 2008-08-07 Nitin Kumar Methods for forming resistive switching memory elements
US20080192531A1 (en) 2005-10-19 2008-08-14 Fujitsu Limited Method of writing into semiconductor memory device
US20080198934A1 (en) 2007-02-20 2008-08-21 Edward Hong Motion refinement engine for use in video encoding in accordance with a plurality of sub-pixel resolutions and methods for use therewith
US20080206931A1 (en) 2002-07-26 2008-08-28 Laurent Breuil Nonvolatile memory element and production method thereof and storage memory arrangement
US20080205179A1 (en) 2007-02-28 2008-08-28 Qimonda Ag Integrated circuit having a memory array
US20080220601A1 (en) 2007-03-05 2008-09-11 Nitin Kumar Methods for forming nonvolatile memory elements with resistive-switching metal oxides
US20080232160A1 (en) 2007-02-27 2008-09-25 International Business Machines Corporation Rectifying element for a crosspoint based memory array architecture
US20080278990A1 (en) 2007-05-09 2008-11-13 Pragati Kumar Resistive-switching nonvolatile memory elements
US20080278988A1 (en) 2007-05-09 2008-11-13 Klaus Ufert Resistive switching element
US20080301497A1 (en) 2007-06-04 2008-12-04 Silicon Motion, Inc. Testing Apparatus, System, and Method for Testing at Least One Device with a Connection Interface
US20080304312A1 (en) 2007-06-11 2008-12-11 Macronix International Co., Ltd. Resistance memory with tungsten compound and manufacturing
US20080311722A1 (en) 2007-06-15 2008-12-18 Sandisk 3D Llc Method for forming polycrystalline thin film bipolar transistors
US20090001343A1 (en) 2007-06-29 2009-01-01 April Schricker Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same
US20090001345A1 (en) 2007-06-29 2009-01-01 April Schricker Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same
US20090003717A1 (en) 2007-06-28 2009-01-01 Mitsubishi Electric Corporation Image encoding device, image decoding device, image encoding method and image decoding method
US7474000B2 (en) 2003-12-05 2009-01-06 Sandisk 3D Llc High density contact to relaxed geometry layers
WO2009005699A1 (en) 2007-06-29 2009-01-08 Sandisk 3D, Llc Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
US20090014703A1 (en) 2007-02-07 2009-01-15 Tsuneo Inaba Semiconductor memory device
US20090014707A1 (en) 2006-10-20 2009-01-15 Wei Lu Non-volatile solid state resistive switching devices
US20090052226A1 (en) 2007-08-24 2009-02-26 Samsung Electronics Co., Ltd Resistive random access memory device
JP2009043873A (en) 2007-08-08 2009-02-26 Sony Corp Storage element and storage device
US7499355B2 (en) 2006-07-31 2009-03-03 Sandisk 3D Llc High bandwidth one time field-programmable memory
US7515454B2 (en) 2006-08-02 2009-04-07 Infineon Technologies Ag CBRAM cell and CBRAM array, and method of operating thereof
US20090091981A1 (en) 2007-10-08 2009-04-09 Samsung Electronics Co., Ltd. Nonvolatile memory device with multiple page regions, and methods of reading and precharging the same
US20090095951A1 (en) 2007-10-12 2009-04-16 Ovonyx, Inc. Memory Device With Low Reset Current
US7521705B2 (en) 2005-08-15 2009-04-21 Micron Technology, Inc. Reproducible resistance variable insulating memory devices having a shaped bottom electrode
US20090109728A1 (en) 2007-10-17 2009-04-30 Kabushiki Kaisha Toshiba Resistance change memory device
US20090122591A1 (en) 2007-11-14 2009-05-14 Qimonda North America Corporation Sense Amplifier Biasing Method and Apparatus
US7534625B2 (en) 2004-09-24 2009-05-19 Karpov Ilya V Phase change memory with damascene memory element
KR20090051206A (en) 2006-09-29 2009-05-21 후지쯔 마이크로일렉트로닉스 가부시키가이샤 Nonvolatile semiconductor storage apparatus, reading method thereof, writing method thereof and erasing method thereof
US20090134432A1 (en) 2007-11-22 2009-05-28 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
US7541252B2 (en) 2006-11-09 2009-06-02 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device including a self-aligned cell diode
US20090141567A1 (en) 2007-11-09 2009-06-04 Kwang Jin Lee Semiconductor device having memory array, method of writing, and systems associated therewith
US20090152737A1 (en) 2000-07-14 2009-06-18 Micron Technology, Inc. Memory devices having contact features
US7550380B2 (en) 2004-11-03 2009-06-23 Micron Technology, Inc. Electroless plating of metal caps for chalcogenide-based memory devices
US20090168486A1 (en) 2007-12-27 2009-07-02 Sandisk 3D Llc Large capacity one-time programmable memory cell using metal oxides
US7561461B2 (en) 2007-02-28 2009-07-14 Panasonic Corporation Non-volatile semiconductor memory device
US7566643B2 (en) 2007-07-23 2009-07-28 Ovonyx, Inc. Liquid phase deposition of contacts in programmable resistance and switching devices
CN101501850A (en) 2006-10-16 2009-08-05 松下电器产业株式会社 Non-volatile storage device and method for manufacturing the same
US20090227067A1 (en) 2008-03-10 2009-09-10 Pragati Kumar Methods for Forming Resistive Switching Memory Elements by Heating Deposited Layers
US20090231910A1 (en) * 2008-03-11 2009-09-17 Micron Technology, Inc. Non-volatile memory with resistive access component
US20090231905A1 (en) 2006-11-30 2009-09-17 Fujitsu Limited Nonvolatile semiconductor memory device, and writing method, reading method and erasing method of nonvolatile semiconductor memory device
US20090250787A1 (en) 2008-04-07 2009-10-08 Toshie Kutsunai Semiconductor storage device and manufacturing method of the same
US20090251941A1 (en) 2008-04-03 2009-10-08 Semiconductor Energy Labortory Co., Ltd. Semiconductor Device
US20090256130A1 (en) 2008-04-11 2009-10-15 Sandisk 3D Llc Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element, and methods of forming the same
US20090257265A1 (en) 2008-04-11 2009-10-15 Sandisk 3D Llc Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same
US7606059B2 (en) 2003-03-18 2009-10-20 Kabushiki Kaisha Toshiba Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array
US20090267047A1 (en) 2008-04-28 2009-10-29 Hitachi, Ltd. Semiconductor memory device and manufacturing method thereof
US20090268513A1 (en) 2008-04-29 2009-10-29 Luca De Ambroggi Memory device with different types of phase change memory
US20090272962A1 (en) 2008-05-01 2009-11-05 Pragati Kumar Reduction of forming voltage in semiconductor devices
US7615439B1 (en) 2008-09-29 2009-11-10 Sandisk Corporation Damascene process for carbon memory element with MIIM diode
US20090283737A1 (en) 2008-05-19 2009-11-19 Masahiro Kiyotoshi Nonvolatile storage device and method for manufacturing same
US20090298224A1 (en) 2002-12-13 2009-12-03 Lowrey Tyler A Memory and Access Device and Method Therefor
US20090321706A1 (en) 2008-06-25 2009-12-31 Qimonda Ag Resistive Memory Devices with Improved Resistive Changing Elements
US20090321789A1 (en) 2008-06-30 2009-12-31 Sandisk 3D Llc Triangle two dimensional complementary patterning of pillars
US20100007937A1 (en) 2006-11-09 2010-01-14 Sage Electrochromics, Inc. Method of making an ion-switching device without a separate lithiation step
US20100012914A1 (en) 2008-07-18 2010-01-21 Sandisk 3D Llc Carbon-based resistivity-switching materials and methods of forming the same
CN101636792A (en) 2007-03-13 2010-01-27 松下电器产业株式会社 Resistance-variable storage device
US20100019221A1 (en) 2008-07-22 2010-01-28 Macronix International Co., Ltd. Fully self-aligned pore-type memory cell having diode access device
US20100019310A1 (en) 2008-07-25 2010-01-28 Kabushiki Kaisha Toshiba Semiconductor memory device
US20100025675A1 (en) 2008-07-31 2010-02-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US20100032638A1 (en) 2008-08-07 2010-02-11 Sandisk 3D Llc Memory cell that includes a carbon-based memory element and methods of forming the same
US20100034518A1 (en) 2003-11-10 2010-02-11 Panasonic Corporation Integrated circuit for use in a playback apparatus
US20100032637A1 (en) 2008-08-06 2010-02-11 Hitachi, Ltd. Nonvolatile memory device and method of manufacturing the same
US20100038791A1 (en) 2008-08-12 2010-02-18 Industrial Technology Research Institute Resistive random access memory and method for fabricating the same
US20100039136A1 (en) 2008-08-15 2010-02-18 Qualcomm Incorporated Gate Level Reconfigurable Magnetic Logic
US7667442B2 (en) 2005-03-16 2010-02-23 Ricoh Company, Ltd. Constant voltage power supply circuit and method of testing the same
US20100044798A1 (en) 2008-06-09 2010-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor device and a method of manufacturing the same
US20100044708A1 (en) 2008-08-19 2010-02-25 Chunghwa Picture Tubes, Ltd. Thin film transistor, pixel structure and fabrication methods thereof
US20100046622A1 (en) 2006-12-14 2010-02-25 Thomson Licensing Method and apparatus for encoding and/or decoding bit depth scalable video data using adaptive enhancement layer residual prediction
WO2010026654A1 (en) 2008-09-05 2010-03-11 株式会社 東芝 Memory device
US20100067279A1 (en) 2006-09-19 2010-03-18 Byung-Gil Choi Semiconductor memory device using variable resistor
US20100067282A1 (en) 2008-09-18 2010-03-18 Seagate Technology Llc Memory array with read reference voltage cells
US7692959B2 (en) 2008-04-22 2010-04-06 International Business Machines Corporation Multilayer storage class memory using externally heated phase change material
US20100085798A1 (en) 2008-10-08 2010-04-08 The Regents Of The University Of Michigan Silicon-based nanoscale resistive device with adjustable resistance
US20100084625A1 (en) 2008-10-02 2010-04-08 Guy Wicker Memory Device
US20100085822A1 (en) 2008-10-06 2010-04-08 Tianhong Yan Continuous programming of non-volatile memory
US20100090192A1 (en) 2006-08-31 2010-04-15 Nxp, B.V. Method for controlled formation of the resistive switching material in a resistive switching device and device obtained thereof
US7704788B2 (en) 2007-04-06 2010-04-27 Samsung Electronics Co., Ltd. Methods of fabricating multi-bit phase-change memory devices and devices formed thereby
US20100102290A1 (en) 2008-10-20 2010-04-29 The Regents Of The University Of Michigan Silicon based nanoscale crossbar memory
US20100101290A1 (en) 2008-10-24 2010-04-29 Antonio Bertolotto Method for the production of an agent for treatment of agricultural soils
US20100118587A1 (en) 2008-11-12 2010-05-13 Seagate Technology Llc Resistive sense memory array with partial block update capability
US7719001B2 (en) 2006-06-28 2010-05-18 Semiconductor Energy Laboratory Co., Ltd Semiconductor device with metal oxides and an organic compound
US7728318B2 (en) 2006-11-16 2010-06-01 Sandisk Corporation Nonvolatile phase change memory cell having a reduced contact area
US7729158B2 (en) 2003-04-03 2010-06-01 Kabushiki Kaisha Toshiba Resistance change memory device
US20100140614A1 (en) 2008-12-09 2010-06-10 Hitachi, Ltd. Oxide semiconductor device and method of manufacturing the same and active matrix substrate
US20100157659A1 (en) 2008-12-22 2010-06-24 Unity Semiconductor Corporation Digital potentiometer using third dimensional memory
US20100157656A1 (en) 2008-12-19 2010-06-24 Kabushiki Kaisha Toshiba Resistance change memory
US20100157710A1 (en) 2008-12-19 2010-06-24 Unity Semiconductor Corporation Array Operation Using A Schottky Diode As a Non-Ohmic Isolation Device
US20100157651A1 (en) 2008-12-18 2010-06-24 Sandisk 3D Llc Method of programming a nonvolatile memory device containing a carbon storage material
US7746601B2 (en) 2004-03-03 2010-06-29 Kabushiki Kaisha Toshiba Magneto-resistance effect element with a surface contacting with a side face of electrode having a magnetization direction
US7746696B1 (en) 2008-03-04 2010-06-29 Xilinx, Inc. CMOS twin cell non-volatile random access memory
US20100163828A1 (en) 2008-12-30 2010-07-01 Industrial Technology Research Institute Phase change memory devices and methods for fabricating the same
US7749805B2 (en) 2005-03-10 2010-07-06 Qimonda Ag Method for manufacturing an integrated circuit including an electrolyte material layer
US20100171086A1 (en) 2009-01-07 2010-07-08 Macronix International Co., Ltd. Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method
US20100176368A1 (en) 2009-01-14 2010-07-15 Ko Nikka Method of manufacturing semiconductor memory device, and semiconductor memory device
US20100176367A1 (en) 2009-01-12 2010-07-15 Micron Technology, Inc. Memory cell having dielectric memory element
US20100182821A1 (en) 2003-12-26 2010-07-22 Panasonic Corporation Memory device, memory circuit and semiconductor integrated circuit having variable resistance
US7764536B2 (en) 2007-08-07 2010-07-27 Grandis, Inc. Method and system for providing a sense amplifier and drive circuit for spin transfer torque magnetic random access memory
US7772581B2 (en) 2006-09-11 2010-08-10 Macronix International Co., Ltd. Memory device having wide area phase change element and small electrode contact area
US20100203731A1 (en) 2009-02-09 2010-08-12 Bob Kong Formation of a Zinc Passivation Layer on Titanium or Titanium Alloys Used in Semiconductor Processing
US7776682B1 (en) 2005-04-20 2010-08-17 Spansion Llc Ordered porosity to direct memory element formation
US7786589B2 (en) 2006-12-06 2010-08-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing semiconductor device
US7786464B2 (en) 2007-11-20 2010-08-31 Infineon Technologies Ag Integrated circuit having dielectric layer including nanocrystals
US20100221868A1 (en) 2007-12-04 2010-09-02 Regino Sandoval Active Material Devices with Containment Layer
US20100219510A1 (en) 2008-06-30 2010-09-02 Sandisk 3D Llc Method for fabricating high density pillar structures by double patterning using positive photoresist
US7791060B2 (en) 2006-09-27 2010-09-07 Kabushiki Kaisha Toshiba Semiconductor memory device and method of controlling the same
US20100237314A1 (en) 2009-03-19 2010-09-23 Takayuki Tsukamoto Resistance change type memory
US20100243983A1 (en) 2009-03-31 2010-09-30 Tony Chiang Controlled localized defect paths for resistive memories
US20100258781A1 (en) 2009-04-10 2010-10-14 Prashant Phatak Resistive switching memory element including doped silicon electrode
US20100271885A1 (en) 2009-04-24 2010-10-28 Sandisk 3D Llc Reduced complexity array line drivers for 3D matrix arrays
US7824956B2 (en) 2007-06-29 2010-11-02 Sandisk 3D Llc Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
US20100277969A1 (en) 2008-10-31 2010-11-04 Seagate Technology Llc. Structures for resistive random access memory cells
US7829875B2 (en) 2006-03-31 2010-11-09 Sandisk 3D Llc Nonvolatile rewritable memory cell comprising a resistivity-switching oxide or nitride and an antifuse
US7835170B2 (en) 2005-05-09 2010-11-16 Nantero, Inc. Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks
US20100321095A1 (en) 2008-06-10 2010-12-23 Takumi Mikawa Semiconductor device, manufacturing method of semiconductor device, semiconductor chip and system
US7859884B2 (en) 2005-01-19 2010-12-28 Sandisk 3D Llc Structure and method for biasing phase change memory array for reliable writing
US7858468B2 (en) 2008-10-30 2010-12-28 Micron Technology, Inc. Memory devices and formation methods
US20110006275A1 (en) 2009-07-13 2011-01-13 Seagate Technology Llc Non-volatile resistive sense memory
US20110007551A1 (en) 2009-07-13 2011-01-13 Seagate Technology Llc Non-Volatile Memory Cell with Non-Ohmic Selection Layer
WO2011005266A1 (en) 2009-07-10 2011-01-13 Hewlett-Packard Development Company, L.P. Memristive junction with intrinsic rectifier
US7881097B2 (en) 2006-12-26 2011-02-01 Sony Corporation Storage element and memory
JP2011023645A (en) * 2009-07-17 2011-02-03 Sharp Corp Semiconductor storage element using nonvolatile variable-resistance element
US20110033967A1 (en) 2006-06-04 2011-02-10 Markus Lutz Methods for trapping charge in a microelectromechanical system and microelectromechanical system employing same
KR20110014248A (en) 2010-11-28 2011-02-10 손정삼 A driver to set up lighting slab at night throngh solar panel
US7897953B2 (en) 2008-01-16 2011-03-01 Micron Technology, Inc. Multi-level programmable PCRAM memory
US7898838B2 (en) 2008-10-31 2011-03-01 Seagate Technology Llc Resistive sense memory calibration for self-reference read method
US20110063888A1 (en) 2009-09-11 2011-03-17 Semiconductor Manufacturing International (Shanghai) Corporation Green Transistor for Resistive Random Access Memory and Method of Operating the Same
US20110066878A1 (en) 2009-09-17 2011-03-17 Kabushiki Kaisha Toshiba Non-volatile semiconductor storage device
US20110069533A1 (en) 2009-09-18 2011-03-24 Kurosawa Tomonori Resistance change memory and control method thereof
US20110068373A1 (en) 2009-09-24 2011-03-24 Kabushiki Kaisha Toshiba Semiconductor memory device
US7920412B2 (en) 2006-09-29 2011-04-05 Kabushiki Kaisha Toshiba Magnetic random access memory and method of manufacturing the same
US7924138B2 (en) 2007-03-01 2011-04-12 Fujitsu Limited Semiconductor device and manufacturing method of the same
US7927472B2 (en) 2002-03-25 2011-04-19 Ulvac, Inc. Optical film thickness controlling method, optical film thickness controlling apparatus, dielectric multilayer film manufacturing apparatus, and dielectric multilayer film manufactured using the same controlling apparatus or manufacturing apparatus
US20110089391A1 (en) 2009-10-20 2011-04-21 Andrei Mihnea Punch-through diode steering element
CN102077296A (en) 2009-06-08 2011-05-25 松下电器产业株式会社 Forming method for resistance-change non-volatile memory element, and resistance-change non-volatile memory device
US20110128779A1 (en) 2009-11-30 2011-06-02 Andrea Redaelli Memory including a selector switch on a variable resistance memory cell
US20110133149A1 (en) 2009-12-04 2011-06-09 Sonehara Takeshi Resistance change memory and manufacturing method thereof
US20110136327A1 (en) 2009-12-03 2011-06-09 Applied Materials, Inc. High mobility monolithic p-i-n diodes
US20110151277A1 (en) 2009-02-23 2011-06-23 Panasonic Corporation Information recording medium
US7968419B2 (en) 2005-07-18 2011-06-28 Sharp Laboratories Of America, Inc. Back-to-back metal/semiconductor/metal (MSM) Schottky diode
US20110155991A1 (en) 2009-12-29 2011-06-30 Industrial Technology Research Institute Resistive memory device and fabricating method thereof
US7984776B2 (en) 2007-03-30 2011-07-26 The Regents Of The University Of Michigan Energy storage and control system for a vehicle electrified drivetrain
US20110183525A1 (en) 2010-01-27 2011-07-28 International Business Machines Corporation Homogeneous Porous Low Dielectric Constant Materials
US20110193051A1 (en) 2010-02-08 2011-08-11 Samsung Electronics Co., Ltd. Resistance memory devices and methods of forming the same
US20110194329A1 (en) 2010-02-09 2011-08-11 Sony Corporation Memory component, memory device, and method of operating memory device
US20110198557A1 (en) 2008-02-07 2011-08-18 International Business Machines Corporation Method for fabrication of crystalline diodes for resistive memories
US8004882B2 (en) 2004-06-04 2011-08-23 Micron Technology, Inc. Spintronic devices with integrated transistors
US20110205782A1 (en) 2010-02-23 2011-08-25 Xiying Chen Costa Step soft program for reversible resistivity-switching elements
US20110205780A1 (en) 2010-02-19 2011-08-25 Shinichi Yasuda Semiconductor Integrated Circuit
US20110204312A1 (en) 2008-05-10 2011-08-25 Intermolecular, Inc. Confinement techniques for non-volatile resistive-switching memories
US20110212616A1 (en) 2010-02-26 2011-09-01 Robert Seidel Metallization system of a semiconductor device comprising rounded interconnects formed by hard mask rounding
US8018760B2 (en) 2006-12-28 2011-09-13 Panasonic Corporation Resistance variable element and resistance variable memory apparatus
US8021897B2 (en) 2009-02-19 2011-09-20 Micron Technology, Inc. Methods of fabricating a cross point memory array
US20110227028A1 (en) 2010-03-16 2011-09-22 Deepak Chandra Sekar Bottom electrodes for use with metal oxide resistivity switching layers
US8045364B2 (en) 2009-12-18 2011-10-25 Unity Semiconductor Corporation Non-volatile memory device ion barrier
WO2011133138A1 (en) 2010-04-19 2011-10-27 Hewlett-Packard Development Company, L.P. Nanoscale switching devices with partially oxidized electrodes
US8054674B2 (en) 2007-05-10 2011-11-08 Sharp Kabushiki Kaisha Variable resistive element, manufacturing method for same, and non-volatile semiconductor memory device
US8054679B2 (en) 2007-06-19 2011-11-08 Elpida Memory Inc. Phase change memory device
US20110284814A1 (en) 2010-05-24 2011-11-24 Guobiao Zhang Large Bit-Per-Cell Three-Dimensional Mask-Programmable Read-Only Memory
US8067815B2 (en) 2008-12-11 2011-11-29 Macronix International Co., Lt.d. Aluminum copper oxide based memory devices and methods for manufacture
US20110299324A1 (en) 2008-10-31 2011-12-08 Seagate Technology Llc Write current compensation using word line boosting circuitry
US20110305064A1 (en) 2010-06-11 2011-12-15 Crossbar, Inc. Interface control for improved switching in rram
US20110312151A1 (en) 2010-06-11 2011-12-22 Crossbar Inc. Pillar structure for memory device and method
US20110310656A1 (en) 2010-06-18 2011-12-22 Franz Kreupl Memory Cell With Resistance-Switching Layers Including Breakdown Layer
US8084830B2 (en) 2009-02-24 2011-12-27 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US20110317470A1 (en) * 2010-06-24 2011-12-29 The Regents Of The University Of Michigan Rectification element and method for resistive switching for non volatile memory device
US8088688B1 (en) 2010-11-05 2012-01-03 Crossbar, Inc. p+ polysilicon material on aluminum for non-volatile memory device and method
US20120001145A1 (en) 2008-12-31 2012-01-05 Michele Magistretti Avoiding degradation of chalcogenide material during definition of multilayer stack structure
US20120001146A1 (en) 2010-06-24 2012-01-05 The Regents Of The University Of Michigan Nanoscale metal oxide resistive switching element
EP2405441A1 (en) 2010-07-09 2012-01-11 Crossbar, Inc. Resistive memory using SiGe material
US20120007035A1 (en) 2010-07-12 2012-01-12 Crossbar, Inc. Intrinsic Programming Current Control for a RRAM
US8097874B2 (en) 2008-10-30 2012-01-17 Seagate Technology Llc Programmable resistive memory cell with sacrificial metal
EP2408035A2 (en) 2010-07-13 2012-01-18 Crossbar, Inc. Two terminal resistive switching device structure and method of fabricating
US20120012806A1 (en) 2010-07-13 2012-01-19 Crossbar, Inc. Improved on/off ratio for non-volatile memory device and method
US20120012808A1 (en) 2004-09-29 2012-01-19 Herner S Brad Deposited semiconductor structure to minimize n-type dopant diffusion and method of making
US8102018B2 (en) 2005-05-09 2012-01-24 Nantero Inc. Nonvolatile resistive memories having scalable two-terminal nanotube switches
US20120025161A1 (en) 2008-02-27 2012-02-02 Manuj Rathor Diode and resistive memory device structures
US20120033479A1 (en) 2010-08-06 2012-02-09 Lsi Corporation Modification of logic by morphological manipulation of a semiconductor resistive element
US20120043520A1 (en) 2010-08-23 2012-02-23 Crossbar, Inc. Disturb-resistant non-volatile memory device and method
US20120044751A1 (en) 2009-10-28 2012-02-23 Intermolecular, Inc. Bipolar resistive-switching memory with a single diode per memory cell
US20120043621A1 (en) 2010-08-23 2012-02-23 Crossbar, Inc. Stackable non-volatile resistive switching memory device and method
US20120043654A1 (en) 2010-08-19 2012-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
US20120043519A1 (en) 2010-08-23 2012-02-23 Crossbar, Inc. Device switching using layered device structure
US20120074507A1 (en) 2010-09-29 2012-03-29 Crossbar, Inc. Integration of an amorphous silicon resistive switching device
US20120076203A1 (en) 2009-05-29 2012-03-29 Mitsubishi Electric Corporation Video encoding device, video decoding device, video encoding method, and video decoding method
US20120074374A1 (en) 2010-09-29 2012-03-29 Crossbar, Inc. Conductive path in switching material in a resistive random access memory device and control
US20120087172A1 (en) 2010-10-12 2012-04-12 Fujitsu Limited Semiconductor memory and system
US20120087169A1 (en) 2010-10-07 2012-04-12 Crossbar, Inc. Circuit for concurrent read operation and method therefor
US20120091420A1 (en) 2010-10-15 2012-04-19 Kabushiki Kaisha Toshiba Nonvolatile resistance change device
US20120108030A1 (en) 2010-10-27 2012-05-03 Crossbar, Inc. Method for obtaining smooth, continuous silver film
US20120104351A1 (en) 2010-07-01 2012-05-03 Zhiqiang Wei Non-volatile memory cell, non-volatile memory cell array, and method of manufacturing the same
US20120122290A1 (en) 2006-07-14 2012-05-17 4D-S Pty Ltd. Systems and methods for fabricating self-aligned memory cell
US20120140816A1 (en) 2010-12-01 2012-06-07 Jean-Francois Franche Method and system for parallel encoding of a video
US20120147657A1 (en) 2009-06-19 2012-06-14 Sekar Deepak C Programming reversible resistance switching elements
US20120145984A1 (en) 2010-12-13 2012-06-14 Peter Rabkin Punch-through diode
US20120155146A1 (en) 2010-12-20 2012-06-21 Yoshihiro Ueda Resistance-change memory
US8207064B2 (en) 2009-09-17 2012-06-26 Sandisk 3D Llc 3D polysilicon diode with low contact resistance and method for forming same
US20120176831A1 (en) 2010-06-18 2012-07-12 Li Xiao Resistive Random Access Memory With Low Current Operation
US8231998B2 (en) 2007-03-30 2012-07-31 The Regents Of The University Of Michigan Deposited microarchitectured battery and manufacturing method
US8237146B2 (en) 2010-02-24 2012-08-07 Sandisk 3D Llc Memory cell with silicon-containing carbon switching layer and methods for forming the same
US8243542B2 (en) 2005-11-30 2012-08-14 Samsung Electronics Co., Ltd. Resistance variable memory devices and read methods thereof
US20120205793A1 (en) 2011-02-10 2012-08-16 Applied Materials, Inc. Seed layer passivation
US20120205606A1 (en) 2011-02-14 2012-08-16 Dongguk University Industry-Academic Cooperation Foundation Nonvolatile Memory Device Using The Resistive Switching of Graphene Oxide And The Fabrication Method Thereof
US20120218807A1 (en) 2011-02-25 2012-08-30 Micron Technology, Inc. Resistive memory sensing methods and devices
US8258020B2 (en) 2010-11-04 2012-09-04 Crossbar Inc. Interconnects for stacked non-volatile memory device and method
US20120224413A1 (en) 2011-03-02 2012-09-06 Jingyan Zhang Non-Volatile Storage System Using Opposite Polarity Programming Signals For MIM Memory Cell
US20120235112A1 (en) 2010-11-30 2012-09-20 Huo Zongliang Resistive switching memory and method for manufacturing the same
US20120236625A1 (en) 2011-03-18 2012-09-20 Sony Corporation Memory element and memory device
US8274812B2 (en) 2010-06-14 2012-09-25 Crossbar, Inc. Write and erase scheme for resistive memory device
US20120241710A1 (en) 2011-03-21 2012-09-27 Nanyang Technological University Fabrication of RRAM Cell Using CMOS Compatible Processes
US20120243292A1 (en) 2011-03-22 2012-09-27 Akira Takashima Memory device
US20120250183A1 (en) 2011-03-31 2012-10-04 Nidec Corporation Motor and storage disk drive
US20120269275A1 (en) 2010-10-20 2012-10-25 Nokia Corporation Method and device for video coding and decoding
US8305793B2 (en) 2008-05-16 2012-11-06 Qimonda Ag Integrated circuit with an array of resistance changing memory cells
US8320160B2 (en) 2011-03-18 2012-11-27 Crossbar, Inc. NAND architecture having a resistive memory cell connected to a control gate of a field-effect transistor
US20120305874A1 (en) 2011-05-31 2012-12-06 Crossbar, Inc. Vertical Diodes for Non-Volatile Memory Device
US20120305879A1 (en) 2011-05-31 2012-12-06 Crossbar, Inc. Switching device having a non-linear element
US20120327701A1 (en) 2011-06-23 2012-12-27 Crossbar, Inc. Memory array architecture with two-terminal memory cells
US20120326265A1 (en) 2011-06-24 2012-12-27 International Business Machines Corporation Method of forming memory cell access device
US20130023085A1 (en) 2011-07-22 2013-01-24 Intermolecular, Inc. Method for forming metal oxides and silicides in a memory device
US20130020548A1 (en) 2011-07-22 2013-01-24 Crossbar, Inc. Seed layer for a p+ silicon germanium material for a non-volatile memory device and method
US8369129B2 (en) 2009-06-18 2013-02-05 Kabushiki Kaisha Toshiba Semiconductor memory device with variable resistance element
US8385100B2 (en) 2009-12-08 2013-02-26 Intel Corporation Energy-efficient set write of phase change memory with switch
US8389971B2 (en) 2010-10-14 2013-03-05 Sandisk 3D Llc Memory cells having storage elements that share material layers with steering elements and methods of forming the same
US20130065066A1 (en) 2010-05-27 2013-03-14 Applied Thin Films, Inc. Protective coatings for substrates having an active surface
US20130075685A1 (en) 2011-09-22 2013-03-28 Yubao Li Methods and apparatus for including an air gap in carbon-based memory devices
US20130075688A1 (en) 2011-09-27 2013-03-28 Semiconductor Manufacturing International Corporation Semiconductor Memory Device and Manufacturing Method Thereof
US20130119341A1 (en) 2011-01-27 2013-05-16 Institute of Microelectronics, Chinese Academy of Sciences Resistive random access memory cell and memory
US8456892B2 (en) 2010-09-29 2013-06-04 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US8467226B2 (en) 2011-01-14 2013-06-18 Micron Technology, Inc. Programming an array of resistance random access memory cells using unipolar pulses
US8467227B1 (en) 2010-11-04 2013-06-18 Crossbar, Inc. Hetero resistive switching material layer in RRAM device and method
US20130166825A1 (en) 2011-12-27 2013-06-27 Jin Yeong Kim Method Of Controlling Non-Volatile Memory, Non-Volatile Memory Controller Therefor, And Memory System Including The Same
US20130207065A1 (en) 2012-02-14 2013-08-15 Intermolecular, Inc. Bipolar multistate nonvolatile memory
US20130214234A1 (en) 2012-02-22 2013-08-22 Adesto Technologies Corporation Resistive Switching Devices and Methods of Formation Thereof
US20130235648A1 (en) 2012-03-12 2013-09-12 Samsung Semiconductor Co., Ltd. Resistive memory device and related method of operation
US20130279240A1 (en) 2010-11-04 2013-10-24 Crossbar, Inc. Hetero-switching layer in a rram device and method
US8569104B2 (en) 2012-02-07 2013-10-29 Intermolecular, Inc. Transition metal oxide bilayers
US8587989B2 (en) 2008-06-20 2013-11-19 Nantero Inc. NRAM arrays with nanotube blocks, nanotube traces, and nanotube planes and methods of making same
US20130308369A1 (en) 2010-11-04 2013-11-21 Crossbar, Inc. Switching device having a non-linear element
US8619459B1 (en) 2011-06-23 2013-12-31 Crossbar, Inc. High operating speed resistive random access memory
US20140015018A1 (en) 2012-07-12 2014-01-16 SK Hynix Inc. Semiconductor device and method of fabricating the same
US20140029327A1 (en) 2012-07-24 2014-01-30 John Paul Strachan Bipolar resistive switch heat mitigation
US8658476B1 (en) 2012-04-20 2014-02-25 Crossbar, Inc. Low temperature P+ polycrystalline silicon material for non-volatile memory device
US20140070160A1 (en) 2012-09-07 2014-03-13 Takayuki Ishikawa Nonvolatile memory device
US8693241B2 (en) 2011-07-13 2014-04-08 SK Hynix Inc. Semiconductor intergrated circuit device, method of manufacturing the same, and method of driving the same
US20140103284A1 (en) 2012-02-07 2014-04-17 Intermolecular Inc. ReRAM Cells Including TaXSiYN Embedded Resistors
US20140145135A1 (en) 2011-06-30 2014-05-29 Crossbar, Inc. Sub-oxide interface layer for two-terminal memory
US20140166961A1 (en) 2012-12-14 2014-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Resistive random access memory (rram) and method of making
US20140175360A1 (en) 2012-12-20 2014-06-26 Intermolecular Inc. Bilayered Oxide Structures for ReRAM Cells
US20140177315A1 (en) 2012-12-20 2014-06-26 Intermolecular Inc. Multi-Level Memory Array Having Resistive Elements For Multi-Bit Data Storage
US20140192589A1 (en) 2012-04-13 2014-07-10 Crossbar, Inc. Reduced diffusion in metal electrode for two-terminal memory
US20140197369A1 (en) 2013-01-16 2014-07-17 Hewlett-Packard Development Company, L.P. Nanoparticle-based memristor structure
US20140233294A1 (en) 2013-02-21 2014-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Memory Cell with Decoupled Read/Write Path
US20140269002A1 (en) 2013-03-14 2014-09-18 Crossbar, Inc. Two-terminal memory with intrinsic rectifying characteristic
US20140268997A1 (en) 2013-03-15 2014-09-18 Crossbar, Inc. Programming two-terminal memory cells with reduced program current
US20140264236A1 (en) 2013-03-14 2014-09-18 Crossbar, Inc. Controlling on-state current for two-terminal memory
US20140264250A1 (en) 2013-03-14 2014-09-18 Crossbar, Inc. Low temperature in-situ doped silicon-based conductor material for memory cell
US20140268998A1 (en) 2013-03-14 2014-09-18 Crossbar, Inc. Rram with dual mode operation
US8853759B2 (en) 2008-01-23 2014-10-07 Samsung Electronics Co., Ltd. Resistive memory devices and methods of manufacturing the same
US20140312296A1 (en) 2011-06-30 2014-10-23 Crossbar, Inc. Three-dimensional oblique two-terminal memory with enhanced electric field
US20140335675A1 (en) 2013-05-08 2014-11-13 Crossbar, Inc. Regulating interface layer growth with n2o for two-terminal memory
US8946667B1 (en) 2012-04-13 2015-02-03 Crossbar, Inc. Barrier structure for a silver based RRAM and method
US8946673B1 (en) 2012-08-24 2015-02-03 Crossbar, Inc. Resistive switching device structure with improved data retention for non-volatile memory device and method
US20150070961A1 (en) 2013-09-06 2015-03-12 Kabushiki Kaisha Toshiba Semiconductor storage device
US8999811B2 (en) 2010-05-21 2015-04-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20150228334A1 (en) 2011-05-31 2015-08-13 Crossbar, Inc. Memory array architecture with two-terminal memory cells
US20160111640A1 (en) 2014-10-15 2016-04-21 National Sun Yat-Sen University Resistive random access memory

Patent Citations (498)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US680652A (en) 1897-11-08 1901-08-13 Leonard L Elden Circuit-breaker.
US4433468A (en) 1980-03-26 1984-02-28 Nippon Electric Co., Ltd. Method for making semiconductor device having improved thermal stress characteristics
US4684972A (en) 1981-08-07 1987-08-04 The British Petroleum Company, P.L.C. Non-volatile amorphous semiconductor memory device utilizing a forming voltage
US4741601A (en) 1984-10-08 1988-05-03 Nec Corporation Non-linear device for driving liquid crystal display
US4994866A (en) 1988-01-07 1991-02-19 Fujitsu Limited Complementary semiconductor device
US5139911A (en) 1989-01-04 1992-08-18 Fuji Xerox Co., Ltd. Electrophotographic photoreceptor with two part surface layer
US5360981A (en) 1989-05-11 1994-11-01 British Telecommunications Public Limited Company Amorphous silicon memory
US5763898A (en) 1990-04-12 1998-06-09 Actel Corporation Above via metal-to-metal antifuses incorporating a tungsten via plug
US5614756A (en) 1990-04-12 1997-03-25 Actel Corporation Metal-to-metal antifuse with conductive
US5315131A (en) 1990-11-22 1994-05-24 Matsushita Electric Industrial Co., Ltd. Electrically reprogrammable nonvolatile memory device
US5335219A (en) 1991-01-18 1994-08-02 Ovshinsky Stanford R Homogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements
US5707487A (en) 1991-01-22 1998-01-13 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5242855A (en) 1991-09-30 1993-09-07 Nec Corporation Method of fabricating a polycrystalline silicon film having a reduced resistivity
US5541869A (en) 1991-10-22 1996-07-30 British Telecommunications, Plc Resistive memory element
US5278085A (en) 1992-08-11 1994-01-11 Micron Semiconductor, Inc. Single mask process for forming both n-type and p-type gates in a polycrystalline silicon layer during the formation of a semiconductor device
US6002268A (en) 1993-01-08 1999-12-14 Dynachip Corporation FPGA with conductors segmented by active repeaters
US5627451A (en) 1993-04-28 1997-05-06 Fujitsu Limited Control method and control apparatus for secondary battery charging in constant current charging method
US5538564A (en) 1994-03-18 1996-07-23 Regents Of The University Of California Three dimensional amorphous silicon/microcrystalline silicon solar cells
US5596214A (en) 1994-05-30 1997-01-21 Nec Corporation Non-volatile semiconductor memory device having a metal-insulator-semiconductor gate structure and method for fabricating the same
US5645628A (en) 1994-07-14 1997-07-08 Matsushita Electric Industrial Co., Ltd. Electroless plating bath used for forming a wiring of a semiconductor device, and method of forming a wiring of a semiconductor device
US5457649A (en) 1994-08-26 1995-10-10 Microchip Technology, Inc. Semiconductor memory device and write-once, read-only semiconductor memory array using amorphous-silicon and method therefor
US5714416A (en) 1994-08-26 1998-02-03 Microchip Technology Incorporated Semiconductor memory device and write-once, read-only semiconductor memory array using amorphous-silicon and method therefor
US5499208A (en) 1994-09-12 1996-03-12 At&T Corp. Integrated circuit memory device
US5973335A (en) 1994-12-22 1999-10-26 U.S. Philips Corporation Semiconductor memory devices with amorphous silicon alloy
US5970332A (en) 1995-03-28 1999-10-19 U.S. Philips Corporation Method of manufacturing a semiconductor device with a BiCMOS circuit
US5594363A (en) 1995-04-07 1997-01-14 Zycad Corporation Logic cell and routing architecture in a field programmable gate array
US5751012A (en) 1995-06-07 1998-05-12 Micron Technology, Inc. Polysilicon pillar diode for use in a non-volatile memory cell
US20050029587A1 (en) 1995-06-07 2005-02-10 Harshfield Steven T. Method and apparatus for forming an integrated circuit electrode having a reduced contact area
US5673223A (en) 1995-06-09 1997-09-30 Samsung Electronics Co., Ltd. Nonvolatile semiconductor memory device with multiple word line voltage generators
US6291836B1 (en) 1996-06-05 2001-09-18 U. S. Philips Corporation Method of operating a programmable, non-volatile memory device
US5998244A (en) 1996-08-22 1999-12-07 Micron Technology, Inc. Memory cell incorporating a chalcogenide element and method of making same
US5923587A (en) 1996-09-21 1999-07-13 Samsung Electronics, Co., Ltd. Multi-bit memory cell array of a non-volatile semiconductor memory device and method for driving the same
US6122318A (en) 1996-10-31 2000-09-19 Kabushiki Kaisha Toshiba Video encoding apparatus and video decoding apparatus
US5840608A (en) 1996-11-22 1998-11-24 United Microelectronics Corporation High density ROM and a method of making the same
US6436818B1 (en) 1997-02-19 2002-08-20 Micron Technology, Inc. Semiconductor structure having a doped conductive layer
US6864127B2 (en) 1997-04-25 2005-03-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US6259116B1 (en) 1997-10-22 2001-07-10 U.S. Philips Corporation Multiple memory element semiconductor memory devices
US6143642A (en) 1997-12-22 2000-11-07 Vlsi Technology, Inc. Programmable semiconductor structures and methods for making the same
US6492694B2 (en) 1998-02-27 2002-12-10 Micron Technology, Inc. Highly conductive composite polysilicon gate for CMOS integrated circuits
US6180998B1 (en) 1998-03-30 2001-01-30 Lsi Logic Corporation DRAM with built-in noise protection
US6762474B1 (en) 1998-06-10 2004-07-13 Agere Systems Inc. Method and apparatus for temperature compensation of read-only memory
US6037204A (en) 1998-08-07 2000-03-14 Taiwan Semiconductor Manufacturing Company Silicon and arsenic double implanted pre-amorphization process for salicide technology
US20020048940A1 (en) 1998-09-03 2002-04-25 Garo J. Derderian Chemical vapor deposition for smooth metal films
US20030206659A1 (en) 1998-09-08 2003-11-06 Canon Kabushiki Kaisha Image processing apparatus including an image data encoder having at least two scalability modes and method therefor
US20040194340A1 (en) 1998-10-14 2004-10-07 Tokyo Electron Limited Method and apparatus for surface treatment
US20060134837A1 (en) 1998-11-16 2006-06-22 Vivek Subramanian Vertically stacked field programmable nonvolatile memory and method of fabrication
US6181597B1 (en) 1999-02-04 2001-01-30 Tower Semiconductor Ltd. EEPROM array using 2-bit non-volatile memory cells with serial read operations
US6128214A (en) 1999-03-29 2000-10-03 Hewlett-Packard Molecular wire crossbar memory
EP1096465A2 (en) 1999-10-26 2001-05-02 Sel Semiconductor Energy Laboratory Co., Ltd. Gradation control of an electro-optical display device
US6181587B1 (en) 1999-11-24 2001-01-30 Mitsubishi Denki Kabushiki Kaisha Analog signal detecting circuit, and AC side current detector of semiconductor power conversion device
US6288435B1 (en) 1999-12-28 2001-09-11 Xerox Corporation Continuous amorphous silicon layer sensors using doped poly-silicon back contact
US6939787B2 (en) 1999-12-28 2005-09-06 Fujitsu Limited Method for fabricating semiconductor device having gate electrode with polymetal structure of polycrystalline silicon film and metal film
US6724186B2 (en) 2000-06-27 2004-04-20 Brown & Sharpe Tesa Sa Measuring device with magneto-resistive electrodes, and measuring method
US20120080798A1 (en) 2000-07-14 2012-04-05 Round Rock Research, Llc Memory devices having contact features
US20090152737A1 (en) 2000-07-14 2009-06-18 Micron Technology, Inc. Memory devices having contact features
US6881994B2 (en) 2000-08-14 2005-04-19 Matrix Semiconductor, Inc. Monolithic three dimensional array of charge storage devices containing a planarized surface
US20030036238A1 (en) 2000-12-22 2003-02-20 The Regents Of The University Of California Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction
US6627530B2 (en) 2000-12-22 2003-09-30 Matrix Semiconductor, Inc. Patterning three dimensional structures
US20050019699A1 (en) 2001-02-08 2005-01-27 Moore John T. Non-volatile resistance variable device
US6436765B1 (en) 2001-02-09 2002-08-20 United Microelectronics Corp. Method of fabricating a trenched flash memory cell
US7102150B2 (en) 2001-05-11 2006-09-05 Harshfield Steven T PCRAM memory cell and method of making same
US6927430B2 (en) 2001-06-28 2005-08-09 Sharp Laboratories Of America, Inc. Shared bit line cross-point memory array incorporating P/N junctions
US20030006440A1 (en) 2001-07-03 2003-01-09 Matsushita Electric Industrial Co., Ltd. Integrated circuit device including a layered superlattice material with an interface buffer layer
US6768157B2 (en) 2001-08-13 2004-07-27 Advanced Micro Devices, Inc. Memory device
US20040159835A1 (en) 2001-08-13 2004-08-19 Krieger Juri Heinrich Memory device
US6858481B2 (en) 2001-08-13 2005-02-22 Advanced Micro Devices, Inc. Memory device with active and passive layers
US6864522B2 (en) 2001-08-13 2005-03-08 Advanced Micro Devices, Inc. Memory device
US6838720B2 (en) 2001-08-13 2005-01-04 Advanced Micro Devices, Inc. Memory device with active passive layers
US6815286B2 (en) 2001-08-13 2004-11-09 Advanced Micro Devices, Inc. Memory device
US7026702B2 (en) 2001-08-13 2006-04-11 Advanced Micro Devices, Inc. Memory device
US7254053B2 (en) 2001-08-13 2007-08-07 Advanced Micro Devices, Inc. Active programming and operation of a memory device
US20030052330A1 (en) 2001-09-20 2003-03-20 Klein Rita J. Electro-and electroless plating of metal in the manufacture of PCRAM devices
US6552932B1 (en) 2001-09-21 2003-04-22 Sandisk Corporation Segmented metal bitlines
US20040036124A1 (en) 2001-09-25 2004-02-26 Matrix Semiconductor, Inc. Inverted staggered thin film transistor with salicided source/drain structures and method of making same
JP2005506703A (en) 2001-10-16 2005-03-03 ミッドウエスト リサーチ インスティチュート The combination of stacked switchable element and a diode
WO2003034498A1 (en) 2001-10-16 2003-04-24 Midwest Research Institute Stacked switchable element and diode combination
US6867618B2 (en) 2001-11-19 2005-03-15 Broadcom Corporation Voltage mode differential driver and method
US20030141565A1 (en) 2002-01-28 2003-07-31 Fumihiko Hirose Diode
US6740921B2 (en) 2002-02-01 2004-05-25 Hitachi, Ltd. Semiconductor memory cell and method of forming same
US20040192006A1 (en) 2002-02-20 2004-09-30 Campbell Kristy A. Layered resistance variable memory device and method of fabrication
US20030174574A1 (en) 2002-03-12 2003-09-18 Perner Frederick A. Write pulse circuit for a magnetic memory
US7927472B2 (en) 2002-03-25 2011-04-19 Ulvac, Inc. Optical film thickness controlling method, optical film thickness controlling apparatus, dielectric multilayer film manufacturing apparatus, and dielectric multilayer film manufactured using the same controlling apparatus or manufacturing apparatus
US7479650B2 (en) 2002-04-10 2009-01-20 Micron Technology, Inc. Method of manufacture of programmable conductor memory
US6858482B2 (en) 2002-04-10 2005-02-22 Micron Technology, Inc. Method of manufacture of programmable switching circuits and memory cells employing a glass layer
US20030194865A1 (en) 2002-04-10 2003-10-16 Gilton Terry L. Method of manufacture of programmable conductor memory
US20040026682A1 (en) 2002-06-17 2004-02-12 Hai Jiang Nano-dot memory and fabricating same
US20080206931A1 (en) 2002-07-26 2008-08-28 Laurent Breuil Nonvolatile memory element and production method thereof and storage memory arrangement
US20040170040A1 (en) 2002-08-02 2004-09-02 Unity Semiconductor Corporation Rewritable memory with non-linear memory element
US7020006B2 (en) 2002-08-02 2006-03-28 Unity Semiconductor Corporation Discharge of conductive array lines in fast memory
US20050020510A1 (en) 2002-08-29 2005-01-27 Benedict Dale L. D-mannose contraceptives
US7087454B2 (en) 2002-08-29 2006-08-08 Micron Technology, Inc. Fabrication of single polarity programmable resistance structure
US6848012B2 (en) 2002-09-27 2005-01-25 Broadcom Corporation Method and system for an adaptive multimode media queue
US20050062045A1 (en) 2002-10-02 2005-03-24 Arup Bhattacharyya Processes of forming stacked resistor constructions
US7023093B2 (en) 2002-10-24 2006-04-04 International Business Machines Corporation Very low effective dielectric constant interconnect Structures and methods for fabricating the same
US6821879B2 (en) 2002-10-30 2004-11-23 Xerox Corporation Copper interconnect by immersion/electroless plating in dual damascene process
US6731535B1 (en) 2002-12-10 2004-05-04 Renesas Technology Corp. Nonvolatile semiconductor memory device
US20090298224A1 (en) 2002-12-13 2009-12-03 Lowrey Tyler A Memory and Access Device and Method Therefor
US7238607B2 (en) 2002-12-19 2007-07-03 Sandisk 3D Llc Method to minimize formation of recess at surface planarized by chemical mechanical planarization
US20050052915A1 (en) 2002-12-19 2005-03-10 Matrix Semiconductor, Inc. Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states
US20080002481A1 (en) 2002-12-20 2008-01-03 Dietmar Gogl Integrated Circuit, Method of Operating an Integrated Circuit, Method of Manufacturing an Integrated Circuit, Memory Module, Stackable Memory Module
US7433253B2 (en) 2002-12-20 2008-10-07 Qimonda Ag Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module
US6897519B1 (en) 2003-02-26 2005-05-24 Dialog Semiconductor Tunneling floating gate APS pixel
US7606059B2 (en) 2003-03-18 2009-10-20 Kabushiki Kaisha Toshiba Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array
US7729158B2 (en) 2003-04-03 2010-06-01 Kabushiki Kaisha Toshiba Resistance change memory device
US20040202041A1 (en) 2003-04-11 2004-10-14 Sharp Kabushiki Kaisha Memory cell, memory device and manufacturing method of memory cell
US6816405B1 (en) 2003-06-02 2004-11-09 International Business Machines Corporation Segmented word line architecture for cross point magnetic random access memory
US20050041498A1 (en) 2003-06-16 2005-02-24 Claudio Resta Writing circuit for a phase change memory device
US20080007987A1 (en) 2003-09-22 2008-01-10 Daisaburo Takashima Semiconductor integrated circuit device
US7883964B2 (en) 2003-09-30 2011-02-08 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and a fabrication method thereof
US20050101081A1 (en) 2003-09-30 2005-05-12 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and a fabrication method thereof
US20050073881A1 (en) 2003-10-06 2005-04-07 Tran Lung The Magnetic memory device including groups of series-connected memory elements
US7167387B2 (en) 2003-10-23 2007-01-23 Matsushita Electric Industrial Co., Ltd. Variable resistance element, method of manufacturing the element, memory containing the element, and method of driving the memory
US20100034518A1 (en) 2003-11-10 2010-02-11 Panasonic Corporation Integrated circuit for use in a playback apparatus
US20070087508A1 (en) 2003-12-03 2007-04-19 Herner S B Method for making a p-i-n diode crystallized adjacent to a silicide in series with a dielectric antifuse
US6946719B2 (en) 2003-12-03 2005-09-20 Matrix Semiconductor, Inc Semiconductor device including junction diode contacting contact-antifuse unit comprising silicide
US20070105284A1 (en) 2003-12-03 2007-05-10 Herner S B Method for forming a memory cell comprising a semiconductor junction diode crystallized adjacent to a silicide
US7474000B2 (en) 2003-12-05 2009-01-06 Sandisk 3D Llc High density contact to relaxed geometry layers
US6849891B1 (en) 2003-12-08 2005-02-01 Sharp Laboratories Of America, Inc. RRAM memory cell electrodes
US20100182821A1 (en) 2003-12-26 2010-07-22 Panasonic Corporation Memory device, memory circuit and semiconductor integrated circuit having variable resistance
US20070091685A1 (en) 2004-01-27 2007-04-26 Guterman Daniel C Efficient verification for coarse/fine programming of non-volatile memory
US20050175099A1 (en) 2004-02-06 2005-08-11 Nokia Corporation Transcoder and associated system, method and computer program product for low-complexity reduced resolution transcoding
US7405418B2 (en) 2004-02-17 2008-07-29 Infineon Technologies Ag Memory device electrode with a surface structure
US7746601B2 (en) 2004-03-03 2010-06-29 Kabushiki Kaisha Toshiba Magneto-resistance effect element with a surface contacting with a side face of electrode having a magnetization direction
US8164948B2 (en) 2004-06-04 2012-04-24 Micron Technology, Inc. Spintronic devices with integrated transistors
US8004882B2 (en) 2004-06-04 2011-08-23 Micron Technology, Inc. Spintronic devices with integrated transistors
JP2008503085A (en) 2004-06-16 2008-01-31 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Electrical device and manufacturing method thereof
WO2005124787A2 (en) 2004-06-16 2005-12-29 Koninklijke Philips Electronics N.V. Electrical device having a programmable resistor connected in series to a punch-through diode and method of manufacturing therefor
US20060017488A1 (en) 2004-07-21 2006-01-26 Sharp Laboratories Of America, Inc. Mono-polarity switchable PCMO resistor trimmer
JP2006032951A (en) 2004-07-21 2006-02-02 Sharp Corp Monopolar variable resistance pcmo resistor adjusting circuit
US20080083918A1 (en) 2004-07-22 2008-04-10 Sony Corporation Storage Element
US7365411B2 (en) 2004-08-12 2008-04-29 Micron Technology, Inc. Resistance variable memory with temperature tolerant materials
US7122853B1 (en) 2004-08-17 2006-10-17 Fasl, Inc. Method to improve yield and simplify operation of polymer memory cells
US7289353B2 (en) 2004-08-17 2007-10-30 Spansion, Llc Systems and methods for adjusting programming thresholds of polymer memory cells
US7251152B2 (en) 2004-08-26 2007-07-31 Infineon Technologies Ag Memory circuit having memory cells which have a resistance memory element
US20060054950A1 (en) 2004-09-10 2006-03-16 In-Gyu Baek Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer and methods of manufacturing the same
US7534625B2 (en) 2004-09-24 2009-05-19 Karpov Ilya V Phase change memory with damascene memory element
US20120012808A1 (en) 2004-09-29 2012-01-19 Herner S Brad Deposited semiconductor structure to minimize n-type dopant diffusion and method of making
US7221599B1 (en) 2004-11-01 2007-05-22 Spansion, Llc Polymer memory cell operation
US7550380B2 (en) 2004-11-03 2009-06-23 Micron Technology, Inc. Electroless plating of metal caps for chalcogenide-based memory devices
US7274587B2 (en) 2004-11-10 2007-09-25 Kabushiki Kaisha Toshiba Semiconductor memory element and semiconductor memory device
US20060154417A1 (en) 2005-01-11 2006-07-13 Sharp Kabushiki Kaisha Semiconductor memory device
US8102698B2 (en) 2005-01-19 2012-01-24 Sandisk 3D Llc Structure and method for biasing phase change memory array for reliable writing
US7859884B2 (en) 2005-01-19 2010-12-28 Sandisk 3D Llc Structure and method for biasing phase change memory array for reliable writing
US7749805B2 (en) 2005-03-10 2010-07-06 Qimonda Ag Method for manufacturing an integrated circuit including an electrolyte material layer
US7667442B2 (en) 2005-03-16 2010-02-23 Ricoh Company, Ltd. Constant voltage power supply circuit and method of testing the same
US20060215445A1 (en) 2005-03-28 2006-09-28 In-Gyu Baek Magneto-resistive memory cells and devices having asymmetrical contacts and methods of fabrication therefor
US20110204314A1 (en) 2005-03-28 2011-08-25 Samsung Electronics Co., Ltd. Resistive memory cells and devices having asymmetrical contacts
US20060231910A1 (en) 2005-04-15 2006-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming silicide and semiconductor device formed thereby
US7776682B1 (en) 2005-04-20 2010-08-17 Spansion Llc Ordered porosity to direct memory element formation
US20060246606A1 (en) 2005-05-02 2006-11-02 Sharp Laboratories Of America, Inc. Self-aligned cross point resistor memory array
US7835170B2 (en) 2005-05-09 2010-11-16 Nantero, Inc. Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks
US8102018B2 (en) 2005-05-09 2012-01-24 Nantero Inc. Nonvolatile resistive memories having scalable two-terminal nanotube switches
US20060281244A1 (en) 2005-06-08 2006-12-14 Masayuki Ichige Nonvolatile semiconductor memory device and method of manufacturing the same
US20060279979A1 (en) 2005-06-13 2006-12-14 Tyler Lowrey Method of reading phase-change memory elements
US20060286762A1 (en) 2005-06-15 2006-12-21 Winbond Electronics Corp. Method for non-volatile memory fabrication
US7238994B2 (en) 2005-06-17 2007-07-03 Macronix International Co., Ltd. Thin film plate phase change ram circuit and manufacturing method
US7426128B2 (en) 2005-07-11 2008-09-16 Sandisk 3D Llc Switchable resistive memory with opposite polarity write pulses
US7345907B2 (en) 2005-07-11 2008-03-18 Sandisk 3D Llc Apparatus and method for reading an array of nonvolatile memory cells including switchable resistor memory elements
US20070008773A1 (en) 2005-07-11 2007-01-11 Matrix Semiconductor, Inc. Nonvolatile memory cell comprising switchable resistor and transistor
US7968419B2 (en) 2005-07-18 2011-06-28 Sharp Laboratories Of America, Inc. Back-to-back metal/semiconductor/metal (MSM) Schottky diode
US20070284575A1 (en) 2005-07-18 2007-12-13 Sharp Laboratories Of America, Inc. Metal/semiconductor/metal current limiter
US20070015348A1 (en) 2005-07-18 2007-01-18 Sharp Laboratories Of America, Inc. Crosspoint resistor memory device with back-to-back Schottky diodes
US20070025144A1 (en) 2005-07-29 2007-02-01 International Business Machines Corporation Write operations for phase-change-material memory
US7521705B2 (en) 2005-08-15 2009-04-21 Micron Technology, Inc. Reproducible resistance variable insulating memory devices having a shaped bottom electrode
US20070035990A1 (en) 2005-08-15 2007-02-15 Micron Technology, Inc. Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
US20070042612A1 (en) 2005-08-22 2007-02-22 Hirotaka Nishino Method for manufacturing semiconductor device
JP2007067408A (en) 2005-08-31 2007-03-15 Samsung Electronics Co Ltd Nonvolatile organic resistance memory device and manufacturing method thereof
US20070045615A1 (en) 2005-08-31 2007-03-01 Samsung Electronics Co., Ltd. Non-volatile organic resistance random access memory device and method of manufacturing the same
US20070133270A1 (en) 2005-09-05 2007-06-14 Samsung Electronics Co., Ltd. Phase-change random access memory device and method of operating the same
US20070069119A1 (en) 2005-09-23 2007-03-29 Massachusetts Institute Of Technology Optical trapping with a semiconductor
US20070090425A1 (en) 2005-09-28 2007-04-26 Matrix Semiconductor, Inc. Memory cell comprising switchable semiconductor memory element with trimmable resistance
US20080192531A1 (en) 2005-10-19 2008-08-14 Fujitsu Limited Method of writing into semiconductor memory device
US20070105390A1 (en) 2005-11-09 2007-05-10 Oh Travis B Oxygen depleted etching process
US7187577B1 (en) 2005-11-23 2007-03-06 Grandis, Inc. Method and system for providing current balanced writing for memory cells and magnetic devices
US8243542B2 (en) 2005-11-30 2012-08-14 Samsung Electronics Co., Ltd. Resistance variable memory devices and read methods thereof
US20070133250A1 (en) 2005-12-08 2007-06-14 Juhan Kim Phase change memory including diode access device
US7324363B2 (en) 2005-12-12 2008-01-29 Synopsys, Inc. SPICE optimized for arrays
US20070171698A1 (en) 2005-12-23 2007-07-26 Heinz Hoenigschmid Memory circuit including a resistive memory element and method for operating such a memory circuit
US20070159876A1 (en) 2006-01-06 2007-07-12 Tadahiko Sugibayashi Magnetic ramdom access memory and operating method of the same
US20070159869A1 (en) 2006-01-09 2007-07-12 Samsung Electronics Co., Ltd. Multi-state resistive memory element, multi-bit resistive memory cell, operating method thereof, and data processing system using the memory element
US20070205510A1 (en) 2006-03-03 2007-09-06 Lavoie Adrien R Noble metal barrier layers
US20070228414A1 (en) 2006-03-31 2007-10-04 Sandisk 3D, Llc Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride
US7829875B2 (en) 2006-03-31 2010-11-09 Sandisk 3D Llc Nonvolatile rewritable memory cell comprising a resistivity-switching oxide or nitride and an antifuse
US7875871B2 (en) 2006-03-31 2011-01-25 Sandisk 3D Llc Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride
US8227787B2 (en) 2006-03-31 2012-07-24 Sandisk 3D Llc Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride
JP2007281208A (en) 2006-04-07 2007-10-25 Matsushita Electric Ind Co Ltd Multilayer resistance variable element array, resistance variable device, multilayer nonvolatile storage element array, and nonvolatile storage device
US20070290186A1 (en) 2006-05-04 2007-12-20 El Mostafa Bourim Non-volatile variable resistance memory device and method of fabricating the same
US20110033967A1 (en) 2006-06-04 2011-02-10 Markus Lutz Methods for trapping charge in a microelectromechanical system and microelectromechanical system employing same
JP2007328857A (en) 2006-06-07 2007-12-20 Sony Corp Storage device
US20070291527A1 (en) 2006-06-07 2007-12-20 Sony Corporation Memory apparatus
US20070297501A1 (en) 2006-06-08 2007-12-27 Via Technologies, Inc. Decoding Systems and Methods in Computational Core of Programmable Graphics Processing Unit
US20070295950A1 (en) 2006-06-27 2007-12-27 Samsung Electronics Co., Ltd. Variable resistance random access memory device and a method of fabricating the same
US7719001B2 (en) 2006-06-28 2010-05-18 Semiconductor Energy Laboratory Co., Ltd Semiconductor device with metal oxides and an organic compound
US20080006907A1 (en) 2006-07-06 2008-01-10 Samsung Electronics Co., Ltd Non-volatile memory device including a variable resistance material
US20080048164A1 (en) 2006-07-11 2008-02-28 Matsushita Electric Industrial Co., Ltd. Electro-resistance element, method of manufacturing the same and electro-resistance memory using the same
US20120122290A1 (en) 2006-07-14 2012-05-17 4D-S Pty Ltd. Systems and methods for fabricating self-aligned memory cell
US20080019163A1 (en) 2006-07-21 2008-01-24 Heinz Hoenigschmid Method and memory circuit for operating a resistive memory cell
US7499355B2 (en) 2006-07-31 2009-03-03 Sandisk 3D Llc High bandwidth one time field-programmable memory
US7515454B2 (en) 2006-08-02 2009-04-07 Infineon Technologies Ag CBRAM cell and CBRAM array, and method of operating thereof
CN101131872A (en) 2006-08-21 2008-02-27 奇梦达股份公司 Method of determining a memory state of a resistive memory cell and device measuring the memory state of a resistive memory cell
US20080043521A1 (en) 2006-08-21 2008-02-21 Corvin Liaw Method of determining a memory state of a resistive memory cell and device measuring the memory state of a resistive memory cell
US7869253B2 (en) 2006-08-21 2011-01-11 Qimonda Ag Method of determining a memory state of a resistive memory cell and device measuring the memory state of a resistive memory cell
US20100090192A1 (en) 2006-08-31 2010-04-15 Nxp, B.V. Method for controlled formation of the resistive switching material in a resistive switching device and device obtained thereof
US7772581B2 (en) 2006-09-11 2010-08-10 Macronix International Co., Ltd. Memory device having wide area phase change element and small electrode contact area
US20100067279A1 (en) 2006-09-19 2010-03-18 Byung-Gil Choi Semiconductor memory device using variable resistor
US7791060B2 (en) 2006-09-27 2010-09-07 Kabushiki Kaisha Toshiba Semiconductor memory device and method of controlling the same
KR20090051206A (en) 2006-09-29 2009-05-21 후지쯔 마이크로일렉트로닉스 가부시키가이샤 Nonvolatile semiconductor storage apparatus, reading method thereof, writing method thereof and erasing method thereof
US7920412B2 (en) 2006-09-29 2011-04-05 Kabushiki Kaisha Toshiba Magnetic random access memory and method of manufacturing the same
US20080090337A1 (en) 2006-10-03 2008-04-17 Williams R Stanley Electrically actuated switch
CN101501850A (en) 2006-10-16 2009-08-05 松下电器产业株式会社 Non-volatile storage device and method for manufacturing the same
US20080089110A1 (en) 2006-10-16 2008-04-17 Warren Robinett Crossbar-memory systems and methods for writing to and reading from crossbar memory junctions of crossbar-memory systems
US20090014707A1 (en) 2006-10-20 2009-01-15 Wei Lu Non-volatile solid state resistive switching devices
CN101170132A (en) 2006-10-27 2008-04-30 奇梦达股份公司 Modifiable gate stack memory element
US20080106925A1 (en) 2006-11-08 2008-05-08 Symetrix Corporation Correlated electron memory
US20080106926A1 (en) 2006-11-08 2008-05-08 Symetrix Corporation Non-volatile resistance switching memories and methods of making same
US7778063B2 (en) 2006-11-08 2010-08-17 Symetrix Corporation Non-volatile resistance switching memories and methods of making same
US7541252B2 (en) 2006-11-09 2009-06-02 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device including a self-aligned cell diode
US20100007937A1 (en) 2006-11-09 2010-01-14 Sage Electrochromics, Inc. Method of making an ion-switching device without a separate lithiation step
US7728318B2 (en) 2006-11-16 2010-06-01 Sandisk Corporation Nonvolatile phase change memory cell having a reduced contact area
US20090231905A1 (en) 2006-11-30 2009-09-17 Fujitsu Limited Nonvolatile semiconductor memory device, and writing method, reading method and erasing method of nonvolatile semiconductor memory device
US7786589B2 (en) 2006-12-06 2010-08-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing semiconductor device
JP2008147343A (en) 2006-12-08 2008-06-26 Sharp Corp Nonvolatile semiconductor memory
US20100046622A1 (en) 2006-12-14 2010-02-25 Thomson Licensing Method and apparatus for encoding and/or decoding bit depth scalable video data using adaptive enhancement layer residual prediction
US7881097B2 (en) 2006-12-26 2011-02-01 Sony Corporation Storage element and memory
US8018760B2 (en) 2006-12-28 2011-09-13 Panasonic Corporation Resistance variable element and resistance variable memory apparatus
US20080165571A1 (en) 2007-01-09 2008-07-10 Macronix International Co., Ltd. Method, Apparatus and Computer Program Product for Read Before Programming Process on Multiple Programmable Resistive Memory Cell
US7972897B2 (en) 2007-02-05 2011-07-05 Intermolecular, Inc. Methods for forming resistive switching memory elements
US20080185567A1 (en) 2007-02-05 2008-08-07 Nitin Kumar Methods for forming resistive switching memory elements
US20090014703A1 (en) 2007-02-07 2009-01-15 Tsuneo Inaba Semiconductor memory device
US8265136B2 (en) 2007-02-20 2012-09-11 Vixs Systems, Inc. Motion refinement engine for use in video encoding in accordance with a plurality of sub-pixel resolutions and methods for use therewith
US20080198934A1 (en) 2007-02-20 2008-08-21 Edward Hong Motion refinement engine for use in video encoding in accordance with a plurality of sub-pixel resolutions and methods for use therewith
US20080232160A1 (en) 2007-02-27 2008-09-25 International Business Machines Corporation Rectifying element for a crosspoint based memory array architecture
US7561461B2 (en) 2007-02-28 2009-07-14 Panasonic Corporation Non-volatile semiconductor memory device
US20080205179A1 (en) 2007-02-28 2008-08-28 Qimonda Ag Integrated circuit having a memory array
US7924138B2 (en) 2007-03-01 2011-04-12 Fujitsu Limited Semiconductor device and manufacturing method of the same
US7629198B2 (en) 2007-03-05 2009-12-08 Intermolecular, Inc. Methods for forming nonvolatile memory elements with resistive-switching metal oxides
US20080220601A1 (en) 2007-03-05 2008-09-11 Nitin Kumar Methods for forming nonvolatile memory elements with resistive-switching metal oxides
US20100110767A1 (en) 2007-03-13 2010-05-06 Yoshikazu Katoh Resistance variable memory apparatus
CN101636792A (en) 2007-03-13 2010-01-27 松下电器产业株式会社 Resistance-variable storage device
US7984776B2 (en) 2007-03-30 2011-07-26 The Regents Of The University Of Michigan Energy storage and control system for a vehicle electrified drivetrain
US8231998B2 (en) 2007-03-30 2012-07-31 The Regents Of The University Of Michigan Deposited microarchitectured battery and manufacturing method
US7704788B2 (en) 2007-04-06 2010-04-27 Samsung Electronics Co., Ltd. Methods of fabricating multi-bit phase-change memory devices and devices formed thereby
US20080278990A1 (en) 2007-05-09 2008-11-13 Pragati Kumar Resistive-switching nonvolatile memory elements
US8144498B2 (en) 2007-05-09 2012-03-27 Intermolecular, Inc. Resistive-switching nonvolatile memory elements
US20080278988A1 (en) 2007-05-09 2008-11-13 Klaus Ufert Resistive switching element
US8054674B2 (en) 2007-05-10 2011-11-08 Sharp Kabushiki Kaisha Variable resistive element, manufacturing method for same, and non-volatile semiconductor memory device
US20080301497A1 (en) 2007-06-04 2008-12-04 Silicon Motion, Inc. Testing Apparatus, System, and Method for Testing at Least One Device with a Connection Interface
US20080304312A1 (en) 2007-06-11 2008-12-11 Macronix International Co., Ltd. Resistance memory with tungsten compound and manufacturing
US20080311722A1 (en) 2007-06-15 2008-12-18 Sandisk 3D Llc Method for forming polycrystalline thin film bipolar transistors
US8054679B2 (en) 2007-06-19 2011-11-08 Elpida Memory Inc. Phase change memory device
US20090003717A1 (en) 2007-06-28 2009-01-01 Mitsubishi Electric Corporation Image encoding device, image decoding device, image encoding method and image decoding method
US7824956B2 (en) 2007-06-29 2010-11-02 Sandisk 3D Llc Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
US8233308B2 (en) 2007-06-29 2012-07-31 Sandisk 3D Llc Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same
US20090001345A1 (en) 2007-06-29 2009-01-01 April Schricker Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same
US20090001343A1 (en) 2007-06-29 2009-01-01 April Schricker Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same
WO2009005699A1 (en) 2007-06-29 2009-01-08 Sandisk 3D, Llc Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
US7566643B2 (en) 2007-07-23 2009-07-28 Ovonyx, Inc. Liquid phase deposition of contacts in programmable resistance and switching devices
US7764536B2 (en) 2007-08-07 2010-07-27 Grandis, Inc. Method and system for providing a sense amplifier and drive circuit for spin transfer torque magnetic random access memory
JP2009043873A (en) 2007-08-08 2009-02-26 Sony Corp Storage element and storage device
US20090052226A1 (en) 2007-08-24 2009-02-26 Samsung Electronics Co., Ltd Resistive random access memory device
US20090091981A1 (en) 2007-10-08 2009-04-09 Samsung Electronics Co., Ltd. Nonvolatile memory device with multiple page regions, and methods of reading and precharging the same
US20090095951A1 (en) 2007-10-12 2009-04-16 Ovonyx, Inc. Memory Device With Low Reset Current
US20090109728A1 (en) 2007-10-17 2009-04-30 Kabushiki Kaisha Toshiba Resistance change memory device
US20090141567A1 (en) 2007-11-09 2009-06-04 Kwang Jin Lee Semiconductor device having memory array, method of writing, and systems associated therewith
US20090122591A1 (en) 2007-11-14 2009-05-14 Qimonda North America Corporation Sense Amplifier Biasing Method and Apparatus
US7786464B2 (en) 2007-11-20 2010-08-31 Infineon Technologies Ag Integrated circuit having dielectric layer including nanocrystals
US20090134432A1 (en) 2007-11-22 2009-05-28 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
US20100221868A1 (en) 2007-12-04 2010-09-02 Regino Sandoval Active Material Devices with Containment Layer
US20090168486A1 (en) 2007-12-27 2009-07-02 Sandisk 3D Llc Large capacity one-time programmable memory cell using metal oxides
US7897953B2 (en) 2008-01-16 2011-03-01 Micron Technology, Inc. Multi-level programmable PCRAM memory
US8853759B2 (en) 2008-01-23 2014-10-07 Samsung Electronics Co., Ltd. Resistive memory devices and methods of manufacturing the same
US20110198557A1 (en) 2008-02-07 2011-08-18 International Business Machines Corporation Method for fabrication of crystalline diodes for resistive memories
US20120025161A1 (en) 2008-02-27 2012-02-02 Manuj Rathor Diode and resistive memory device structures
US7746696B1 (en) 2008-03-04 2010-06-29 Xilinx, Inc. CMOS twin cell non-volatile random access memory
US20090227067A1 (en) 2008-03-10 2009-09-10 Pragati Kumar Methods for Forming Resistive Switching Memory Elements by Heating Deposited Layers
US8143092B2 (en) 2008-03-10 2012-03-27 Pragati Kumar Methods for forming resistive switching memory elements by heating deposited layers
US8369139B2 (en) * 2008-03-11 2013-02-05 Micron Technology, Inc. Non-volatile memory with resistive access component
US20090231910A1 (en) * 2008-03-11 2009-09-17 Micron Technology, Inc. Non-volatile memory with resistive access component
US20090251941A1 (en) 2008-04-03 2009-10-08 Semiconductor Energy Labortory Co., Ltd. Semiconductor Device
US20090250787A1 (en) 2008-04-07 2009-10-08 Toshie Kutsunai Semiconductor storage device and manufacturing method of the same
US20090257265A1 (en) 2008-04-11 2009-10-15 Sandisk 3D Llc Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same
US20090256130A1 (en) 2008-04-11 2009-10-15 Sandisk 3D Llc Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element, and methods of forming the same
US7830698B2 (en) 2008-04-11 2010-11-09 Sandisk 3D Llc Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same
US7692959B2 (en) 2008-04-22 2010-04-06 International Business Machines Corporation Multilayer storage class memory using externally heated phase change material
US20090267047A1 (en) 2008-04-28 2009-10-29 Hitachi, Ltd. Semiconductor memory device and manufacturing method thereof
US20090268513A1 (en) 2008-04-29 2009-10-29 Luca De Ambroggi Memory device with different types of phase change memory
US20090272962A1 (en) 2008-05-01 2009-11-05 Pragati Kumar Reduction of forming voltage in semiconductor devices
US20110204312A1 (en) 2008-05-10 2011-08-25 Intermolecular, Inc. Confinement techniques for non-volatile resistive-switching memories
US8305793B2 (en) 2008-05-16 2012-11-06 Qimonda Ag Integrated circuit with an array of resistance changing memory cells
US20090283737A1 (en) 2008-05-19 2009-11-19 Masahiro Kiyotoshi Nonvolatile storage device and method for manufacturing same
US20100044798A1 (en) 2008-06-09 2010-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor device and a method of manufacturing the same
US20100321095A1 (en) 2008-06-10 2010-12-23 Takumi Mikawa Semiconductor device, manufacturing method of semiconductor device, semiconductor chip and system
US8587989B2 (en) 2008-06-20 2013-11-19 Nantero Inc. NRAM arrays with nanotube blocks, nanotube traces, and nanotube planes and methods of making same
US20090321706A1 (en) 2008-06-25 2009-12-31 Qimonda Ag Resistive Memory Devices with Improved Resistive Changing Elements
US20100219510A1 (en) 2008-06-30 2010-09-02 Sandisk 3D Llc Method for fabricating high density pillar structures by double patterning using positive photoresist
US20090321789A1 (en) 2008-06-30 2009-12-31 Sandisk 3D Llc Triangle two dimensional complementary patterning of pillars
US20100012914A1 (en) 2008-07-18 2010-01-21 Sandisk 3D Llc Carbon-based resistivity-switching materials and methods of forming the same
US20100019221A1 (en) 2008-07-22 2010-01-28 Macronix International Co., Ltd. Fully self-aligned pore-type memory cell having diode access device
US20100019310A1 (en) 2008-07-25 2010-01-28 Kabushiki Kaisha Toshiba Semiconductor memory device
US20100025675A1 (en) 2008-07-31 2010-02-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US20100032637A1 (en) 2008-08-06 2010-02-11 Hitachi, Ltd. Nonvolatile memory device and method of manufacturing the same
US20100032640A1 (en) 2008-08-07 2010-02-11 Sandisk 3D Llc Memory cell that includes a carbon-based memory element and methods of forming the same
US20100032638A1 (en) 2008-08-07 2010-02-11 Sandisk 3D Llc Memory cell that includes a carbon-based memory element and methods of forming the same
US20100038791A1 (en) 2008-08-12 2010-02-18 Industrial Technology Research Institute Resistive random access memory and method for fabricating the same
US20100039136A1 (en) 2008-08-15 2010-02-18 Qualcomm Incorporated Gate Level Reconfigurable Magnetic Logic
US20100044708A1 (en) 2008-08-19 2010-02-25 Chunghwa Picture Tubes, Ltd. Thin film transistor, pixel structure and fabrication methods thereof
WO2010026654A1 (en) 2008-09-05 2010-03-11 株式会社 東芝 Memory device
US20100067282A1 (en) 2008-09-18 2010-03-18 Seagate Technology Llc Memory array with read reference voltage cells
US7615439B1 (en) 2008-09-29 2009-11-10 Sandisk Corporation Damascene process for carbon memory element with MIIM diode
US20100084625A1 (en) 2008-10-02 2010-04-08 Guy Wicker Memory Device
WO2010042354A1 (en) 2008-10-06 2010-04-15 Sandisk 3D Llc Continuous programming of resistive memory using staggered precharge
JP2012504840A (en) 2008-10-06 2012-02-23 サンディスク スリーディー,エルエルシー Continuous programming of non-volatile memory
US20100085822A1 (en) 2008-10-06 2010-04-08 Tianhong Yan Continuous programming of non-volatile memory
WO2010042732A2 (en) 2008-10-08 2010-04-15 The Regents Of The University Of Michigan Silicon-based nanoscale resistive device with adjustable resistance
JP2012505551A (en) 2008-10-08 2012-03-01 ザ・リージェンツ・オブ・ザ・ユニバーシティ・オブ・ミシガンThe Regents Of The University Of Michigan Silicon nanoscale resistive element having an adjustable resistance
US20100085798A1 (en) 2008-10-08 2010-04-08 The Regents Of The University Of Michigan Silicon-based nanoscale resistive device with adjustable resistance
US20100102290A1 (en) 2008-10-20 2010-04-29 The Regents Of The University Of Michigan Silicon based nanoscale crossbar memory
US8071972B2 (en) 2008-10-20 2011-12-06 The Regents Of The University Of Michigan Silicon based nanoscale crossbar memory
US20100101290A1 (en) 2008-10-24 2010-04-29 Antonio Bertolotto Method for the production of an agent for treatment of agricultural soils
US7858468B2 (en) 2008-10-30 2010-12-28 Micron Technology, Inc. Memory devices and formation methods
US8097874B2 (en) 2008-10-30 2012-01-17 Seagate Technology Llc Programmable resistive memory cell with sacrificial metal
US20110299324A1 (en) 2008-10-31 2011-12-08 Seagate Technology Llc Write current compensation using word line boosting circuitry
US20110122679A1 (en) 2008-10-31 2011-05-26 Seagate Technology Llc Resistive Sense Memory Calibration for Self-Reference Read Method
US20100277969A1 (en) 2008-10-31 2010-11-04 Seagate Technology Llc. Structures for resistive random access memory cells
US7898838B2 (en) 2008-10-31 2011-03-01 Seagate Technology Llc Resistive sense memory calibration for self-reference read method
US20100118587A1 (en) 2008-11-12 2010-05-13 Seagate Technology Llc Resistive sense memory array with partial block update capability
US20100140614A1 (en) 2008-12-09 2010-06-10 Hitachi, Ltd. Oxide semiconductor device and method of manufacturing the same and active matrix substrate
US8067815B2 (en) 2008-12-11 2011-11-29 Macronix International Co., Lt.d. Aluminum copper oxide based memory devices and methods for manufacture
US20100157651A1 (en) 2008-12-18 2010-06-24 Sandisk 3D Llc Method of programming a nonvolatile memory device containing a carbon storage material
US20100157710A1 (en) 2008-12-19 2010-06-24 Unity Semiconductor Corporation Array Operation Using A Schottky Diode As a Non-Ohmic Isolation Device
US20100157656A1 (en) 2008-12-19 2010-06-24 Kabushiki Kaisha Toshiba Resistance change memory
US20100157659A1 (en) 2008-12-22 2010-06-24 Unity Semiconductor Corporation Digital potentiometer using third dimensional memory
US20100163828A1 (en) 2008-12-30 2010-07-01 Industrial Technology Research Institute Phase change memory devices and methods for fabricating the same
US20120001145A1 (en) 2008-12-31 2012-01-05 Michele Magistretti Avoiding degradation of chalcogenide material during definition of multilayer stack structure
US20100171086A1 (en) 2009-01-07 2010-07-08 Macronix International Co., Ltd. Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method
US20100176367A1 (en) 2009-01-12 2010-07-15 Micron Technology, Inc. Memory cell having dielectric memory element
US20100176368A1 (en) 2009-01-14 2010-07-15 Ko Nikka Method of manufacturing semiconductor memory device, and semiconductor memory device
US20100203731A1 (en) 2009-02-09 2010-08-12 Bob Kong Formation of a Zinc Passivation Layer on Titanium or Titanium Alloys Used in Semiconductor Processing
US8021897B2 (en) 2009-02-19 2011-09-20 Micron Technology, Inc. Methods of fabricating a cross point memory array
US20110151277A1 (en) 2009-02-23 2011-06-23 Panasonic Corporation Information recording medium
US8084830B2 (en) 2009-02-24 2011-12-27 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US20100237314A1 (en) 2009-03-19 2010-09-23 Takayuki Tsukamoto Resistance change type memory
US20100243983A1 (en) 2009-03-31 2010-09-30 Tony Chiang Controlled localized defect paths for resistive memories
US8183553B2 (en) 2009-04-10 2012-05-22 Intermolecular, Inc. Resistive switching memory element including doped silicon electrode
US20100258781A1 (en) 2009-04-10 2010-10-14 Prashant Phatak Resistive switching memory element including doped silicon electrode
US20100271885A1 (en) 2009-04-24 2010-10-28 Sandisk 3D Llc Reduced complexity array line drivers for 3D matrix arrays
US20120076203A1 (en) 2009-05-29 2012-03-29 Mitsubishi Electric Corporation Video encoding device, video decoding device, video encoding method, and video decoding method
CN102077296A (en) 2009-06-08 2011-05-25 松下电器产业株式会社 Forming method for resistance-change non-volatile memory element, and resistance-change non-volatile memory device
US20120120712A1 (en) 2009-06-08 2012-05-17 Ken Kawai Forming method for variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device
US8369129B2 (en) 2009-06-18 2013-02-05 Kabushiki Kaisha Toshiba Semiconductor memory device with variable resistance element
US20120147657A1 (en) 2009-06-19 2012-06-14 Sekar Deepak C Programming reversible resistance switching elements
WO2011005266A1 (en) 2009-07-10 2011-01-13 Hewlett-Packard Development Company, L.P. Memristive junction with intrinsic rectifier
JP2012533195A (en) 2009-07-13 2012-12-20 シーゲイト テクノロジー エルエルシー Nonvolatile memory cell having a non-ohmic selection layer
US20110007551A1 (en) 2009-07-13 2011-01-13 Seagate Technology Llc Non-Volatile Memory Cell with Non-Ohmic Selection Layer
US20110006275A1 (en) 2009-07-13 2011-01-13 Seagate Technology Llc Non-volatile resistive sense memory
WO2011008654A1 (en) 2009-07-13 2011-01-20 Seagate Technology Llc Non-volatile memory cell with non-ohmic selection layer
JP2011023645A (en) * 2009-07-17 2011-02-03 Sharp Corp Semiconductor storage element using nonvolatile variable-resistance element
CN102024494A (en) 2009-09-11 2011-04-20 中芯国际集成电路制造(上海)有限公司 Green transistor, resistive random access memory and drive method thereof
US20110063888A1 (en) 2009-09-11 2011-03-17 Semiconductor Manufacturing International (Shanghai) Corporation Green Transistor for Resistive Random Access Memory and Method of Operating the Same
US8207064B2 (en) 2009-09-17 2012-06-26 Sandisk 3D Llc 3D polysilicon diode with low contact resistance and method for forming same
US20110066878A1 (en) 2009-09-17 2011-03-17 Kabushiki Kaisha Toshiba Non-volatile semiconductor storage device
JP2011065737A (en) 2009-09-18 2011-03-31 Toshiba Corp Resistance change memory
US20110069533A1 (en) 2009-09-18 2011-03-24 Kurosawa Tomonori Resistance change memory and control method thereof
US20110068373A1 (en) 2009-09-24 2011-03-24 Kabushiki Kaisha Toshiba Semiconductor memory device
US20110089391A1 (en) 2009-10-20 2011-04-21 Andrei Mihnea Punch-through diode steering element
US8274130B2 (en) 2009-10-20 2012-09-25 Sandisk 3D Llc Punch-through diode steering element
US20120044751A1 (en) 2009-10-28 2012-02-23 Intermolecular, Inc. Bipolar resistive-switching memory with a single diode per memory cell
US20110128779A1 (en) 2009-11-30 2011-06-02 Andrea Redaelli Memory including a selector switch on a variable resistance memory cell
US20110136327A1 (en) 2009-12-03 2011-06-09 Applied Materials, Inc. High mobility monolithic p-i-n diodes
US20110133149A1 (en) 2009-12-04 2011-06-09 Sonehara Takeshi Resistance change memory and manufacturing method thereof
US20130264535A1 (en) 2009-12-04 2013-10-10 Kabushiki Kaisha Toshiba Resistance change memory and manufacturing method thereof
US8385100B2 (en) 2009-12-08 2013-02-26 Intel Corporation Energy-efficient set write of phase change memory with switch
US8045364B2 (en) 2009-12-18 2011-10-25 Unity Semiconductor Corporation Non-volatile memory device ion barrier
US20110155991A1 (en) 2009-12-29 2011-06-30 Industrial Technology Research Institute Resistive memory device and fabricating method thereof
US20110183525A1 (en) 2010-01-27 2011-07-28 International Business Machines Corporation Homogeneous Porous Low Dielectric Constant Materials
US20110193051A1 (en) 2010-02-08 2011-08-11 Samsung Electronics Co., Ltd. Resistance memory devices and methods of forming the same
US20110194329A1 (en) 2010-02-09 2011-08-11 Sony Corporation Memory component, memory device, and method of operating memory device
US20110205780A1 (en) 2010-02-19 2011-08-25 Shinichi Yasuda Semiconductor Integrated Circuit
US20110205782A1 (en) 2010-02-23 2011-08-25 Xiying Chen Costa Step soft program for reversible resistivity-switching elements
US8237146B2 (en) 2010-02-24 2012-08-07 Sandisk 3D Llc Memory cell with silicon-containing carbon switching layer and methods for forming the same
US20110212616A1 (en) 2010-02-26 2011-09-01 Robert Seidel Metallization system of a semiconductor device comprising rounded interconnects formed by hard mask rounding
US20110227028A1 (en) 2010-03-16 2011-09-22 Deepak Chandra Sekar Bottom electrodes for use with metal oxide resistivity switching layers
WO2011133138A1 (en) 2010-04-19 2011-10-27 Hewlett-Packard Development Company, L.P. Nanoscale switching devices with partially oxidized electrodes
US20130026440A1 (en) 2010-04-19 2013-01-31 Jianhua Yang Nanoscale switching devices with partially oxidized electrodes
US8999811B2 (en) 2010-05-21 2015-04-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20110284814A1 (en) 2010-05-24 2011-11-24 Guobiao Zhang Large Bit-Per-Cell Three-Dimensional Mask-Programmable Read-Only Memory
US20130065066A1 (en) 2010-05-27 2013-03-14 Applied Thin Films, Inc. Protective coatings for substrates having an active surface
US8441835B2 (en) 2010-06-11 2013-05-14 Crossbar, Inc. Interface control for improved switching in RRAM
US20110312151A1 (en) 2010-06-11 2011-12-22 Crossbar Inc. Pillar structure for memory device and method
US20120220100A1 (en) 2010-06-11 2012-08-30 Crossbar Inc. Pillar structure for memory device and method
US20110305064A1 (en) 2010-06-11 2011-12-15 Crossbar, Inc. Interface control for improved switching in rram
US8198144B2 (en) 2010-06-11 2012-06-12 Crossbar, Inc. Pillar structure for memory device and method
US8274812B2 (en) 2010-06-14 2012-09-25 Crossbar, Inc. Write and erase scheme for resistive memory device
US20120320660A1 (en) 2010-06-14 2012-12-20 Crossbar, Inc. Write and erase scheme for resistive memory device
US20110310656A1 (en) 2010-06-18 2011-12-22 Franz Kreupl Memory Cell With Resistance-Switching Layers Including Breakdown Layer
US20120176831A1 (en) 2010-06-18 2012-07-12 Li Xiao Resistive Random Access Memory With Low Current Operation
US20120001146A1 (en) 2010-06-24 2012-01-05 The Regents Of The University Of Michigan Nanoscale metal oxide resistive switching element
US8351241B2 (en) 2010-06-24 2013-01-08 The Regents Of The University Of Michigan Rectification element and method for resistive switching for non volatile memory device
US20110317470A1 (en) * 2010-06-24 2011-12-29 The Regents Of The University Of Michigan Rectification element and method for resistive switching for non volatile memory device
US20120104351A1 (en) 2010-07-01 2012-05-03 Zhiqiang Wei Non-volatile memory cell, non-volatile memory cell array, and method of manufacturing the same
US20130134379A1 (en) 2010-07-09 2013-05-30 Crossbar, Inc. Resistive memory using sige material
US8374018B2 (en) 2010-07-09 2013-02-12 Crossbar, Inc. Resistive memory using SiGe material
EP2405441A1 (en) 2010-07-09 2012-01-11 Crossbar, Inc. Resistive memory using SiGe material
US20120008366A1 (en) 2010-07-09 2012-01-12 Crossbar, Inc. RESTIVE MEMORY USING SiGe MATERIAL
US20120007035A1 (en) 2010-07-12 2012-01-12 Crossbar, Inc. Intrinsic Programming Current Control for a RRAM
EP2408035A2 (en) 2010-07-13 2012-01-18 Crossbar, Inc. Two terminal resistive switching device structure and method of fabricating
US20120015506A1 (en) 2010-07-13 2012-01-19 Crossbar, Inc. Two terminal resistive switching device structure and method of fabricating
US20120012806A1 (en) 2010-07-13 2012-01-19 Crossbar, Inc. Improved on/off ratio for non-volatile memory device and method
US8168506B2 (en) 2010-07-13 2012-05-01 Crossbar, Inc. On/off ratio for non-volatile memory device and method
US20120033479A1 (en) 2010-08-06 2012-02-09 Lsi Corporation Modification of logic by morphological manipulation of a semiconductor resistive element
US20120043654A1 (en) 2010-08-19 2012-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
US20120043621A1 (en) 2010-08-23 2012-02-23 Crossbar, Inc. Stackable non-volatile resistive switching memory device and method
US20120043519A1 (en) 2010-08-23 2012-02-23 Crossbar, Inc. Device switching using layered device structure
US8659003B2 (en) 2010-08-23 2014-02-25 Crossbar, Inc. Disturb-resistant non-volatile memory device and method
US20120043520A1 (en) 2010-08-23 2012-02-23 Crossbar, Inc. Disturb-resistant non-volatile memory device and method
US20120074374A1 (en) 2010-09-29 2012-03-29 Crossbar, Inc. Conductive path in switching material in a resistive random access memory device and control
US20120074507A1 (en) 2010-09-29 2012-03-29 Crossbar, Inc. Integration of an amorphous silicon resistive switching device
US8456892B2 (en) 2010-09-29 2013-06-04 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US8315079B2 (en) 2010-10-07 2012-11-20 Crossbar, Inc. Circuit for concurrent read operation and method therefor
US20120087169A1 (en) 2010-10-07 2012-04-12 Crossbar, Inc. Circuit for concurrent read operation and method therefor
US8675384B2 (en) 2010-10-07 2014-03-18 Crossbar, Inc. Circuit for concurrent read operation and method therefor
US20120087172A1 (en) 2010-10-12 2012-04-12 Fujitsu Limited Semiconductor memory and system
US8389971B2 (en) 2010-10-14 2013-03-05 Sandisk 3D Llc Memory cells having storage elements that share material layers with steering elements and methods of forming the same
JP2012089567A (en) 2010-10-15 2012-05-10 Toshiba Corp Non-volatile resistance change element
US20120091420A1 (en) 2010-10-15 2012-04-19 Kabushiki Kaisha Toshiba Nonvolatile resistance change device
US20120269275A1 (en) 2010-10-20 2012-10-25 Nokia Corporation Method and device for video coding and decoding
US8187945B2 (en) 2010-10-27 2012-05-29 Crossbar, Inc. Method for obtaining smooth, continuous silver film
US20120252183A1 (en) 2010-10-27 2012-10-04 Crossbar, Inc. Method for obtaining smooth, continuous silver film
US20120108030A1 (en) 2010-10-27 2012-05-03 Crossbar, Inc. Method for obtaining smooth, continuous silver film
US8258020B2 (en) 2010-11-04 2012-09-04 Crossbar Inc. Interconnects for stacked non-volatile memory device and method
US8467227B1 (en) 2010-11-04 2013-06-18 Crossbar, Inc. Hetero resistive switching material layer in RRAM device and method
US8399307B2 (en) 2010-11-04 2013-03-19 Crossbar, Inc. Interconnects for stacked non-volatile memory device and method
US20130308369A1 (en) 2010-11-04 2013-11-21 Crossbar, Inc. Switching device having a non-linear element
US8947908B2 (en) 2010-11-04 2015-02-03 Crossbar, Inc. Hetero-switching layer in a RRAM device and method
US20130279240A1 (en) 2010-11-04 2013-10-24 Crossbar, Inc. Hetero-switching layer in a rram device and method
US20120142163A1 (en) 2010-11-05 2012-06-07 Crossbar Inc. P+ polysilicon material on aluminum for non-volatile memory device and method
US8088688B1 (en) 2010-11-05 2012-01-03 Crossbar, Inc. p+ polysilicon material on aluminum for non-volatile memory device and method
KR20110014248A (en) 2010-11-28 2011-02-10 손정삼 A driver to set up lighting slab at night throngh solar panel
US20120235112A1 (en) 2010-11-30 2012-09-20 Huo Zongliang Resistive switching memory and method for manufacturing the same
US20120140816A1 (en) 2010-12-01 2012-06-07 Jean-Francois Franche Method and system for parallel encoding of a video
US20120145984A1 (en) 2010-12-13 2012-06-14 Peter Rabkin Punch-through diode
US20120155146A1 (en) 2010-12-20 2012-06-21 Yoshihiro Ueda Resistance-change memory
US8467226B2 (en) 2011-01-14 2013-06-18 Micron Technology, Inc. Programming an array of resistance random access memory cells using unipolar pulses
US20130119341A1 (en) 2011-01-27 2013-05-16 Institute of Microelectronics, Chinese Academy of Sciences Resistive random access memory cell and memory
US20120205793A1 (en) 2011-02-10 2012-08-16 Applied Materials, Inc. Seed layer passivation
US20120205606A1 (en) 2011-02-14 2012-08-16 Dongguk University Industry-Academic Cooperation Foundation Nonvolatile Memory Device Using The Resistive Switching of Graphene Oxide And The Fabrication Method Thereof
US20120218807A1 (en) 2011-02-25 2012-08-30 Micron Technology, Inc. Resistive memory sensing methods and devices
US20120224413A1 (en) 2011-03-02 2012-09-06 Jingyan Zhang Non-Volatile Storage System Using Opposite Polarity Programming Signals For MIM Memory Cell
US8320160B2 (en) 2011-03-18 2012-11-27 Crossbar, Inc. NAND architecture having a resistive memory cell connected to a control gate of a field-effect transistor
US20120236625A1 (en) 2011-03-18 2012-09-20 Sony Corporation Memory element and memory device
US20120241710A1 (en) 2011-03-21 2012-09-27 Nanyang Technological University Fabrication of RRAM Cell Using CMOS Compatible Processes
US20120243292A1 (en) 2011-03-22 2012-09-27 Akira Takashima Memory device
US20120250183A1 (en) 2011-03-31 2012-10-04 Nidec Corporation Motor and storage disk drive
US8394670B2 (en) 2011-05-31 2013-03-12 Crossbar, Inc. Vertical diodes for non-volatile memory device
US20120305879A1 (en) 2011-05-31 2012-12-06 Crossbar, Inc. Switching device having a non-linear element
US20120305874A1 (en) 2011-05-31 2012-12-06 Crossbar, Inc. Vertical Diodes for Non-Volatile Memory Device
US8502185B2 (en) 2011-05-31 2013-08-06 Crossbar, Inc. Switching device having a non-linear element
US20150228334A1 (en) 2011-05-31 2015-08-13 Crossbar, Inc. Memory array architecture with two-terminal memory cells
US8619459B1 (en) 2011-06-23 2013-12-31 Crossbar, Inc. High operating speed resistive random access memory
US20120327701A1 (en) 2011-06-23 2012-12-27 Crossbar, Inc. Memory array architecture with two-terminal memory cells
US20120326265A1 (en) 2011-06-24 2012-12-27 International Business Machines Corporation Method of forming memory cell access device
US9166163B2 (en) 2011-06-30 2015-10-20 Crossbar, Inc. Sub-oxide interface layer for two-terminal memory
US20140145135A1 (en) 2011-06-30 2014-05-29 Crossbar, Inc. Sub-oxide interface layer for two-terminal memory
US20140312296A1 (en) 2011-06-30 2014-10-23 Crossbar, Inc. Three-dimensional oblique two-terminal memory with enhanced electric field
US8934294B2 (en) 2011-07-13 2015-01-13 SK Hynix Inc. Semiconductor integrated circuit device, method of manufacturing the same, and method of driving the same
US8693241B2 (en) 2011-07-13 2014-04-08 SK Hynix Inc. Semiconductor intergrated circuit device, method of manufacturing the same, and method of driving the same
US20130020548A1 (en) 2011-07-22 2013-01-24 Crossbar, Inc. Seed layer for a p+ silicon germanium material for a non-volatile memory device and method
US20130023085A1 (en) 2011-07-22 2013-01-24 Intermolecular, Inc. Method for forming metal oxides and silicides in a memory device
US8466005B2 (en) 2011-07-22 2013-06-18 Intermolecular, Inc. Method for forming metal oxides and silicides in a memory device
US20130075685A1 (en) 2011-09-22 2013-03-28 Yubao Li Methods and apparatus for including an air gap in carbon-based memory devices
US20130075688A1 (en) 2011-09-27 2013-03-28 Semiconductor Manufacturing International Corporation Semiconductor Memory Device and Manufacturing Method Thereof
US20130166825A1 (en) 2011-12-27 2013-06-27 Jin Yeong Kim Method Of Controlling Non-Volatile Memory, Non-Volatile Memory Controller Therefor, And Memory System Including The Same
US20140103284A1 (en) 2012-02-07 2014-04-17 Intermolecular Inc. ReRAM Cells Including TaXSiYN Embedded Resistors
US8569104B2 (en) 2012-02-07 2013-10-29 Intermolecular, Inc. Transition metal oxide bilayers
US20130207065A1 (en) 2012-02-14 2013-08-15 Intermolecular, Inc. Bipolar multistate nonvolatile memory
US20130214234A1 (en) 2012-02-22 2013-08-22 Adesto Technologies Corporation Resistive Switching Devices and Methods of Formation Thereof
US20130235648A1 (en) 2012-03-12 2013-09-12 Samsung Semiconductor Co., Ltd. Resistive memory device and related method of operation
US20140192589A1 (en) 2012-04-13 2014-07-10 Crossbar, Inc. Reduced diffusion in metal electrode for two-terminal memory
US8946667B1 (en) 2012-04-13 2015-02-03 Crossbar, Inc. Barrier structure for a silver based RRAM and method
US8658476B1 (en) 2012-04-20 2014-02-25 Crossbar, Inc. Low temperature P+ polycrystalline silicon material for non-volatile memory device
US20140015018A1 (en) 2012-07-12 2014-01-16 SK Hynix Inc. Semiconductor device and method of fabricating the same
US20140029327A1 (en) 2012-07-24 2014-01-30 John Paul Strachan Bipolar resistive switch heat mitigation
US8946673B1 (en) 2012-08-24 2015-02-03 Crossbar, Inc. Resistive switching device structure with improved data retention for non-volatile memory device and method
US20140070160A1 (en) 2012-09-07 2014-03-13 Takayuki Ishikawa Nonvolatile memory device
US20140166961A1 (en) 2012-12-14 2014-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Resistive random access memory (rram) and method of making
US20140175360A1 (en) 2012-12-20 2014-06-26 Intermolecular Inc. Bilayered Oxide Structures for ReRAM Cells
US20140177315A1 (en) 2012-12-20 2014-06-26 Intermolecular Inc. Multi-Level Memory Array Having Resistive Elements For Multi-Bit Data Storage
US20140197369A1 (en) 2013-01-16 2014-07-17 Hewlett-Packard Development Company, L.P. Nanoparticle-based memristor structure
US20140233294A1 (en) 2013-02-21 2014-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Memory Cell with Decoupled Read/Write Path
US20140268998A1 (en) 2013-03-14 2014-09-18 Crossbar, Inc. Rram with dual mode operation
US20140264250A1 (en) 2013-03-14 2014-09-18 Crossbar, Inc. Low temperature in-situ doped silicon-based conductor material for memory cell
US20140269002A1 (en) 2013-03-14 2014-09-18 Crossbar, Inc. Two-terminal memory with intrinsic rectifying characteristic
US9093635B2 (en) 2013-03-14 2015-07-28 Crossbar, Inc. Controlling on-state current for two-terminal memory
US20140264236A1 (en) 2013-03-14 2014-09-18 Crossbar, Inc. Controlling on-state current for two-terminal memory
US20140268997A1 (en) 2013-03-15 2014-09-18 Crossbar, Inc. Programming two-terminal memory cells with reduced program current
US20140335675A1 (en) 2013-05-08 2014-11-13 Crossbar, Inc. Regulating interface layer growth with n2o for two-terminal memory
US20150070961A1 (en) 2013-09-06 2015-03-12 Kabushiki Kaisha Toshiba Semiconductor storage device
US20160111640A1 (en) 2014-10-15 2016-04-21 National Sun Yat-Sen University Resistive random access memory

Non-Patent Citations (327)

* Cited by examiner, † Cited by third party
Title
Advisory Action mailed Jun. 8, 2012 for U.S. Appl. No. 12/835,704, filed Jul. 13, 2010.
Avila A., et al., "Switching in Coplanar Amorphous Hydrogenated Silicon Devices," Solid-State Electronics, 2000, vol. 44 (1), pp. 17-27.
Cagli C., et al., "Evidence for Threshold Switching in the Set Process of Nio-based Rram and Physical Modeling for Set, Reset, Retention and Disturb Prediction", 2008 IEEE International Electron Devices Meeting (IEDM), Dec. 15-17, 2008, pp. 1-4, San Francisco, CA, USA.
Chang P.H., et al., "Aluminum Spiking at Contact Windows in Al/Ti-W/Si," Applied Physics Letters, 1988, vol. 52 (4), pp. 272-274.
Chen Y., et al., "Nanoscale Molecular-switch Crossbar Circuits," Nanotechnology, 2003, vol. 14, pp. 462-468.
Chinese Office Action (English Translation) for Chinese Application No. 201110195933.7 dated Jul. 31, 2014, 4 pages.
Chinese Office Action (English Translation) for Chinese Application No. 201110195933.7 dated May 18, 2015, 4 pages.
Chinese Office Action (English Translation) for Chinese Application No. 201180050941.0 dated Apr. 3, 2015, 8 pages.
Chinese Office Action (English Translation) for Chinese Application No. 201180050941.0 dated Dec. 9, 2015, 5 pages.
Chinese Office Action (English Translation) for Chinese Application No. 201280027066.9 dated Nov. 23, 2015, 6 pages.
Chinese Office Action (with English Translation) for Chinese Application No. 201280027066.9 mailed on Jul. 4, 2016, 5 pages.
Chinese Office Action (with English Translation) for Chinese Application No. 201290000773.4 dated Jun. 9, 2014, 3 pages.
Chinese Office Action mailed on Sep. 1, 2016 for Chinese Application No. 201380027469.8, 8 pages (including translation).
Chinese Seach Report (English Translation) for Chinese Application No. 201180050941.0 dated Mar. 25, 2015, 1 page.
Chinese Search Report (English Translation) for Chinese Application No. 201280027066.9 dated Nov. 13, 2015, 2 pages.
Choi J.W., "Bistable [2]Rotaxane Based Molecular Electronics: Fundamentals and Applications", Dissertation, Chapter 3, California Institute of Technology, Pasadena, 2007, pp. 79-120. Retrieved from the Internet.
Chou S.Y., et al., "Imprint Lithography With 25-Nanometer Resolution," Science, 1996, vol. 272, pp. 85-87.
Collier C.P., et al., "Electronically Configurable Molecular-based Logic Gates," Science, 1999, vol. 285 (5426), pp. 391-395.
Corrected Notice of Allowability dated Dec. 6, 2016 for U.S. Appl. No. 14/383,079, 33 pages.
Corrected Notice of Allowability dated Jun. 15, 2016 for U.S. Appl. No. 13/952,467, 10 pages.
Corrected Notice of Allowability dated Nov. 20, 2014 for U.S. Appl. No. 13/594,665, 5 pages.
Corrected Notice of Allowability mailed Oct. 1, 2013 for U.S. Appl. No. 13/733,828, filed Jan. 3, 2013.
Corrected Notice of Allowance mailed Jan. 11, 2013 for U.S. Appl. No. 12/861,666 dated Aug. 23, 2010.
Dehon A., "Array-Based Architecture for FET-Based, Nanoscale Electronics," IEEE Transactions on Nanotechnology, 2003, vol. 2 (1), pp. 23-32.
Del Alamo J., et al., "Operating limits of Al-alloyed High-low Junction for BSF Solar Cells," Solid-State Electronics, 1981, vol. 24, pp. 415-420.
Den Boer W., "Threshold Switching in Hydrogenated Amorphous Silicon," Applied Physics Letters, 1982, vol. 40, pp. 812-813.
Dey S.K., "Electrothermal Model of Switching in Amorphous Silicon Films," Journal of Vacuum Science & Technology, 1980, vol. 17 (1), pp. 445-448.
Dong Y., et al., "Si/a-Si Core/Shell Nanowires as Nonvolatile Crossbar Switches," Nano Letters, 2008, vol. 8 (2), pp. 386-391.
European Search Report for Application No. EP09819890.6 mailed on Mar. 27 , 2012.
European Search Report for Application No. EP11005207.3 mailed on Oct. 12, 2011.
European Search Report for Application No. EP14000949, mailed on Jun. 4, 2014, 7 pages.
European Search Report for European Application No. EP11005649 mailed Oct. 15, 2014, 2 pages.
Ex parte Quayle Action mailed May 8, 2012 for U.S. Appl. No. 12/826,653, filed Jun. 29, 2010.
Final Office Action dated Jun. 29, 2016 for U.S. Appl. No. 14/692,677, 21 pages.
Final Office Action mailed Aug. 13, 2014 for U.S. Appl. No. 13/525,096, filed Jun. 15, 2012.
Final Office Action mailed Feb. 1, 2016 for U.S. Appl. No. 14/573,817.
Final Office Action mailed May 20, 2016 for U.S. Appl. No. 14/253,796.
Gangopadhyay S., et al., "Memory Switching in Sputtered Hydrogenated Amorphous Silicon (a-Si:H)," Japanese Journal of Applied Physics, 1985, vol. 24 (10), pp. 1363-1364.
Goronkin H., et al., High-Performance Emerging Solid-State Memory Technologies, MRS Bulletin, Nov. 2004, pp. 805-813. Retrieved from the Internet.
Hajto J., et al., "Amorphous & Microcrystalline Semiconductor Devices: Materials and Device Physics", Artech House Publishers, Mar. 1, 2004, vol. 2, pp. 640-700.
Hajto J., et al., "Analogue Memory and Ballistic Electron Effects in Metal-amorphous Silicon Structures," Philosophical Magazine, 1991, vol. 63 (1), pp. 349-369.
Hajto J., et al., "Electronic Switching in Amorphous-Semiconductor Thin Films", Chapter 14, 1992, pp. 640-701.
Hajto J., et al., "The Programmability of Amorphous Silicon Analogue Memory Elements," Materials Research Society Symposium Proceedings, 1990, vol. 192, pp. 405-410.
Holmes A.J., et al., "Design of Analogue Synapse Circuits using Non-Volatile a-Si:H Memory Devices", Proceedings of IEEE International Symposium on Circuits and System, 1994, pp. 351-354, vol. 6.
Hu J., et al., "AC Characteristics of Cr/p. sup.+a-Si:H/V Analog Switching Devices," IEEE Transactions on Electron Devices, 2000, vol. 47 (9), pp. 1751-1757.
Hu X.Y., et al., "Write Amplification Analysis in Flash-based Solid State Drives", Systor'09; 20090504-20090406, May 4, 2009, pp. 1-9.
Hudgens S., et al., "Overview of Phase-Change Chalcogenide Nonvolatile Memory Technology", MRS Bulletin, Nov. 2004, pp. 829-832. Retrieved from the Internet.
International Search Report and Written Opinion for Application No. PCT/US2011/040362, mailed on Jan. 19, 2012, 7 pages.
International Search Report and Written Opinion for Application No. PCT/US2011/046035, mailed on Mar. 27, 2012, 6 pages.
International Search Report and Written Opinion for Application No. PCT/US2012/040242, mailed on Jan. 31, 2013, 9 pages.
International Search Report and Written Opinion for Application No. PCT/US2012/044077, mailed on Jan. 25, 2013, 3 pages.
International Search Report and Written Opinion for Application No. PCT/US2012/045312, mailed on Mar. 29, 2013, 11 pages.
International Search Report and Written Opinion for Application No. PCT/US2013/042746, mailed on Sep. 6, 2013, 7 pages.
International Search Report and Written Opinion for Application No. PCT/US2013/061244, mailed on Jan. 28, 2014, 3 pages.
International Search Report and Written Opinion for Application No. PCT/US2013/077628, mailed on Apr. 29, 2014, 12 pages.
International Search Report and Written Opinion for PCT Patent Application No. PCT/US2012/040232 filed on May 31, 2012.
International Search Report and Written Opinion for PCT Patent Application No. PCT/US2013/054976, filed on Aug. 14, 2013.
International Search Report for Application no. PCT/US2009/060023, mailed on May 18, 2010, 3 pages.
International Search Report for Application No. PCT/US2009/061249, mailed on May 19, 2010, 3 pages.
International Search Report for Application No. PCT/US2011/040090, mailed on Feb. 17, 2012, 5 pages.
International Search Report for Application No. PCT/US2011/045124, mailed on May 29, 2012, 3 pages.
International Search Report for Application No. PCT/US2011/046036, mailed on Feb. 23, 2012, 3 pages.
Jafar M., et al., "Switching in Amorphous-silicon Devices," Physical Review, 1994, vol. 49 (19), pp. 611-615.
Japanese Office Action (English Translation) for Japanese Application No. 2011-153349 mailed Feb. 24, 2015, 3 pages.
Japanese Office Action (English Translation) for Japanese Application No. 2013-525926 mailed Mar. 3, 2015, 4 pages.
Japanese Office Action (English Translation) for Japanese Application No. 2014-513700 mailed Jan. 12, 2016, 4 pages.
Japanese Office Action and English Translation for Japanese Patent Application No. 2011-153349 mailed Feb. 24, 2015, 9 pages.
Japanese Office Action and English Translation for Japanese Patent Application No. 2011-153349 mailed Mar. 24, 2015, 9 pages.
Japanese Office Action mailed on Aug. 9, 2016 for Japanese Application No. 2014-513700, 8 pages (including translation).
Japanese Search Report (English Translation) for Japanese Application No. 2011-153349 dated Feb. 9, 2015, 11 pages.
Japanese Search Report (English Translation) for Japanese Application No. 2013-525926 dated Feb. 9, 2015, 15 pages.
Japanese Search Report (English Translation) for Japanese Application No. 2014-513700 dated Jan. 14, 2016, 25 pages.
Jian Fill, et al., "Area-Dependent Switching in Thin Film-Silicon Devices," Materials Research Society Symposium Proceedings, 2003, vol. 762, pp. A 18.3.1-A 18.3.6.
Jian Fill, et al., "Switching and Filament Formation in hot-wire CVD p-type a-Si:H devices," Thin Solid Films, Science Direct, 2003, vol. 430, pp. 249-252.
Jo S.H. et al., "High-Density Crossbar Arrays Based on a Si Memristive System", Supporting Information, 2009, pp. 1-4.
Jo S.H., et al., "A Silicon-Based Crossbar Ultra-High-Density Non-Volatile Memory", SSEL Annual Report, 2007.
Jo S.H., et al., "Ag/a-Si:1-1/c-Si Resistive Switching Nonvolatile Memory Devices," Nanotechnology Materials and Devices Conference, 2006, vol. 1, pp. 116-117.
Jo S.H., et al., "CMOS Compatible Nanoscale Nonvolatile Resistance Switching Memory," Nano Letters, 2008, vol. 8 (2), pp. 392-397.
Jo S.H., et al., "Experimental, Modeling and Simulation Studies of Nanoscale Resistance Switching Devices", 9.sup.th Conference on Nanotechnology, IEEE, 2009, pp. 493-495.
Jo S.H., et al., "High-Density Crossbar Arrays Based on a Si Memristive System," Nano Letters, 2009, vol. 9 (2), pp. 870-874.
Jo S.H., et al., "Nanoscale Memristive Devices for Memory and Logic Applications", Ph. D Dissertation, University of Michigan, 2010.
Jo S.H., et al., "Nanoscale Memristor Device as Synapse in Neuromorphic Systems," Nano Letters, 2010, vol. 10, pp. 1297-1301.
Jo S.H., et al., "Nonvolatile Resistive Switching Devices Based on Nanoscale Metal/Amorphous Silicon/Crystalline Silicon Junctions," Materials Research Society Symposium Proceedings, 2007, vol. 997.
Jo S.H., et al., "Programmable Resistance Switching in Nanoscale Two-Terminal Devices," Nano Letters, 2009, vol. 9 (1), pp. 496-500.
Jo S.H., et al., "Programmable Resistance Switching in Nanoscale Two-Terminal Devices," Supporting Information, 2009, pp. 1-4.
Jo S.H., et al., "Si Memristive Devices Applied to Memory and Neuromorphic Circuits", Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010, pp. 13-16.
Jo S.H., et al., "Si-Based Two-Terminal Resistive Switching Nonvolatile Memory", IEEE, 2008.
Kuk-H Wan Kim et al., "Nanoscale Resistive Memory with Intrinsic Diode Characteristics and Long Endurance," Applied Physics Letters, 2010, vol. 96, pp. 053106-1-053106-3.
Kund M., et al., "Conductive Bridging Ram (cbram): An Emerging Non-volatile Memory Technology Scalable to Sub 20nm", IEEE, 2005.
Le Comber P.G., "Present and Future Applications of Amorphous Silicon and Its Alloys," Journal of Non-Crystalline Solids, 1989, vol. 115, pp. 1-13.
Le Comber P.G., et al., "The Switching Mechanism in Amorphous Silicon Junctions," Journal of Non-Crystalline Solids, 1985, vol. 77 & 78, pp. 1373-1382.
Lee S.H., et al., "Full Integration and Cell Characteristics for 64Mb Nonvolatile PRAM", 2004 Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2004, pp. 20-21.
Liu M., et al., "rFGA: CMOS-Nano Hybrid FPGA Using RRAM Components", IEEE CB3 N171ntemational Symposium on Nanoscale Architectures, Anaheim, USA, Jun. 12-13, 2008, pp. 93-98.
Lu W., et al., "Nanoelectronics from the Bottom Up," Nature Materials, 2007, vol. 6, pp. 841-850.
Lu W., et al., "Supporting Information", 2008.
Marand, "Materials Engineering Science," MESc. 5025 Lecture Notes: Chapter 7. Diffusion, University of Vermont. Retrieved from the Internet on Aug. 8, 2016.
Moopenn A. et al., "Programmable Synaptic Devices for Electronic Neural Nets," Control and Computers, 1990, vol. 18 (2), pp. 37-41.
Muller D.A., et al., "The Electronic Structure at the Atomic Scale of Ultrathin Gate Oxides," Nature, 1999, vol. 399, pp. 758-761.
Muller G., et al., "Status and Outlook of Emerging Nonvolatile Memory Technologies", IEEE, 2004, pp. 567-570.
Newman R.C., "Defects in Silicon," Reports on Progress in Physics, 1982, vol. 45, pp. 1163-1210.
Notice of Allowance dated Dec. 16, 2014 for U.S. Appl. No. 12/835,704, 47 pages.
Notice of Allowance dated Dec. 19, 2014 for U.S. Appl. No. 13/529,985, 9 pgs.
Notice of Allowance dated Jul. 1, 2016 for U.S. Appl. No. 14/213,953, 96 pages.
Notice of Allowance dated Jul. 17, 2014 for U.S. Appl. No. 12/861,432, 25 pages.
Notice of Allowance dated Nov. 26, 2013 for U.S. Appl. No. 13/481,696, 15 pages.
Notice of Allowance dated Oct. 5, 2016 for U.S. Appl. No. 14/887,050, 113 pages.
Notice of Allowance dated Oct. 7, 2016 for U.S. Appl. No. 14/213,953, 43 pages.
Notice of Allowance dated Sep. 14, 2016 for U.S. Appl. No. 14/588,202, 119 pages.
Notice of Allowance for U.S. Appl. No. 13/585,759 dated Sep. 19, 2013.
Notice of Allowance for U.S. Appl. No. 13/912,136 dated Aug. 3, 2015, 15 pages.
Notice of Allowance for U.S. Appl. No. 13/952,467 dated Sep. 28, 2016, 128 pages.
Notice of Allowance for U.S. Appl. No. 131952,467 dated May 20, 2016, 19 pages.
Notice of Allowance for U.S. Appl. No. 14/027,045 dated Jun. 9, 2015, 14 pages.
Notice of Allowance for U.S. Appl. No. 14/194,499 dated Dec. 12, 2016, 125 pages.
Notice of Allowance for U.S. Appl. No. 14/213,953 dated Feb. 16, 2016, 21 pages.
Notice of Allowance for U.S. Appl. No. 14/383,079 dated Aug. 17, 2016, 71 pages.
Notice of Allowance for U.S. Appl. No. 14/383,079 dated Jan. 4, 2016, 27 pages.
Notice of Allowance for U.S. Appl. No. 14/509,967 dated Feb. 17, 2016, 18 pages.
Notice of Allowance for U.S. Appl. No. 14/509,967 dated Jun. 16, 2016, 96 pages.
Notice of Allowance for U.S. Appl. No. 14/509,967 dated Oct. 24, 2016, 42 pages.
Notice of Allowance for U.S. Appl. No. 14/588,202 dated Jan. 20, 2016, 15 pages.
Notice of Allowance for U.S. Appl. No. 14/611,022 dated Feb. 12, 2016, 13 pages.
Notice of Allowance for U.S. Appl. No. 14/611,022 dated Jun. 8, 2016, 57 pages.
Notice of Allowance for U.S. Appl. No. 14/611,022 dated Oct. 26, 2016, 41 pages.
Notice of Allowance for U.S. Appl. No. 14/611,022 dated Sep. 10, 2015, 13 pages.
Notice of Allowance for U.S. Appl. No. 14/692,677 dated Nov. 21, 2016, 97 pages.
Notice of Allowance for U.S. Appl. No. 14/887,050 dated Jun. 22, 2016, 13 pages.
Notice of Allowance for U.S. Appl. No. 14/946,367 dated Jul. 13, 2016, 23 pages.
Notice of Allowance for U.S. Appl. No. 15/046,172 dated Oct. 4, 2016, 116 pages.
Notice of Allowance mailed Apr. 17, 2012 for U.S. Appl. No. 13/158,231, filed Jun. 10, 2011.
Notice of Allowance mailed Apr. 2, 2013 for U.S. Appl. No. 13/149,757, filed May 31, 2011.
Notice of Allowance mailed Apr. 20, 2016 for U.S. Appl. No. 14/573,817.
Notice of Allowance mailed Apr. 9, 2013 for U.S. Appl. No. 13/748,490, filed Jan. 23, 2013.
Notice of Allowance mailed Aug. 26, 2015 for U.S. Appl. No. 14/034,390.
Notice of Allowance mailed Aug. 27, 2014 for U.S. Appl. No. 13/077,941, filed Mar. 31, 2011.
Notice of Allowance mailed Aug. 31, 2012 for U.S. Appl. No. 13/051,296 filed Mar. 18, 2011.
Notice of Allowance mailed Aug. 8, 2013 for U.S. Appl. No. 13/733,828 filed Jan. 3, 2013.
Notice of Allowance mailed Dec. 23, 2015 for U.S. Appl. No. 14/573,770.
Notice of Allowance mailed Feb. 10, 2015 for U.S. Appl. No. 13/525,096, filed Jun. 15, 2012.
Notice of Allowance mailed Feb. 20, 2014 for U.S. Appl. No. 13/468,201, filed May 10, 2012.
Notice of Allowance mailed Feb. 6, 2012 for U.S. Appl. No. 12/835,699, filed Jul. 13, 2010.
Notice of Allowance mailed Feb. 6, 2013 for U.S. Appl. No. 13/118,258, filed May 27, 2011.
Notice of Allowance mailed Jan. 11, 2013 for U.S. Appl. No. 12/894,087, filed Sep. 29, 2010.
Notice of Allowance mailed Jan. 11, 2016 for U.S. Appl. No. 14/613,299.
Notice of Allowance mailed Jan. 16, 2014 for U.S. Appl. No. 13/921,157, filed Jun. 18, 2013.
Notice of Allowance mailed Jan. 17, 2014 for U.S. Appl. No. 13/725,331, filed Dec. 21, 2012.
Notice of Allowance mailed Jan. 20, 2016 for U.S. Appl. No. 14/034,390.
Notice of Allowance mailed Jan. 24, 2013 for U.S. Appl. No. 13/314,513, filed Dec. 8, 2011.
Notice of Allowance mailed Jan. 8, 2013 for U.S. Appl. No. 12/814,410, filed Jun. 11, 2010.
Notice of Allowance mailed Jul. 24, 2012 for U.S. Appl. No. 12/939,824 filed Nov. 4, 2010.
Notice of Allowance mailed Jun. 19, 2012 for U.S. Appl. No. 12/861,650, filed Aug. 23, 2010.
Notice of Allowance mailed Mar. 12, 2012 for U.S. Appl. No. 12/913,719, filed Oct. 27, 2010.
Notice of Allowance mailed Mar. 15, 2013 for U.S. Appl. No. 12/894,098, filed Sep. 29, 2010.
Notice of Allowance mailed Mar. 17, 2014 for U.S. Appl. No. 13/592,224, filed Aug. 22, 2012.
Notice of Allowance mailed Mar. 20, 2014 for U.S. Appl. No. 13/461,725, filed May 1, 2012.
Notice of Allowance mailed Mar. 20, 2014 for U.S. Appl. No. 13/598,550, filed Aug. 29, 2012.
Notice of Allowance mailed May 11, 2012 for U.S. Appl. No. 12/939,824, filed Nov. 4, 2010.
Notice of Allowance mailed May 17, 2013 for U.S. Appl. No. 13/290,024.
Notice of Allowance mailed May 22, 2012 for U.S. Appl. No. 12/815,369, filed Jun. 14, 2010.
Notice of Allowance mailed May 30, 2012 for U.S. Appl. No. 12/833,898, filed Jul. 9, 2010.
Notice of Allowance mailed Nov. 13, 2013 for U.S. Appl. No. 13/461,725, filed May 1, 2012.
Notice of Allowance mailed Nov. 14, 2012 for U.S. Appl. No. 12/861,666, filed Aug. 23, 2010.
Notice of Allowance mailed Nov. 14, 2012 for U.S. Appl. No. 13/532,019, filed Jun. 25, 2012.
Notice of Allowance mailed Nov. 28, 2012 for U.S. Appl. No. 13/290,024, filed Nov. 4, 2011.
Notice of Allowance mailed Nov. 29, 2012 for U.S. Appl. No. 12/815,318, filed Jun. 14, 2010.
Notice of Allowance mailed Oct. 10, 2013 for U.S. Appl. No. 13/452,657, filed Apr. 20, 2012.
Notice of Allowance mailed Oct. 16, 2013 for U.S. Appl. No. 13/174,264, filed Jun. 30, 2011.
Notice of Allowance mailed Oct. 21, 2011 for U.S. Appl. No. 12/582,086, filed Oct. 20, 2009.
Notice of Allowance mailed Oct. 21, 2014 for U.S. Appl. No. 13/426,869, filed Mar. 22, 2012.
Notice of Allowance mailed Oct. 23, 2013 for U.S. Appl. No. 13/417,135 filed Mar. 9, 2012.
Notice of Allowance mailed Oct. 25, 2012 for U.S. Appl. No. 12/894,087, filed Sep. 29, 2010.
Notice of Allowance mailed Oct. 28, 2013 for U.S. Appl. No. 13/194,500, filed Jul. 29, 2011.
Notice of Allowance mailed Oct. 28, 2013 for U.S. Appl. No. 13/651,169, filed Oct. 12, 2012.
Notice of Allowance mailed Oct. 29, 2012 for U.S. Appl. No. 13/149,807, filed May 31, 2011.
Notice of Allowance mailed Oct. 5, 2011 for U.S. Appl. No. 12/940,920, filed Nov. 5, 2010.
Notice of Allowance mailed Oct. 8, 2013 for U.S. Appl. No. 13/769,152, filed Feb. 15, 2013.
Notice of Allowance mailed Oct. 8, 2013 for U.S. Appl. No. 13/905,074, filed May 29, 2013.
Notice of Allowance mailed Oct. 8, 2014 for U.S. Appl. No. 13/077,941, filed Mar. 31, 2011.
Notice of Allowance mailed Sep. 17, 2013 for U.S. Appl. No. 13/679,976, filed Nov. 16, 2012.
Notice of Allowance mailed Sep. 17, 2014 for U.S. Appl. No. 13/462,653, filed May 2, 2012.
Notice of Allowance mailed Sep. 17, 2014 for U.S. Appl. No. 13/960,735, filed Aug. 6, 2013.
Notice of Allowance mailed Sep. 18, 2012 for U.S. Appl. No. 12/900,232, filed Oct. 7, 2010.
Notice of Allowance mailed Sep. 18, 2014 for U.S. Appl. No. 13/586,815, filed Aug. 15, 2012.
Notice of Allowance mailed Sep. 18, 2014 for U.S. Appl. No. 13/920,021, filed Jun. 17, 2013.
Notice of Allowance mailed Sep. 25, 2014 for U.S. Appl. No. 13/447,036, filed Apr. 13, 2012.
Notice of Allowance mailed Sep. 26, 2014 for U.S. Appl. No. 13/594,665, filed Aug. 24, 2012.
Notice of Allowance mailed Sep. 30, 2013 for U.S. Appl. No. 13/481,696, filed May 25, 2012.
Notice of Allowance mailed Sep. 4, 2014 for U.S. Appl. No. 13/761,132, filed Feb. 6, 2013.
Notice of Allowance mailed Sep. 8, 2015 for U.S. Appl. No. 14/613,299.
Notice of Allowance mailed Sep. 9, 2014 for U.S. Appl. No. 13/620,012, filed Sep. 14, 2012.
Notice of Allowance mailed Sep. 9, 2014 for U.S. Appl. No. 13/870,919, filed Apr. 25, 2013.
Office Action dated Apr. 11, 2014 for U.S. Appl. No. 13/594,665, 44 pages.
Office Action dated Apr. 6, 2015 for U.S. Appl. No. 13/912,136, 23 pages.
Office Action dated Aug. 12, 2016 for U.S. Appl. No. 14/613,301, 43 pages.
Office Action dated Aug. 12, 2016 for U.S. Appl. No. 14/667,346, 27 pages.
Office Action dated Aug. 23, 2016 for U.S. Appl. No. 14/613,585, 9 pages.
Office Action dated Dec. 31, 2015 for U.S. Appl. No. 14/692,677, 27 pages.
Office Action dated Feb. 5, 2015 for U.S. Appl. No. 14/027,045, 6 pages.
Office Action for European Application No. 11005649.6 dated Dec. 1, 2014, 2 pages.
Office Action for European Application No. 11005649.6 dated Nov. 17, 2015, 5 pages.
Office Action for European Application No. EP11005207.3 dated Aug. 8, 2012, 4 pages.
Office Action for U.S. Appl. No. 13/463,714 dated Dec. 7, 2012.
Office Action for U.S. Appl. No. 13/585,759 dated May 7, 2013.
Office Action for U.S. Appl. No. 13/592,224 dated May 23, 2013.
Office Action for U.S. Appl. No. 13/952,467 dated Jan. 15, 2016, 22 pages.
Office Action for U.S. Appl. No. 13/960,735 dated Dec. 6, 2013.
Office Action for U.S. Appl. No. 14/194,499 dated May 18, 2016, 10 pages.
Office Action for U.S. Appl. No. 14/207,430 dated Jul. 25, 2016, 79 pages.
Office Action for U.S. Appl. No. 14/207,430 dated Mar. 10, 2016, 78 pages.
Office Action for U.S. Appl. No. 14/207,430 dated Oct. 15, 2015, 57 pages.
Office Action for U.S. Appl. No. 14/213,953 dated Nov. 9, 2015, 20 pages.
Office Action for U.S. Appl. No. 14/383,079 dated Aug. 4, 2015, 11 pages.
Office Action for U.S. Appl. No. 14/383,079 dated May 10, 2016, 7 pages.
Office Action for U.S. Appl. No. 14/588,136 dated Nov. 2, 2016, 132 pages.
Office Action for U.S. Appl. No. 14/588,202 dated May 10, 2016, 8 pages.
Office Action for U.S. Appl. No. 14/588,202 dated Sep. 11, 2015, 9 pages.
Office Action for U.S. Appl. No. 14/597,151 dated Oct. 20, 2016, 52 pages.
Office Action for U.S. Appl. No. 14/611,022 dated May 7, 2015, 13 pages.
Office Action for U.S. Appl. No. 14/613,301 dated Feb. 4, 2016, 42 pages.
Office Action for U.S. Appl. No. 14/613,301 dated Jul. 31, 2015, 26 pages.
Office Action for U.S. Appl. No. 14/887,050 dated Mar. 11, 2016, 12 pages.
Office Action for U.S. Appl. No. 141613,301 dated Mar. 31, 2015, 58 pages.
Office Action for U.S. Appl. No. 15/046,172 dated Apr. 20, 2016, 8 pages.
Office Action mailed Apr. 1, 2013 for U.S. Appl. No. 13/174,077, filed Jun. 30, 2011.
Office Action mailed Apr. 11, 2014 for U.S. Appl. No. 13/143,047, filed Jun. 30, 2011.
Office Action mailed Apr. 15, 2016 for U.S. Appl. No. 14/597,151.
Office Action mailed Apr. 16, 2012 for U.S. Appl. No. 12/834,610, filed Jul. 12, 2010.
Office Action mailed Apr. 17, 2012 for U.S. Appl. No. 12/814,410, filed Jun. 11, 2010.
Office Action mailed Apr. 18, 2016 for U.S. Appl. No. 14/573,770.
Office Action mailed Apr. 19, 2011 for U.S. Appl. No. 12/582,086, filed Oct. 20, 2009.
Office Action mailed Apr. 25, 2012 for U.S. Appl. No. 13/149,653, filed May 31, 2011.
Office Action mailed Apr. 25, 2014 for U.S. Appl. No. 13/761,132, filed Feb. 6, 2013.
Office Action mailed Apr. 3, 2014 for U.S. Appl. No. 13/870,919, filed Apr. 25, 2013.
Office Action mailed Apr. 5, 2012 for U.S. Appl. No. 12/833,898, filed Jul. 9, 2010.
Office Action mailed Apr. 6, 2015 for U.S. Appl. No. 14/034,390, filed Sep. 23, 2013.
Office Action mailed Apr. 6, 2015 for U.S. Appl. No. 14/034,390.
Office Action mailed Aug. 1, 2012 for U.S. Appl. No. 12/894,098, filed Sep. 29, 2010.
Office Action mailed Aug. 12, 2013 for U.S. Appl. No. 13/077,941, filed Mar. 31, 2011.
Office Action mailed Aug. 19, 2013 for U.S. Appl. No. 13/585,759, filed Aug. 14, 2012.
Office Action mailed Aug. 2, 2013 for U.S. Appl. No. 13/594,665, filed Aug. 24, 2012.
Office Action mailed Aug. 24, 2011 for U.S. Appl. No. 12/835,699, filed Jul. 13, 2010.
Office Action mailed Aug. 27, 2013 for U.S. Appl. No. 13/436,714, filed Mar. 30, 2012.
Office Action mailed Aug. 8, 2012 for EP Application No. EP11005207 filed Jun. 27, 2011.
Office Action mailed Aug. 9, 2013 for U.S. Appl. No. 13/764,710, filed Feb. 11, 2013.
Office Action mailed Dec. 27, 2013 for U.S. Appl. No. 13/525,096, filed Jun. 15, 2012.
Office Action mailed Dec. 3, 2015 for U.S. Appl. No. 14/253,796.
Office Action mailed Dec. 6, 2013 for U.S. Appl. No. 13/564,639, filed Aug. 1, 2012.
Office Action mailed Dec. 7, 2012 for U.S. Appl. No. 13/436,714, filed Mar. 30, 2012.
Office Action mailed Feb. 11, 2014 for U.S. Appl. No. 13/620,012, filed Sep. 14, 2012.
Office Action mailed Feb. 13, 2014 for U.S. Appl. No. 13/174,077, filed Jun. 30, 2011.
Office Action mailed Feb. 17, 2011 for U.S. Appl. No. 12/913,719, filed Oct. 27, 2010.
Office Action mailed Feb. 28, 2014 for U.S. Appl. No. 12/625,817, filed Nov. 25, 2009.
Office Action mailed Feb. 6, 2014 for U.S. Appl. No. 13/434,567, filed Mar. 29, 2012.
Office Action mailed Jan. 10, 2014 for U.S. Appl. No. 13/920,021, filed Jun. 17, 2013.
Office Action mailed Jan. 16, 2014 for U.S. Appl. No. 13/739,283, filed Jan. 11, 2013.
Office Action mailed Jan. 25, 2012 for U.S. Appl. No. 12/861,650, filed Aug. 23, 2010.
Office Action mailed Jan. 29, 2014 for U.S. Appl. No. 13/586,815, filed Aug. 15, 2012.
Office Action mailed Jan. 8, 2014 for U.S. Appl. No. 12/861,432, filed Aug. 23, 2010.
Office Action mailed Jul. 11, 2013 for U.S. Appl. No. 13/764,698, filed Feb. 11, 2013.
Office Action mailed Jul. 22, 2010 for U.S. Appl. No. 11/875,541, filed Oct. 19, 2007.
Office Action mailed Jul. 22, 2011 for U.S. Appl. No. 12/913,719 filed Oct. 27, 2010.
Office Action mailed Jul. 29, 2013 for U.S. Appl. No. 13/466,008, filed May 7, 2012.
Office Action mailed Jul. 30, 2012 for U.S. Appl. No. 12/900,232, filed Oct. 7, 2010.
Office Action mailed Jul. 9, 2013 for U.S. Appl. No. 13/447,036, filed Apr. 13, 2012.
Office Action mailed Jul. 9, 2014 for U.S. Appl. No. 14/166,691, filed Jan. 28, 2014.
Office Action mailed Jul. 9, 2015 for U.S. Appl. No. 14/573,817.
Office Action mailed Jun. 17, 2014 for U.S. Appl. No. 14/072,657, filed Nov. 5, 2013.
Office Action mailed Jun. 19, 2012 for U.S. Appl. No. 13/149,757, filed May 31, 2011.
Office Action mailed Jun. 30, 2014 for U.S. Appl. No. 13/531,449, filed Jun. 22, 2012.
Office Action mailed Jun. 8, 2012 for U.S. Appl. No. 11/875,541, filed Oct. 19, 2007.
Office Action mailed Mar. 1, 2012 for U.S. Appl. No. 12/835,704, filed Jul. 13, 2010.
Office Action mailed Mar. 12, 2014 for U.S. Appl. No. 13/167,920, filed Jun. 24, 2011.
Office Action mailed Mar. 14, 2012 for U.S. Appl. No. 12/815,369, filed Jun. 14, 2010.
Office Action mailed Mar. 14, 2014 for U.S. Appl. No. 12/835,704, filed Jul. 13, 2010.
Office Action mailed Mar. 17, 2015 for U.S. Appl. No. 14/573,770.
Office Action mailed Mar. 19, 2013 for U.S. Appl. No. 13/465,188, filed May 7, 2012.
Office Action mailed Mar. 19, 2013 for U.S. Appl. No. 13/564,639, filed Aug. 1, 2012.
Office Action mailed Mar. 21, 2014 for U.S. Appl. No. 13/447,036, filed Apr. 13, 2012.
Office Action mailed Mar. 27, 2012 for U.S. Appl. No. 13/314,513, filed Dec. 8, 2011.
Office Action mailed Mar. 29, 2013 for U.S. Appl. No. 12/861,432, filed Aug. 23, 2010.
Office Action mailed Mar. 30, 2011 for U.S. Appl. No. 11/875,541, filed Oct. 19, 2007.
Office Action mailed Mar. 6, 2013 for U.S. Appl. No. 13/174,264, filed Jun. 30, 2011.
Office Action mailed Mar. 6, 2013 for U.S. Appl. No. 13/679,976, filed Nov. 16, 2012.
Office Action mailed Mar. 7, 2013 for U.S. Appl. No. 13/651,169, filed Oct. 12, 2012.
Office Action mailed May 16, 2012 for U.S. Appl. No. 121815,318, filed Jun. 14, 2010.
Office Action mailed May 20, 2013 for U.S. Appl. No. 13/725,331, filed Dec. 21, 2012.
Office Action mailed May 20, 2016 for U.S. Appl. No. 14/613,299.
Office Action mailed May 21, 2014 for U.S. Appl. No. 13/764,698, filed Feb. 11, 2013.
Office Action mailed Nov. 20, 2012 for U.S. Appl. No. 13/149,653, filed May 31, 2011.
Office Action mailed Nov. 26, 2012 for U.S. Appl. No. 13/156,232.
Office Action mailed Oct. 16, 2012 for U.S. Appl. No. 12/861,650, filed Aug. 23, 2010.
Office Action mailed Oct. 25, 2012 for U.S. Appl. No. 13/461,725, filed May 1, 2012.
Office Action mailed Oct. 3, 2013 for U.S. Appl. No. 13/921,157, filed Jun. 18, 2013.
Office Action mailed Oct. 5, 2011 for U.S. Appl. No. 11/875,541, filed Oct. 19, 2007.
Office Action mailed Oct. 9, 2012 for U.S. Appl. No. 13/417,135, filed Mar. 9, 2012.
Office Action mailed Sep. 11, 2014 for U.S. Appl. No. 13/739,283, filed Jan. 11, 2013.
Office Action mailed Sep. 12, 2014 for U.S. Appl. No. 13/426,869, filed Mar. 22, 2012.
Office Action mailed Sep. 12, 2014 for U.S. Appl. No. 13/756,498.
Office Action mailed Sep. 2, 2014 for U.S. Appl. No. 13/705,082, 41 pages.
Office Action mailed Sep. 20, 2013 for U.S. Appl. No. 13/481,600, filed May 25, 2012.
Office Action mailed Sep. 21, 2011 for U.S. Appl. No. 12/835,704, filed Jul. 13, 2010.
Office Action mailed Sep. 22, 2013 for U.S. Appl. No. 13/189,401, filed Jul. 22, 2011.
Office Action mailed Sep. 25, 2013 for U.S. Appl. No. 13/194,479, filed Jul. 29, 2011.
Office Action mailed Sep. 30, 2013 for U.S. Appl. No. 13/189,401, filed Jul. 22, 2011.
Office Action mailed Sep. 30, 2013 for U.S. Appl. No. 13/462,653, filed May 2, 2012.
Office Action mailed Sep. 6, 2011 for U.S. Appl. No. 12/582,086, filed Oct. 20, 2009.
Owen A.E., et al., "Electronic Switching in Amorphous Silicon Devices: Properties of the Conducting Filament", Proceedings of 5th International Conference on Solid-State and Integrated Circuit Technology, IEEE, 1998, pp. 830-833.
Owen A.E., et al., "Memory Switching in Amorphous Silicon Devices," Journal of Non-Crystalline Solids, 1983, vol. 50-60 (Pt.2), pp. 1273-1280.
Owen A.E., et al., "New Amorphous-Silicon Electrically Programmable Nonvolatile Switching Device," Solid-State and Electron Devices, IEEE Proceedings, 1982, vol. 129 (Pt. 1), pp. 51-54.
Owen A.E., et al., "Switching in Amorphous Devices," International Journal of Electronics, 1992, vol. 73 (5), pp. 897-906.
Rose M.J., et al., "Amorphous Silicon Analogue Memory Devices," Journal of Non-Crystalline Solids, 1989, vol. 115, pp. 168-170.
Russo U., et al., "Self-Accelerated Thermal Dissolution Model for Reset Programming in Unipolar Resistive-Switching Memory (RRAM) Devices," IEEE Transactions on Electron Devices, 2009, vol. 56 (2), pp. 193-200.
Scott J.C., "Is There an Immortal Memory?," American Association for the Advancement of Science, 2004, vol. 304 (5667), pp. 62-63.
Shin W., et al., "Effect of Native Oxide on Polycrystalline Silicon CMP," Journal of the Korean Physical Society, 2009, vol. 54 (3), pp. 1077-1081.
Stikeman A., Polymer Memory-The Plastic Path to Better Data Storage, Technology Review, Sep. 2002, pp. 31. Retrieved from the Internet.
Suehle J.S., et al., "Temperature Dependence of Soft Breakdown and Wear-out in Sub-3 Nm Si02 Films", 38th Annual International Reliability Physics Symposium, San Jose, California, 2000, pp. 33-39.
Sune J., et al., "Nondestructive Multiple Breakdown Events in Very Thin Si02 Films," Applied Physics Letters, 1989, vol. 55, pp. 128-130.
Terabe K., et al., "Quantized Conductance Atomic Switch," Nature, 2005, vol. 433, pp. 47-50.
Waser R., et al., "Nanoionics-based Resistive Switching Memories," Nature Materials, 2007, vol. 6, pp. 833-835.
Written Opinion for Application No. PCT/US2009/060023, mailed on May 18, 2010, 3 pages.
Written Opinion for Application No. PCT/US2009/061249, mailed on May 19, 2010, 3 pages.
Written Opinion for Application No. PCT/US2011/040090, mailed on Feb. 17, 2012, 6 pages.
Written Opinion for Application No. PCT/US2011/045124, mailed on May 29, 2012, 5 pages.
Written Opinion for Application No. PCT/US2011/046036, mailed on Feb. 23, 2012, 4 pages.
Yin S., "Solution Processed Silver Sulfide Thin Films for Filament Memory Applications", Technical Report No. UCB/EECS-2010-166, Dec. 17, 2010, Electrical Engineering and Computer Sciences, University of California at Berkeley. Retrieved from the Internet.
Yuan H.C., et al., "Silicon Solar Cells with Front Hetero-Contact and Aluminum Alloy Back Junction", NREL Conference Paper CP-520-42566, 33rd IEEE Photovoltaic Specialists Conference, May 11-16, 2008, National Renewable Energy Laboratory, San Diego, California.
Zankovych S., et al., "Nanoimprint Lithography: Challenges and Prospects," Nanotechnology, 2001, vol. 12, pp. 91-95.

Similar Documents

Publication Publication Date Title
Waser et al. Nanoionics-based resistive switching memories
Chen et al. Non-volatile resistive switching for advanced memory applications
Akinaga et al. Resistive random access memory (ReRAM) based on metal oxides
US8320160B2 (en) NAND architecture having a resistive memory cell connected to a control gate of a field-effect transistor
US7738279B2 (en) Integrated circuit and method of operating an integrated circuit
US8374018B2 (en) Resistive memory using SiGe material
US7924138B2 (en) Semiconductor device and manufacturing method of the same
US20060034116A1 (en) Cross point array cell with series connected semiconductor diode and phase change storage media
Huang et al. Bipolar Nonlinear $\hbox {Ni/TiO} _ {2}\hbox {/}\hbox {Ni} $ Selector for 1S1R Crossbar Array Applications
US8315079B2 (en) Circuit for concurrent read operation and method therefor
US20070165434A1 (en) Resistive RAM having at least one varistor and methods of operating the same
US9589636B1 (en) Method, system and device for complementary non-volatile memory device operation
US8274812B2 (en) Write and erase scheme for resistive memory device
US7426128B2 (en) Switchable resistive memory with opposite polarity write pulses
US20060109704A1 (en) Nonvolatile memory device using resistor having multiple resistance states and method of operating the same
US20080278989A1 (en) Resistive memory device and method of manufacturing the same
Prakash et al. TaO x-based resistive switching memories: prospective and challenges
Sawa Resistive switching in transition metal oxides
US20060152961A1 (en) NOR-type hybrid multi-bit non-volatile memory device and method of operating the same
US20120127779A1 (en) Re-writable Resistance-Switching Memory With Balanced Series Stack
US20120074374A1 (en) Conductive path in switching material in a resistive random access memory device and control
US20100085798A1 (en) Silicon-based nanoscale resistive device with adjustable resistance
US20080170428A1 (en) Nonvolatile semiconductor memory device and method of writing into the same
US20140160830A1 (en) Programmable Resistive Device and Memory Using Diode as Selector
US7303971B2 (en) MSM binary switch memory device

Legal Events

Date Code Title Description
AS Assignment

Owner name: CROSSBAR, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LU, WEI;JO, SUNG HYUN;NAZARIAN, HAGOP;SIGNING DATES FROM 20140318 TO 20140319;REEL/FRAME:036554/0770

MAFP

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551)

Year of fee payment: 4