CN1698198A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- CN1698198A CN1698198A CNA2004800000580A CN200480000058A CN1698198A CN 1698198 A CN1698198 A CN 1698198A CN A2004800000580 A CNA2004800000580 A CN A2004800000580A CN 200480000058 A CN200480000058 A CN 200480000058A CN 1698198 A CN1698198 A CN 1698198A
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
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- H01L2224/9222—Sequential connecting processes
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Engineering & Computer Science (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A semiconductor device includes at least one semiconductor structure which has a plurality of external connection electrodes formed on a semiconductor substrate. An insulating sheet member is arranged on the side of the semiconductor structure. Upper interconnections have connection pad portions that are arranged on the insulating sheet member in correspondence with the upper interconnections and connected to the external connection electrodes of the semiconductor structure.
Description
Technical field
The present invention relates to a kind of semiconductor device, particularly a kind of semiconductor device and manufacture method thereof that belongs to the small semiconductor encapsulation that is called as CSP (chip size packages).
Background technology
In recent years, along with the portable electron device that with the cell phone is representative reduces their size, developed the semiconductor device that is called as CSP (chip size packages).In CSP, passivating film (intermediate insulating film) is formed on the upper surface with the bare semiconductor device that is used for the outside a plurality of connection pads that connect.Opening portion is formed in the passivating film and corresponding connection pads.The intercommunicated opening portion of crossing is connected to the distolateral of connection pads.Being used for the outside columnar electrode that connects, to be formed on another of interconnection distolateral.Fill with encapsulant in the space that is used between the outside columnar electrode that connects.According to this CSP, when solder ball is formed on the columnar electrode that is used for outside connection, can this device be connected on the circuit board with splicing ear by prone method profit.Erection space can be almost identical with the bare semiconductor size of devices.Therefore compare the size that CSP has reduced electronic installation greatly with the method for attachment that faces up of the routine of using line to be connected.U.S. Pat 6467674 discloses a kind of method, wherein in order to increase output, forms passivating film, interconnection, external connecting electrode and encapsulant on the Semiconductor substrate under the wafer state.Do not form solder ball there being sealed material to cover on the upper surface of exposed exterior connection electrode afterwards.Then, along the line of cut cut crystal, thereby form individual semiconductor device.
There is following point in conventional semiconductor device: along with integrated level uprises, the quantity of external connecting electrode increases.As mentioned above, in CSP, external connecting electrode is arranged on the upper surface of bare semiconductor device.Therefore, external connecting electrode is arranged in matrix usually.In having the semiconductor device of a lot of external connecting electrodes, the size of external connecting electrode and spacing become especially little.Because this defective, the CSP technology can not be applicable to the device that has with respect to a large amount of external connecting electrodes of bare semiconductor device size.If it is external connecting electrode has minimum size and spacing, then very difficult with aiming at of circuit board.Also have a lot of fatal problems, as low bonding strength, connect between the electrode short circuit and cause the damage of external connecting electrode by the stress of the difference generation of the linear expansion coefficient between circuit board and the Semiconductor substrate that forms by silicon substrate usually.
Summary of the invention
The purpose of this invention is to provide a kind of new semiconductor device and manufacture method thereof,, also can guarantee the required size and the spacing of external connecting electrode even number of electrodes increases.
According to a scheme of the present invention, a kind of semiconductor device is provided, comprising: at least one semiconductor component has Semiconductor substrate and a plurality of external connecting electrodes that are formed on the Semiconductor substrate; Be arranged on the insulation plate on semiconductor component one side; With a plurality of upper interconnect with connection pads part, wherein connection pads partly is arranged on the insulation plate and corresponding upper interconnect, and is electrically connected to the external connecting electrode of semiconductor component.
According to another aspect of the present invention, a kind of method, semi-conductor device manufacturing method is provided, comprise: a plurality of semiconductor components are set on substrate, each semiconductor component has a Semiconductor substrate and a plurality of connection pads, simultaneously semiconductor component is separated from each other, with on the position of corresponding semiconductor component, be provided with at least one the insulation plate, upside heating and pressurization insulation plate from the insulation plate, thereby fusing and curing insulation plate are between semiconductor component, form one deck upper interconnect at least, this upper interconnect has connection pads part and is connected on corresponding of a plurality of connection pads of one of a plurality of semiconductor components, so that the connection pads part is set to corresponding upper interconnect on the insulation plate, and between semiconductor component cutting insulation plate, thereby obtain a plurality of semiconductor device, wherein the connection pads of upper interconnect partly is arranged on the insulation plate.
Description of drawings
Fig. 1 is the profile according to the semiconductor device of first embodiment of the invention;
Fig. 2 is the profile of the initial preparation structure in the example of manufacture method of semiconductor device shown in Figure 1;
Fig. 3 is the profile of the manufacturing step after the presentation graphs 2;
Fig. 4 is the profile of the manufacturing step after the presentation graphs 3;
Fig. 5 is the profile of the manufacturing step after the presentation graphs 4;
Fig. 6 is the profile of the manufacturing step after the presentation graphs 5;
Fig. 7 is the profile of the manufacturing step after the presentation graphs 6;
Fig. 8 is the profile of the manufacturing step after the presentation graphs 7;
Fig. 9 is the profile of the manufacturing step after the presentation graphs 8;
Figure 10 is the profile of the manufacturing step after the presentation graphs 9;
Figure 11 is the profile of the manufacturing step after expression Figure 10;
Figure 12 is the profile of the manufacturing step after expression Figure 11;
Figure 13 is the profile of the manufacturing step after expression Figure 12;
Figure 14 is the profile of the manufacturing step after expression Figure 13;
Figure 15 is the profile of the manufacturing step after expression Figure 14;
Figure 16 is the profile of the manufacturing step after expression Figure 15;
Figure 17 is the profile according to the semiconductor device of second embodiment of the invention;
Figure 18 is the profile according to the semiconductor device of third embodiment of the invention;
Figure 19 is the profile according to the semiconductor device of fourth embodiment of the invention;
Figure 20 is the profile according to the semiconductor device of fifth embodiment of the invention;
Figure 21 is the profile according to the semiconductor device of sixth embodiment of the invention;
Figure 22 is the profile according to the semiconductor device of seventh embodiment of the invention;
Figure 23 is the profile according to the semiconductor device of eighth embodiment of the invention;
Figure 24 is the profile of the predetermined manufacturing step in the example of manufacture method of expression semiconductor device shown in Figure 23;
Figure 25 is the profile of the manufacturing step after expression Figure 24;
Figure 26 is the profile according to the semiconductor device of ninth embodiment of the invention;
Figure 27 is the profile of the predetermined manufacturing step in the example of manufacture method of expression semiconductor device shown in Figure 26;
Figure 28 is the profile of the manufacturing step after expression Figure 27;
Figure 29 is the profile of the manufacturing step after expression Figure 28;
Figure 30 is the profile according to the semiconductor device of tenth embodiment of the invention;
Figure 31 is the profile according to the semiconductor device of eleventh embodiment of the invention;
Figure 32 is the profile according to the semiconductor device of twelveth embodiment of the invention;
Figure 33 is the profile according to the semiconductor device of thriteenth embodiment of the invention;
Figure 34 is the profile according to the semiconductor device of fourteenth embodiment of the invention;
Figure 35 is the profile according to the semiconductor device of fifteenth embodiment of the invention;
Figure 36 is the profile that is used to explain the manufacturing step of the semiconductor device shown in Figure 35;
Figure 37 is the profile of the manufacturing step after expression Figure 36;
Figure 38 is the profile of the manufacturing step after expression Figure 37;
Figure 39 is the profile of the manufacturing step after expression Figure 38;
Figure 40 is the profile of the manufacturing step after expression Figure 39;
Figure 41 is the profile of the manufacturing step after expression Figure 40;
Figure 42 is the profile of the manufacturing step after expression Figure 41;
Figure 43 is the profile of the manufacturing step after expression Figure 42;
Figure 44 is the profile according to the semiconductor device of sixteenth embodiment of the invention;
Figure 45 is the profile according to the semiconductor device of seventeenth embodiment of the invention;
Figure 46 is the profile according to the semiconductor device of eighteenth embodiment of the invention;
Figure 47 is the profile that is used to explain the manufacturing step of semiconductor device shown in Figure 46;
Figure 48 represents the profile of the manufacturing step after Figure 47;
Figure 49 is the profile of the manufacturing step after expression Figure 48; With
Figure 50 is the profile of the manufacturing step after expression Figure 49.
Embodiment
(first embodiment)
Fig. 1 is the profile according to the semiconductor device of first embodiment of the invention.Semiconductor device have rectangular planar shape and the metal level 1 made by copper etc. and the lower surface that is formed on metal level 1 on and the insulating barrier 2 made by solder resist.Metal level prevent to electrify or rayed on the integrated circuit of silicon substrate 5 (will illustrate below).Insulating barrier 2 protection metal levels 1.
Have rectangular planar shape and be slightly less than the upper surface core that adhesive phase 4 that the lower surface of the semiconductor component 3 of metal level 1 makes via the tube core welding material is connected to metal level 1.Semiconductor component 3 has interconnection, columnar electrode and diaphragm seal (will illustrate below) and is commonly referred to as CSP.Especially, because employing forms interconnection, columnar electrode and diaphragm seal, cuts to obtain the method for independent semiconductor component 3 then on silicon wafer, as hereinafter described, semiconductor component 3 liquid are called wafer level chip size package (W-CSP) especially.The structure of semiconductor component 3 will be introduced below.
The diaphragm of being made by epoxy resin or polyimide resin (dielectric film) 9 is formed on the upper surface of the dielectric film 7 on the silicon substrate 5.Opening portion 10 is formed in the diaphragm 9 on the position of the opening portion 8 of corresponding dielectric film 7.The interconnection 11 that is made of copper extends to the predetermined portions of the upper surface of diaphragm 9 from the upper surface by opening portion 8 and 10 each connection pads 6 that exposes.
The columnar electrode that is made of copper (external connecting electrode) 12 is formed on the connection pads upper surface partly of each interconnection 11.The diaphragm seal of being made by epoxy resin or polyimide resin (dielectric film) 13 is formed on the upper surface of diaphragm 9 and interconnection 11.The upper surface flush of the upper surface of diaphragm seal 13 and columnar electrode 12.As mentioned above, the semiconductor component 3 of so-called W-CSP comprises silicon substrate 5, connection pads 6 and dielectric film 7, and also comprises diaphragm 9, interconnection 11, columnar electrode 12 and diaphragm seal 13.
First insulating material (insulation plate) 14 with rectangular frame shape is arranged on the upper surface of semiconductor component 3 metal level 1 on every side.The upper surface of first insulating material 14 almost with the upper surface flush of semiconductor component 3.Second insulating material 15 with flat upper surfaces is arranged on the upper surface of the semiconductor component 3 and first insulating material 14.
First insulating material 14 is commonly called pre impregnated material, prepares by for example thermosetting resin such as epoxy resin being injected in the glass fibre.Second insulating material 15 is commonly called the aggregate material that is used for gathered substrate.Second insulating material 15 is by the thermosetting resin that contains reinforcing material such as fiber or filler such as epoxy resin or BT (Bismaleimide Triazine) resin formation.In this case, fiber is preferably made by glass fibre or the poly-sour ammonium fiber of aromatics.Filler is silica filler or ceramic packing preferably.
On the position of the core of the upper surface of corresponding columnar electrode 12, in second insulating material 15, form opening portion 16.The upper interconnect 17 that is made of copper is arranged to matrix.Each upper interconnect 17 extends to the predetermined portions of the upper surface of second insulating material 15 from the upper surface of a corresponding columnar electrode 12, and a wherein corresponding columnar electrode 12 exposes through the upper surface of opening portion 16 from insulating material 15.
The top dielectric film of being made by solder resist 18 is formed on the upper surface of the upper interconnect 17 and second insulating material 15.On the position of the connection pads of corresponding upper interconnect 17, in top dielectric film 18, form opening portion 19.The projected electrode 20 that is formed by solder ball is formed on opening portion 19 neutralizations on it, and electricity (with mechanically) is connected to the connection pads part of upper interconnect 17.Projected electrode 20 with cells arranged in matrix on top dielectric film 18.
The size of metal level 1 is a bit larger tham the size of semiconductor component 3.Reason is as follows.Along with the quantity increase of the connection pads on the silicon substrate 5, the setting area of projected electrode 20 is a bit larger tham the size of semiconductor component 3.Thereby the size of the connection pads of upper interconnect 17 part (part in the opening portion 19 of top dielectric film 8) and spacing form greater than the size and the spacing of columnar electrode 12.
Therefore, the connection pads part of being arranged to the upper interconnect 17 of matrix not only is installed on the zone of corresponding semiconductor component 3, and is installed on the zone of first insulating material 14 beyond the exterior side surfaces that correspondence is arranged on semiconductor component 3.In other words, be arranged in the projected electrode 20 of matrix, be at least projected electrode 20 on the most external position be arranged on semiconductor component 3 around.
As mentioned above; feature as this semiconductor device; first and second insulating elements 14 and 15 be arranged on semiconductor component 3 around and disposed thereon, wherein not only connection pads 6 and dielectric film 7, and diaphragm 9, interconnection 11, columnar electrode 12 and diaphragm seal 13 are formed on the silicon substrate 5.Be formed on the upper surface of second insulating material 15 by being formed on the upper interconnect 17 that opening portion 16 in second insulating material 15 is connected to columnar electrode 12.
In said structure, the upper surface of second insulating material 15 is smooth.For this reason, the height and position of the upper surface of upper interconnect 17 and the projected electrode 20 that forms in step afterwards can be uniformly, and can improve the reliability of connection.
To introduce the example of the method for making semiconductor device below.At first, the example of the method for making semiconductor component 3 will be introduced.In this case; as shown in Figure 2; the preparation component members; the wherein connection pads of making by aluminium based metal 6, the dielectric film of making by silica 7 and be formed on the silicon substrate (Semiconductor substrate) 5 that is in wafer state by the diaphragm 9 that epoxy resin or polyimide resin are made, and the core of connection pads 6 comes out by the opening portion 8 and 10 that is formed in dielectric film 7 and the diaphragm 9.In said structure, the integrated circuit with predetermined function is formed in the zone of the silicon substrate that is in wafer state 5 that will form each semiconductor component.Each connection pads 6 is electrically connected to the integrated circuit that is formed in the corresponding region.
Then, as shown in Figure 3, lower metal layer 11a is formed on the entire upper surface of diaphragm 9, comprises the upper surface by opening portion 8 and 10 connection pads 6 that expose.In this case, lower metal layer 11a can only have the copper layer that forms by electroless or only have the copper layer that forms by sputter.Perhaps, can on the thin titanium layer that forms by sputter, form the copper layer by sputtering method.This also is applicable to the lower metal layer (will be explained below) of upper interconnect 17.
Then, platedresist film 21 is formed on the upper surface of lower metal layer 11a and composition.In this case, patterned resist film 21 has opening portion 22 on the position in the formation zone of corresponding each interconnection 11.Use lower metal layer 11a to carry out the copper plating as the electroplating current path, thereby in each opening portion 22 of platedresist film 21, forming metal level 11b on the upper surface of lower metal layer 11a.Then, remove platedresist film 21.
As shown in Figure 4, platedresist film 23 is formed on the upper surface of the lower metal layer 11a that comprises metal level 11b and composition.In this case, patterned resist film 23 has opening portion 24 on the position in the formation district of corresponding each columnar electrode 12.Use lower metal layer 11a to make the electroplating current path and carry out the copper plating, thus in each opening portion 24 of platedresist film 23, on the upper surface of the connection pads of last metal level 11b formation columnar electrode 12.
Then, remove platedresist film 23.Then, use columnar electrode 12 and last metal level 11b to make mask, the unwanted part of removing lower metal layer 11a by etching, thereby lower metal layer 11a only stay metal level 11b below, as shown in Figure 5.The lower metal layer 11a that each stays and be formed on last metal level 11b on the entire upper surface of lower metal layer 11a and constitute and interconnect 11.
As shown in Figure 6, by silk screen printing, spin coating or mould apply will be formed on diaphragm 9, columnar electrode 12 by the diaphragm seal 13 that epoxy resin or polyimide resin constitute and 11 the entire upper surface of interconnecting on.The thickness of diaphragm seal 13 is greater than the height of columnar electrode 12.Therefore, under this state, the sealed film 13 of the upper surface of columnar electrode 12 covers.Upper surface one side of diaphragm seal 13 and columnar electrode 12 is suitably polished, and exposes the upper surface of columnar electrode 12 thus, as shown in Figure 7.The upper surface of diaphragm seal 13 of exposed upper surface that comprises columnar electrode 12 is also flattened.
The reason that upper surface one side of columnar electrode 12 is suitably polished is: changed and must be made it even by removing this variation by the height of electroplating the columnar electrode 12 form.In order to polish the columnar electrode 12 made by soft copper simultaneously and, to use the grinder of grinding stone with suitable roughness by the diaphragm seal 13 that epoxy resin etc. is made.
As shown in Figure 8, adhesive phase 4 is connected on the whole lower surface of silicon substrate 5.Adhesive phase 4 by tube core welding material such as epoxy resin or the polyimides data are made and by the heating and the pressurization bond on the silicon substrate 5 so that state to be set temporarily.Then, the adhesive phase 4 that bonds to silicon substrate 5 is connected to the cutting belt (not shown).After the cutting step shown in Figure 9, peel off each member from cutting belt.Thereby, obtaining a plurality of semiconductor components 3, each semiconductor component has the adhesive phase 4 on the lower surface of silicon substrate 5, as shown in Figure 1.
In thus obtained semiconductor component 3, adhesive phase 4 is present on the lower surface of silicon substrate 5.Therefore, after cutting step, do not need to be used on the lower surface of the silicon substrate 5 of each semiconductor component 3, to form the very operation of trouble of adhesive phase.The operation that after cutting step, is used for peeling off each semiconductor component from cutting belt than be used for after cutting step lower surface at the silicon substrate 5 of each semiconductor component 3 form adhesive phase simplified control many.
To illustrate below, and wherein use the semiconductor component 3 that obtains by said method to make semiconductor device shown in Figure 1.At first, as shown in figure 10, preparation substrate 31.To such an extent as to the so big a plurality of Copper Foils that constitute the upper surface side of metal level 1 as shown in Figure 1 of substrate 31 are sampled, this will be described later.Substrate 31 has rectangular planar shape, particularly is similar to square plan-form shapes, but its shape is not limited thereto.Copper Foil is connected on the upper surface of substrate 31 through adhesive phase 32.
Then, the adhesive phase 4 of lower surface that bonds to the silicon substrate 5 of semiconductor component 3 bonds on a plurality of predetermined portions of upper surface of Copper Foil 1a.During this technique for sticking, adhesive phase 4 is provided with by heating and pressurization at last.Respectively having two first insulation plate 14a of the opening portion that is arranged in matrix and 14b aims on the upper surface of the Copper Foil 1a between semiconductor component 3 and the outside at the semiconductor component 3 of outermost position and piles up.The second insulation plate 15a is placed on the upper surface of the first insulation plate 14b.Can after piling up and two first insulation plate 14a and 14b are set, semiconductor component 3 be set.
The first insulation plate 14a and the 14b that respectively have matrix shape can obtain by following manner.Thermosetting resin such as epoxy resin are injected glass fibre.Thermosetting resin is a semi-solid preparation, so that preparation plate shape pre impregnated material.By die-cut or be etched in the pre impregnated material and form a plurality of rectangular aperture parts 33.In this case, in order to obtain flatness, each first insulation plate 14a and 14b must be plate shape parts.Yet this material needn't be always pre impregnated material.Thermosetting resin or wherein disperseed also can use as the thermosetting resin of the reinforcing material of glass fibre or silica filler.
The second insulation plate 15a is preferably made by aggregate material, but is not limited thereto.As aggregate material, can use the thermosetting resin that has wherein mixed silica filler and semi-solid preparation, as epoxy resin or BT resin.Yet as the second insulation plate 15a, above-mentioned pre impregnated material or the material that does not conform to filler or only contain thermosetting resin all can use.
The size that the size of the opening portion 33 of the first insulation plate 14a and 14b is a bit larger tham semiconductor component 3.For this reason, between the first insulation plate 14a, 14b and semiconductor component 3, form gap 34.The length in gap 34 for example is approximately 0.1-0.5mm.The gross thickness of the first insulation plate 14a and 14b is greater than the thickness of semiconductor component 3.The first insulation plate 14a and 14b are enough thick so that fill gap 34 when heating and suppress the first insulation plate, as described later.
In this case, first identical insulation plate 14a and the 14b of used thickness.Yet the first insulation board substrate 14a can have different thickness with 14b.The first insulation plate can comprise two-layer, as mentioned above.Yet, also can comprise one deck or three layers or more multi-layered.The thickness of the second insulation plate 15a is corresponding or be a bit larger tham the thickness of second insulating material 15 on the semiconductor component 3 that will be formed among Fig. 1.
Then, use a pair of heat/pressure plate 35 shown in Figure 11 and 36 heating and the pressurize first insulation plate 14a and the 14b and the second insulation plate 15a.Thereby, thereby the thermosetting resin of the fusing among the first insulation plate 14a and the 14b is extruded the gap 34 of filling between the first insulation plate 14a, 14b and the semiconductor component 3, as shown in figure 10.By follow-up cooling processing, the thermosetting resin semi-solid preparation bonds on semiconductor component 3 and the Copper Foil 1a between them simultaneously.In this way, as shown in figure 11, first insulating material 14 of making and bond to substrate 31 by the thermosetting resin that contains reinforcing material is formed on semiconductor component 3 and on the upper surface of the Copper Foil 1a between the outside of the semiconductor component on the outermost locations 3.In addition, second insulating material of being made by the thermosetting resin that contains reinforcing material 15 is formed on the upper surface of the semiconductor component 3 and first insulating material 14.
In this case, as shown in Figure 7, under wafer state, the columnar electrode 12 in each semiconductor component 3 has even height.In addition, it is flattened to comprise the upper surface of diaphragm seal 13 of upper surface of columnar electrode 12.For this reason, under state shown in Figure 11, a plurality of semiconductor components 3 have same thickness.
Under state shown in Figure 11, heat and pressurize, simultaneously as the pressure limit surface, limit the virtual plane of the upper surface that is higher than semiconductor component 3 by the diameter of the reinforcing material (for example silica filler) of one deck.Second insulating material, 15 acquisitions on the semiconductor component 3 equal the thickness of the diameter of reinforcing material (for example silica filler).When beginning (opening) smooth forcing press as having the forcing press of a pair of heat/ pressure plate 35 and 36, unnecessary thermosetting resin is extruded a pair of heating/ heating plate 35 and 36 among insulation plate 14a, 14b, the 15a.
The upper surface of second insulating material 15 is flat surfaces because it be heated/lower surface of increased pressure board 36 pressurizes at upside.Therefore, the polishing step that does not need the upper surface of complanation second insulating material 15.Even Copper Foil 1a has big relatively size, for example about 500 * 500mm also can once carry out complanation to second insulating material 15 at an easy rate with respect to a plurality of semiconductor components 3 that are arranged on the Copper Foil 1a.
First and second insulating material 14 and 15 are made of the thermosetting resin that contains reinforcing material such as fiber or filler., compare for this reason, can reduce because the stress that the contraction in the curing of thermosetting resin produces with the structure that only constitutes by thermosetting resin.This has also prevented Copper Foil 1a bending.
In manufacturing step shown in Figure 11, heating and pressurization can be carried out by the device that separates.That is, for example, pressurization can only be carried out from upper surface one side, utilizes the lower surface heating of heater to semiconductor component 3 simultaneously.Perhaps, heating and pressurization can be carried out in the step of separating.
When manufacturing step shown in Figure 11 finished, first and second insulating material 14 and 15, semiconductor component 3 and Copper Foil 1a were integrated in together.They only keep required intensity.Then, peel off or remove substrate 31 and adhesive phase 32 by polishing or etching.Carry out this processing, so that reduce the load in the cutting (will be explained below) and reduce thickness as the semiconductor device of product.In manufacturing step shown in Figure 10, make when bonding that insulation plate 14a, 14b and 15a are temporary transient to be solidified and when temporarily bonding on the upper surface of Copper Foil 1a by interim contact, can be this step after by polishing or substrate 31 and adhesive phase 32 be peeled off or be removed to etching.
Then, as shown in figure 12,, on the position of the core of the upper surface of corresponding columnar electrode 12, in second insulating material 15, form opening portion 16 by laser engine processing with laser beam irradiation second insulating material 15.Then, as required, handle the epoxy oil stain of removing generation in the opening portion 16 by deoiling.
As shown in figure 13, upper interconnect cambium layer 17a is formed on the entire upper surface of second insulating material 15, comprises the upper surface of the columnar electrode 12 that exposes by opening portion 16.Simultaneously, metal film 1b is formed on the lower surface of Copper Foil 1a.In this case, upper interconnect cambium layer 17a and metal film 1b respectively comprise for example by copper layer lower metal layer that forms and the lip-deep metal level of going up that is formed on lower metal layer, wherein said copper layer forms by electroless, the described metal level of going up is by using lower metal layer as the electroplating current path, electroplates and forms by carrying out copper.
When upper interconnect cambium layer 17a being carried out composition, on the precalculated position of the upper surface of second insulating material 15, form upper interconnect 17, as shown in figure 14 by photoetching.In this state, upper interconnect 17 is connected to the upper surface of columnar electrode 12 by the opening portion 16 in second insulating material 15.Copper Foil 1a and the metal film 1b that is formed on its lower surface form metal level 1.
As shown in figure 15, by silk screen printing or spin coating, on the entire upper surface of second insulating material 15 that comprises upper interconnect 17, form the top dielectric film 18 that constitutes by solder resist.In this case, top dielectric film 18 has opening portion 19 on the position of the connection pads part of corresponding upper interconnect 17.In addition, by forming the insulating barrier 2 that constitutes by solder resist on the lower surface that is spin-coated on metal level 1.Subsequently, on opening portion 19 neutralizes it, form projected electrode 20 and make it be connected to the connection pads part of upper interconnect 17.
As shown in figure 16, when cutting top dielectric film 18 between adjacent semiconductor member 3, first and second insulating material 14 and 15, metal level 1 and insulating barrier 2, obtain semiconductor device as shown in Figure 1.
In the semiconductor device that so obtains, the upper interconnect 17 of post on electrode 12 that be connected to semiconductor component 3 forms by electroless (or sputter) and plating.For this reason, can guarantee electrical connection between the corresponding columnar electrode 12 of each upper interconnect 17 and semiconductor component 3 reliably.
In above-mentioned manufacture method, a plurality of semiconductor components 3 are arranged on the Copper Foil 1a through adhesive phase 4.For a plurality of semiconductor components 3, can once form first and second insulating material 14 and 15, upper interconnect 17, top dielectric film 18 and projected electrode 20.Afterwards, the separating semiconductor structure, thus obtain a plurality of semiconductor device.Therefore, can simplify manufacturing step.In addition, find out that a plurality of semiconductor components 3 can be carried with Copper Foil 1a from manufacturing step shown in Figure 12.This has also simplified manufacturing step.
In above-mentioned manufacture method, as shown in figure 10, the CSP N-type semiconductor N member 3 with interconnection 11 and columnar electrode 12 bonds to Copper Foil 1a through adhesive phase 4.With for example at the standard semiconductor die bonding that has connection pads 6 and dielectric film 7 on the silicon substrate 5 to Copper Foil 1a, and the situation that interconnection and columnar electrode are formed on the diaphragm seal that forms around semiconductor chip compares, and reduced cost.
For example, Copper Foil 1a has the almost round-shaped of preliminary dimension before supposing to cut, as silicon wafer.In this case, if interconnection and columnar electrode are formed on the diaphragm seal of the semiconductor chip formation that bonds to Copper Foil 1a, then processing area increases.In other words, owing to carried out the low-density processing, therefore reduced the processed number of wafers of each circulation.This has reduced output and has increased cost.
On the contrary, in above-mentioned manufacture method, the CSP N-type semiconductor N member 3 with interconnection 11 and columnar electrode 12 bonds on the Copper Foil 1a through adhesive phase 4, carries out then and assembles (build-up).Increase although handle quantity, efficient has improved, because carried out the high density processing, till forming columnar electrode 12.For this reason, even considered to handle the increase of quantity, also can reduce total cost.
In the above-described embodiments, projected electrode 20 is arranged in matrix and corresponding with the whole surface of semiconductor component 3 and first insulating material 14 around it.Yet projected electrode 20 can only be arranged on the zone of first insulating material 14 around the corresponding semiconductor component 3.Projected electrode 20 always can form not around semiconductor component 3, and is formed on one to three side of four sides of semiconductor component 3.In this case, first insulating material 14 needn't have rectangular frame shape, and can only be arranged on the side that will form projected electrode 20.
(second embodiment)
Figure 17 is the profile according to the semiconductor device of second embodiment of the invention.The place that this semiconductor device is different from semiconductor device shown in Figure 1 is that it does not have insulating barrier 2.
When the semiconductor device of making according to second embodiment, in manufacturing step shown in Figure 15, on the lower surface of metal level 1, do not form insulating barrier 2.Form after the projected electrode 20 cutting top dielectric film 18, first and second insulating material 14 and 15 and metal level 1 between adjacent semiconductor member 3.Thereby, obtain a plurality of semiconductor device shown in Figure 17.So a plurality of semiconductor device that obtain can be very thin, because there is not insulating barrier 2.
(the 3rd embodiment)
Figure 18 is the profile according to the semiconductor device of third embodiment of the invention.This semiconductor device can obtain by saving at formation metal level 1b on the upper surface of Copper Foil 1a in manufacturing step shown in Figure 13 and form insulating barrier 2 in manufacturing step shown in Figure 15.
(the 4th embodiment)
Figure 19 is the profile according to the semiconductor device of fourth embodiment of the invention.This semiconductor device can obtain by saving at formation metal level 1b on the lower surface of Copper Foil 1a in manufacturing step shown in Figure 13 and save formation insulating barrier 2 in manufacturing step shown in Figure 15.
(the 5th embodiment)
Figure 20 is the profile according to the semiconductor device of fifth embodiment of the invention.The place that this semiconductor device is different from semiconductor device shown in Figure 1 is that it had not both had metal level 1 not have insulating barrier 2 yet.
When the semiconductor device of making according to the 5th embodiment, for example, in manufacturing step shown in Figure 15, save and on the lower surface of metal level 1, form insulating barrier 2.Form after the projected electrode 20, remove metal level 1 by polishing or etching.Subsequently, cutting top dielectric film 18 and first, second insulating material 14,15 between adjacent semiconductor member 3.Thereby, obtain a plurality of semiconductor device shown in Figure 20.So the semiconductor device that obtains can be very thin, because it does not have metal level 1 not have insulating barrier 2 yet.
(the 6th embodiment)
Figure 21 is the profile according to the semiconductor device of sixth embodiment of the invention.This semiconductor device can obtain in the following manner.For example, under state shown in Figure 19, remove metal level 1 by polishing or etching.Then, lower surface one side of the silicon substrate 5 that comprises adhesive phase 4 and lower surface one side of first insulating material 14 are suitably polished.Then, cutting top dielectric film 18 and first, second insulating material 14,15 between adjacent semiconductor member 3, thus obtain semiconductor device.So the semiconductor device that obtains can be very thinner.
Perhaps, before forming projected electrode 20, remove metal level 1 (if necessary, comprising that lower surface one side of silicon substrate 5 of adhesive phase 4 and lower surface one side of first insulating material 14 are also suitably polished) by polishing or etching.Then, form projected electrode 20, and between adjacent semiconductor member 3, cut top dielectric film 18 and first, second insulating material 14,15.
(the 7th embodiment)
Figure 22 is the profile according to the semiconductor device of seventh embodiment of the invention.The place that this semiconductor device is different from semiconductor device shown in Figure 1 is that it does not have metal level 1 not have insulating barrier 2 yet, but the substrate 31 that replaces them is arranged.
When the semiconductor device of making according to the 7th embodiment, in manufacturing step shown in Figure 10, saved and on the upper surface of substrate 31, formed adhesive phase 32 and Copper Foil 1a.The adhesive phase 4 of semiconductor component 3 through being formed on its lower surface bonds on the upper surface of substrate 31.On the lower surface of substrate 31, do not form whatever.Form after the projected electrode 20 cutting top dielectric film 18, first and second insulating material 14,15 and the substrates 31 between adjacent semiconductor member 3.Thereby, obtain a plurality of semiconductor device shown in Figure 22.
(the 8th embodiment)
Figure 23 is the profile according to the semiconductor device of eighth embodiment of the invention.The place that this semiconductor device is different from semiconductor device shown in Figure 1 is that lower interconnect 41 is formed on the lower surface of the adhesive phase 4 and first insulating material 14 and by vertical electrical connections 43 and is connected to upper interconnect 17, wherein vertical electrical connections 43 is formed on the inner surface of through hole 42, and through hole 42 is formed on the precalculated position of first and second insulating material 14 that form around semiconductor component 3 and 15.
When the semiconductor device of making according to the 8th embodiment, for example, after manufacturing step shown in Figure 11, remove substrate 31, adhesive phase 32 and Copper Foil 1a by polishing or etching.Then, as shown in figure 24, in second insulating material 15, forming opening portion 16 on the position of the core of the upper surface of corresponding columnar electrode 12 by laser processing.In addition, on the precalculated position of first and second insulating material 14 that are provided with around semiconductor component 3 and 15, form through hole 42.
As shown in figure 25, copper electroless-plating and copper are electroplated and are carried out continuously, thereby form upper interconnect cambium layer 17a on the entire upper surface of second insulating material 15 of the upper surface that comprises the columnar electrode 12 that exposes by opening portion 16.In addition, on the whole lower surface of the adhesive phase and first insulating material 14, form lower interconnect cambium layer 41a.Then, on the inner surface of through hole 42, form vertical electrical connections 43.
Then, by photoetching upper interconnect cambium layer 17a and lower interconnect cambium layer 41a are carried out composition.For example, as shown in figure 23, upper interconnect 17 is formed on the upper surface of second insulating material 15, and lower interconnect 41 is formed on the lower surface of the adhesive phase 4 and first insulating material 14, and vertical electrical connections 43 is stayed on the inner surface of through hole 42.
Describe below with reference to Figure 23.On the upper surface of second insulating material 15 that comprises upper interconnect 17, form the top dielectric film 18 that constitutes and have opening portion 19 by solder resist.In addition, the bottom dielectric film of being made by solder resist 44 is formed on the whole lower surface of first insulating material 14 that comprises lower interconnect 41.In this case, fill vertical electrical connections 43 with solder resist.Then, form projected electrode 20, and between adjacent semiconductor member 3, cut top dielectric film 18, first and second insulating material 14,15 and the bottom dielectric films 44.Thereby, obtain a plurality of semiconductor device shown in Figure 23.
(the 9th embodiment)
Figure 26 is the profile according to the semiconductor device of ninth embodiment of the invention.The place that this semiconductor device is different from semiconductor device shown in Figure 23 is that lower interconnect 41 is formed by Copper Foil 1a and the copper layer 41a that be formed on the lower surface of Copper Foil 1a, and in the vertical electrical connections 43 formation through holes 42 but do not form any gap.
When the semiconductor device of making according to the 9th embodiment, for example, in manufacturing step shown in Figure 12, in second insulating material 15, forming opening portion 16 on the position of the core of the upper surface of corresponding columnar electrode 12 by laser processing, as shown in figure 27.In addition, on the precalculated position of first and second insulating material 14,15 that are provided with around semiconductor component 3, form through hole 42.In this case, Copper Foil 1a is formed on the whole lower surface of the adhesive phase 4 and first insulating material 14.Therefore, lower surface one side of through hole 42 covers with Copper Foil 1a.
As shown in figure 28, use Copper Foil 1a to carry out copper and electroplate, thereby form vertical electrical connections 43 on the Copper Foil 1a upper surface in through hole 42 as the electroplating current path.In this case, the upper surface of vertical electrical connections 43 preferably almost flush with the upper plane of through hole 42 or be positioned at slightly under the position on.
Then, as shown in figure 29, copper electroless and copper are electroplated and are carried out continuously, so that form upper interconnect cambium layer 17a on the entire upper surface of second insulating material 15 of the upper surface of upper surface that comprises the columnar electrode 12 that exposes by opening portion 16 and the vertical electrical connections 43 in the through hole 42.In addition, on the whole lower surface of Copper Foil 1a, form lower interconnect cambium layer 41a.Then, utilize the manufacturing step identical, obtain a plurality of semiconductor device shown in Figure 26 with the 8th embodiment.
(the tenth embodiment)
Figure 30 is the profile according to the semiconductor device of tenth embodiment of the invention.The place that this semiconductor device is different from semiconductor device shown in Figure 1 is that it does not have second insulating material 15.
When making the semiconductor device of the tenth embodiment, after the manufacturing step as shown in figure 11, remove substrate 31 and adhesive phase 32.In addition, remove second insulating material 15 by polishing.In this case, when removing second insulating material 15,, then can not go wrong if comprise that upper surface one side of diaphragm seal 13 of columnar electrode 12 and semiconductor component 3 and upper surface one side of first insulating material 14 are slightly polished by polishing.
The manufacturing step of back is basically the same as those in the first embodiment.Yet in the tenth embodiment, as shown in figure 30, upper interconnect 17 is formed on the upper surface of the semiconductor component 3 and first insulating material 14 and is connected to the upper surface of columnar electrode 12.On upper interconnect 17, form top dielectric film 18 with opening portion 19.In opening portion 19 and on form projected electrode 20 and make it be connected to the connection pads part of upper interconnect 17.Although not shown,, certainly between columnar electrode 12, introduce upper interconnect 17 if columnar electrode 12 is arranged in matrix.
(the 11 embodiment)
Figure 31 is the profile according to the semiconductor device of eleventh embodiment of the invention.This semiconductor device obtains by remove second insulating material 15 by polishing in Figure 23, and is identical with the tenth embodiment.
(the 12 embodiment)
Figure 32 is the profile according to the semiconductor device of twelveth embodiment of the invention.This semiconductor device obtains by remove second insulating material 15 by polishing in Figure 26, and is the same with the tenth embodiment.
(the 13 embodiment)
In the above-described embodiments, for example, as shown in Figure 1, comprise that respectively upper interconnect 17 of one deck and top dielectric film 18 are formed on second insulating material 15.Yet, the invention is not restricted to this.Also can form and respectively comprise two-layer or more multi-layered upper interconnect 17 and top dielectric film 18.For example, identical with the 13rd embodiment of the present invention shown in Figure 33, each of upper interconnect 17 and top dielectric film 18 can have two-layer.
More particularly, in this semiconductor device, first upper interconnect 51 is formed on the upper surface of second insulating material 15 and by being formed on the upper surface that opening portion 16 in second insulating material 15 is connected to columnar electrode 12.The first top dielectric film 52 that is made of epoxy resin or polyimide resin is formed on the upper surface of second insulating material 15 that comprises first upper interconnect 51.Second upper interconnect 54 is formed on the upper surface of the first top dielectric film 52 and by being formed on the upper surface of connection pads part that opening portion 53 in the first top dielectric film 52 is connected to first upper interconnect 51.
The second top dielectric film 55 that is made of solder resist is formed on the upper surface of the first top dielectric film 52 that comprises second upper interconnect 54.The second top dielectric film 55 has opening portion 56 on the position of the connection pads part of corresponding second upper interconnect 54.Projected electrode 20 is formed in the opening portion 56 and is last and be connected to the connection pads part of second upper interconnect 54.In this case, have only Copper Foil 1a to be formed on the lower surface of the adhesive phase 4 and first insulating material 14.
(the 14 embodiment)
For example, in Figure 16, the member that cutting obtains between semiconductor component adjacent one another are 3.Yet, the invention is not restricted to this.The member that can obtain for every two or more semiconductor components cuttings.For example, as the 14th embodiment of the present invention, as shown in figure 34,, thereby obtain multi-chip module N-type semiconductor N device for per three semiconductor components 3 cut the member that obtains.In this case, three semiconductor components 3 can be phase homotypes or veriform.
In the above-described embodiments, the semiconductor component 3 and first insulating material 14 form following state: wherein the lower surface of semiconductor component 3 is supported by substrate 31.On the semiconductor component 3 and first insulating material 14, form after second insulating material 15, remove substrate 31.Retention substrate 31 not in the semiconductor device of finishing.Yet organic material such as epoxy-based material or polyimide-based material or the thin plate that is formed by thin metal film also can be as the materials of substrate 31.Form after upper interconnect 17 and the top dielectric film 18, as required, after forming projected electrode 20,, thereby stay the substrate parts of substrate 31 as semiconductor device with top dielectric film 18, second insulating material 15 and first insulating material, 14 cutting substrates 31.In this case, can on substrate 31 surfaces of the opposition side of the installation surface of semiconductor component 3, form after interconnection waits the cutting substrate.
In above-mentioned the first to the 14 embodiment, the lower surface that semiconductor device supports each semiconductor component 3 by substrate 31 simultaneously by the formation dielectric film is basically made.
Yet semiconductor device can be made by the upper surface that substrate 31 supports each semiconductor component 3 simultaneously by forming dielectric film and interconnection.This method is with following detailed description.
(the 15 embodiment)
Semiconductor device according to the 15 embodiment shown in Figure 35 is represented an embodiment with back kind method manufacturing.The purpose of noting this embodiment be represent that structure not only shown in Figure 35 can obtain but also have the semiconductor device of one of structure according to above-mentioned the first to the 14 embodiment by back kind method also can be by back kind method manufacturing.This will describe in proper step below.
The place that semiconductor device shown in Figure 35 is different from the semiconductor device of the first to the 14 embodiment is: the lower surface of semiconductor component 3 directly bonds on the insulating barrier 2 and does not need to insert any adhesive phase.By printing or be spin-coated on and form insulating barrier 2 on the lower surface of semiconductor component 3, this will be explained below.
Introduce manufacture method below according to the semiconductor device of the 15 embodiment.
Utilize the step shown in Fig. 2-7, on the silicon substrate 5 of wafer state, form interconnection 11 and diaphragm seal 13, so as to interconnect 11 and diaphragm seal 13 flush each other.
In this state, not be used in and form any adhesive phase on the lower surface of silicon substrate 5, cut, thereby obtain a plurality of semiconductor components 3 shown in Figure 35, as shown in figure 36.
As shown in figure 37, preparation substrate 31.Substrate 31 has a plurality of semiconductor device corresponding shown in Figure 35.Substrate 31 is made by metal such as aluminium, and has rectangular planar shape, more preferably, have almost square plan-form shapes, but shape is not limited thereto.Substrate 31 can be made by insulating material such as glass, pottery or resin.
The second insulation plate 15a bonds to the entire upper surface of substrate 31.The second insulation plate 15a is preferably made by aggregate material, but the invention is not restricted to this.As aggregate material, can adopt thermosetting resin such as epoxy resin or BT resin formation with silica filler mixing and semi-solid preparation.Yet as the second insulation plate 15a, above-mentioned pre impregnated material or the material that does not contain filler or only contain thermosetting resin all can use.Thermosetting resin is by heating and pressurization and semi-solid preparation (semi-set), and the second insulation plate 15a bonds on the entire upper surface of substrate 31.
Respectively having two first insulation plate 14a of the opening portion that is arranged in matrix and 14b aims on the upper surface of the insulation of second between the semiconductor component 3 plate 15a and piles up and be between the semiconductor component outside that is provided with on the outermost position.The first insulation plate 14a and 14b obtain in the following way.Inject glass fibre with thermosetting resin such as epoxy resin.Thermosetting resin is a semi-solid preparation, so that prepare tabular pre impregnated material.By die-cut or be etched in the pre impregnated material and form a plurality of rectangular aperture parts 33.
In this case, in order to obtain flatness, each first insulation plate 14a and 14b must be plate-shaped members.Yet this material needn't be always pre impregnated material.Also can adopt thermosetting resin or wherein disperse reinforcing material such as the thermosetting resin of glass fibre or silica filler.
The size that the size of the opening portion 33 of the first insulation plate 14a and 14b is a bit larger tham semiconductor component 3.For this reason, between the first insulation plate 14a and 14b and semiconductor component 3, form gap 34.The length in gap 34 for example is approximately 0.1-0.5mm.The gross thickness of the first insulation plate 14a and 14b is greater than the thickness of semiconductor component 3.The first insulation plate 14a and 14b are enough thick, so that fully fill gap 34 when heating and pressurize the first insulation plate, this will be explained below.
In this case, use first insulation plate 14a and the 14b with same thickness.Yet the first insulation plate 14a and 14b can have different-thickness.The second insulation plate can comprise two-layer, as mentioned above.Yet, can comprise one deck or three layers or more multi-layered.The thickness of the second insulation plate 15a is corresponding or be a bit larger tham the thickness of second insulating material 15 that will form on semiconductor component 3 among Figure 35.
Then, by using a pair of heat/pressure plate 35 and the 36 pairs second insulation plate 15a and the first insulation plate 14a and 14b to heat and pressurizeing, as shown in figure 38.Thereby, thereby the thermosetting resin of the fusing among the first insulation plate 14a and the 14b is extruded the gap 34 of filling between the first insulation plate 14a, 14b and the semiconductor component 3, as shown in figure 37.By follow-up cooling processing, thermosetting resin curing bonds to semiconductor component 3 simultaneously.In this way, as shown in figure 38, second insulating material of being made by the thermosetting resin that contains reinforcing material 15 forms and bonds on the upper surface of substrate 31.In addition, semiconductor component 3 bonds on the upper surface of second insulating material 15.In addition, first insulating material of being made by the thermosetting resin that contains reinforcing material 14 forms and is bonded on the upper surface of second insulating material 15.
In this case, as shown in figure 36, under wafer state, the columnar electrode 12 in each semiconductor component 3 has even height.In addition, it is flattened to comprise the upper surface of diaphragm seal 13 of upper surface of columnar electrode 12.For this reason, under state shown in Figure 38, a plurality of semiconductor components 3 have same thickness.
Under state shown in Figure 38, heat and pressurize, simultaneously as the pressure limit surface, limit the virtual plane of the upper surface that is higher than semiconductor component 3 by the diameter of reinforcing material (for example silica filler).Second insulating material, 15 acquisitions below the semiconductor component 3 equal the thickness of the diameter of reinforcing material (for example silica filler).When beginning (opening) smooth forcing press when having the forcing press of a pair of heat/ pressure plate 35 and 36, unnecessary thermosetting resin is extruded this to heating/ heating plate 35 and 36 among insulation plate 14a, 14b and the 15a.
The result is, the upper surface of first insulating material 14 upper surface flush with semiconductor component 3 that becomes.The lower surface of second insulating material 15 is smooth because should the surface by the upper surface adjustment of the heat/pressure plate 35 of downside.Therefore, needn't carry out the polishing step that the lower surface to the upper surface of first insulating material 14 and second insulating material 15 carries out complanation.Even substrate 31 has relative large scale, for example be approximately 500 * 500mm, also can once carry out complanation at an easy rate with respect to a plurality of semiconductor components 3 that are arranged on the substrate 31 to first and second insulating material 14,15.
First and second insulating material 14 and 15 are made of the thermosetting resin that contains reinforcing material such as fiber or filler., compare for this reason, can reduce because the stress that the contraction in the curing of thermosetting resin produces with the structure that only constitutes by thermosetting resin.This has also prevented substrate 31 bendings.
In manufacturing step shown in Figure 38, heating and pressurization can be carried out by the device that separates.That is, for example, pressurization can only be carried out from upper surface one side, utilizes the lower surface heating of heater to semiconductor component 3 simultaneously.Perhaps, heating and pressurization can be carried out in the step of separating.
When manufacturing step shown in Figure 38 finished, the semiconductor component 3 and first and second insulating material 14 and 15 were integrated in together.They only keep required intensity.Then, peel off or remove substrate 31 by polishing or etching.Carry out this processing, so that reduce the load in the cutting (will be explained below) and reduce thickness as the semiconductor device of product.
Then, supine state is inverted and is arranged to the member that obtains shown in Figure 38 that the wherein semiconductor component 3 and first and second insulating material 14,15 are integrated.As shown in figure 39, by laser engine processing method, on the position of the core of the upper surface of corresponding columnar electrode 12, in second insulating material 15, form opening portion 16 with laser beam irradiation second insulating material 15.Then, as required, handle the epoxy oil stain of removing generation in the opening portion 16 by deoiling.
As shown in figure 40, upper interconnect cambium layer 17a is formed on the entire upper surface of second insulating material 15, comprises the upper surface of the columnar electrode 12 that exposes by opening portion 16.In this case, upper interconnect cambium layer 17a comprises the lower metal layer that is formed by for example copper layer and is formed on the lip-deep metal level of going up of lower metal layer, wherein said copper layer forms by electroless, the described metal level of going up is by using lower metal layer as the electroplating current path, electroplates and forms by carrying out copper.
When upper interconnect cambium layer 17a being carried out composition, on the precalculated position of the upper surface of second insulating material 15, form upper interconnect 17, as shown in figure 41 by photoetching.In this state, upper interconnect 17 is connected to the upper surface of columnar electrode 12 by the opening portion 16 in second insulating material 15.
As shown in figure 42, by silk screen printing or spin coating, on the entire upper surface of second insulating material 15 that comprises upper interconnect 17, form the top dielectric film 18 that constitutes by solder resist.In this case, top dielectric film 18 has opening portion 19 on the position of the connection pads part of corresponding upper interconnect 17.In addition, by printing or be spin-coated on and form the insulating barrier 2 that constitutes by solder resist on the lower surface of the silicon substrate 5 and first insulating material 14.Subsequently, in opening portion 19 and on form projected electrode 20 and make it be connected to the connection pads part of upper interconnect 17.
As shown in figure 43, when cutting top dielectric film 18 between adjacent semiconductor member 3, first and second insulating material 14 and 15 and during insulating barrier 2, obtain semiconductor device as shown in figure 35.
In the semiconductor device that so obtains, the upper interconnect 17 of post on electrode 12 that be connected to semiconductor component 3 forms by electroless (or sputter) and plating.For this reason, can guarantee electrical connection between the corresponding columnar electrode 12 of each upper interconnect 17 and semiconductor component 3 reliably.Under state shown in Figure 41, bonding when insulating barrier 2 usefulness adhesive phases with metal level 1, replace on the lower surface of the silicon substrate 5 and first insulating material 14, forming insulating barrier 2, can obtain the semiconductor device according to first embodiment shown in Figure 1.Should be fully understood that any the semiconductor device according to the second to the 14 embodiment that also can obtain except first embodiment, specify although omitted.
In above-mentioned manufacture method, a plurality of semiconductor components 3 are set in place on the insulation of second on the substrate 31 plate 15a.For a plurality of semiconductor components 3, can once form first and second insulating material 14 and 15.Afterwards, remove substrate 31.Then, for a plurality of semiconductor components 3, once form upper interconnect 17, top dielectric film 18 and projected electrode 20.Afterwards, the separating semiconductor member, thus obtain a plurality of semiconductor device.Therefore, can simplify manufacturing step.
In addition, find out that even remove substrate 31, a plurality of semiconductor components 3 also can be carried with first and second insulating material 14 and 15 from manufacturing step shown in Figure 38.This has also simplified manufacturing step.In addition, in above-mentioned manufacture method, as shown in figure 37, semiconductor component 3 bonds to substrate 31 through the second insulation plate 15a.Therefore, do not need to be used to form the technology of bonding difference.When removing substrate 31, have only substrate 31 to be removed.This has also simplified manufacturing step.
In above-mentioned manufacture method, projected electrode 20 is arranged in the whole surface of matrix and corresponding semiconductor component 3 and first insulating material 14 around it.Yet projected electrode 20 can only be arranged on the zone of first insulating material 14 around the corresponding semiconductor component 3.Projected electrode 20 can be all around semiconductor component 3, and just the side in the middle of four sides of semiconductor component 3 to three sides.In this case, first insulating material 14 needn't have rectangular frame shape and can only be arranged on the side that will form projected electrode 20.
(the 16 embodiment)
Figure 44 is the profile according to the semiconductor device of sixteenth embodiment of the invention.The place that this semiconductor device is different from semiconductor device shown in Figure 35 is that it does not have insulating barrier 2.
In manufacturing, in manufacturing step shown in Figure 42, on the lower surface of the silicon substrate 5 and first insulating material 14, do not form insulating barrier 2 according to the semiconductor device of the 16 embodiment.Form after the projected electrode 20 cutting top dielectric film 18 and first and second insulating material 14 and 15 between adjacent semiconductor member 3.Thereby, obtain a plurality of semiconductor device shown in Figure 44.So the semiconductor device that obtains can be very thin, because it does not have insulating barrier 2.
(the 17 embodiment)
Figure 45 is the profile according to the semiconductor device of seventeenth embodiment of the invention.This semiconductor device can obtain in the following way: for example, under state shown in Figure 44, suitably lower surface one side of the polished silicon substrate 5 and first insulating material 14 and between adjacent semiconductor member 3 cutting top dielectric film 18 and first and second insulating material 14 and 15.So the semiconductor device that obtains can be thinner.
Before forming projected electrode 20, can remove insulating barrier 2 (can suitably polish if necessary) by polishing or etching to lower surface one side of the silicon substrate 5 and first insulating material 14.Then, projected electrode 20 can be formed, and the top dielectric film 18 and first insulating material 14 can be between adjacent semiconductor member 3, cut.
(the 18 embodiment)
Figure 46 is the profile according to the semiconductor device of eighteenth embodiment of the invention.The place that this semiconductor device is different from semiconductor device shown in Figure 35 is that the second insulating material 15A is arranged on the upper surface of semiconductor component 3, and the first insulating material 14A is arranged on the upper surface of the insulating barrier 2 of the semiconductor component 3 and the second insulating material 15A.
In the manufacturing according to the semiconductor device of the 18 embodiment, after the manufacturing step shown in Figure 7, the tabular first insulation plate 15A bonds on the entire upper surface of diaphragm seal 13 of the upper surface that comprises columnar electrode 12, as shown in figure 47.
Then, as shown in figure 48, carry out cutting step, thereby obtain a plurality of semiconductor components 3.Yet in this case, the first insulation plate 15A bonds on the upper surface of diaphragm seal 13 of the upper surface that comprises semiconductor component 3.So the semiconductor component 3 that obtains has the lip-deep tabular first insulation plate 15A thereon.Therefore, do not need to be used for the first insulation plate 15A is bonded to the very operation of trouble on the upper surface of each semiconductor component 3 after the cutting step.
As shown in figure 49, semiconductor component shown in Figure 48 3 is inverted also and is arranged to ventricumbent state, thereby the first insulation plate 15A that bonds to the lower surface of semiconductor component 3 bonds to by the first insulation plate 15A that uses proper viscosity on a plurality of precalculated positions of upper surface of substrate 31.Heat and pressurize, thereby the thermosetting resin among the first insulation plate 15A is temporarily solidified, so that the lower surface of the first insulation plate 15A temporarily bonds on the upper surface of substrate 31.In addition, the lower surface of semiconductor component 3 temporarily bonds on the upper surface of the first insulation plate 15A.Respectively have two first of opening portion 33 insulation plate 14a and 14b between the semiconductor component 3 and the upper surface that is arranged on the substrate 31 between the outside of semiconductor component 3 of most external position aim at and pile up.
Equally in this case, the size of the opening portion 33 of first insulation plate 14a and the 14b size of being a bit larger tham semiconductor component 3.For this reason, formation gap 34 between first insulation plate 14a and the 14b and the semiconductor component 3 that comprises the first insulation plate 15A.The length in gap 34 for example is approximately 0.1-0.5mm.The gross thickness of the first insulation plate 14a and 14b is greater than the thickness of the semiconductor component 3 that comprises the first insulation plate 15A.The first insulation plate 14a and 14b are enough thick so that fully fill gap 34 when heating and suppress the first insulation plate, as described later.
Then, use a pair of heat/pressure plate 35 and the 36 pairs first insulation plate 15A and the first insulation plate 14a and 14b to heat and pressurize, as shown in figure 50.Thereby, thereby the thermosetting resin of the fusing among the first insulation plate 14a and the 14b is extruded the gap 34 between the semiconductor component 3 of filling the first insulation plate 14a, 14b and comprising the first insulation plate 15A, as shown in figure 49.By follow-up cooling processing, thermosetting resin curing bonds on semiconductor component 3 and the substrate between them 31 simultaneously.
In this way, as shown in figure 50, the second insulating material 15A that is made by the thermosetting resin that contains reinforcing material forms and bonds on a plurality of precalculated positions of upper surface of substrate 31.In addition, semiconductor component 3 bonds on the upper surface of the second insulating material 15A.In addition, first insulating material 14 that is made of the thermosetting resin that contains reinforcing material forms and bonds to semiconductor component 3 and on the upper surface of the substrate 31 between the semiconductor component outside on the outermost position.Utilize the manufacturing step identical, obtain semiconductor device shown in Figure 46 with the 15 embodiment.
In the above-described embodiments, except connection pads 6, semiconductor component 3 has as the interconnection 11 of external connecting electrode and columnar electrode 12.The present invention can also be applicable to following semiconductor component 3: it has only as the connection pads 6 of external connecting electrode or connection pads 6 and has connection pads interconnection 11 partly.
Describe as the front, according to the present invention, the connection pads of at least some top side upper interconnect partly is arranged on first insulating material that is formed on semiconductor component one side.For this reason, even the quantity of the connection pads of top side upper interconnect part increases, also can guarantee required size and spacing.
Claims (45)
1, a kind of semiconductor device, its spy just is being to comprise:
At least one semiconductor component (3) has a Semiconductor substrate (5) and is formed on a plurality of external connecting electrodes (6) on the Semiconductor substrate;
Be arranged on insulation plate on semiconductor component (3) one sides (14,14A); With
A plurality of upper interconnect (17,54) with a plurality of connection pads part, wherein connection pads partly is arranged on insulation plate (14,14A) and goes up and corresponding upper interconnect, and is electrically connected to the external connecting electrode (6) of semiconductor component (3).
2, semiconductor device according to claim 1 is characterized in that comprising a plurality of semiconductor components (3).
3, semiconductor device according to claim 1 is characterized in that semiconductor component (3) comprises at least one connection pads (6), is connected to the column external connecting electrode (12) of connection pads (6) and is formed on external connecting electrode (12) diaphragm seal (13) on every side.
4, semiconductor device according to claim 1, the plate that it is characterized in that insulating (14,14A) is mainly by making by the material for preparing with the thermosetting resin impregnation of fibers.
5, semiconductor device according to claim 1 is characterized in that insulating material (15) is formed between insulation plate (14) and the upper interconnect (17) and insulate between plate (14) and the semiconductor component (3).
6, semiconductor device according to claim 5 is characterized in that insulating material (15,15A) is a plate.
7, semiconductor device according to claim 5 is characterized in that the upper surface of insulating material (15,15A) is smooth.
8, semiconductor device according to claim 1 is characterized in that also comprising top dielectric film (18,52), covers the connection pads part part in addition of upper interconnect (17,54).
9, semiconductor device according to claim 8 is characterized in that solder ball (20) is formed on each connection pads part of upper interconnect (17,54).
10, semiconductor device according to claim 1 is characterized in that metal level (1,1a) is formed on the lower surface of semiconductor component (3) and insulation plate (14,14A).
11, semiconductor device according to claim 10 is characterized in that insulating barrier (2) is formed on the lower surface of metal level (1).
12, semiconductor device according to claim 10 is characterized in that metal level (1,1a) has metal forming at least.
13, semiconductor device according to claim 12 is characterized in that metal forming is a Copper Foil.
14, semiconductor device according to claim 1, it is characterized in that lower interconnect (41) is formed on the lower surface at least of insulation plate (14,14A), and upper interconnect (17) and lower interconnect (41) are connected by the vertical electrical connections (43) that is formed in the plate (14) that insulate.
15, semiconductor device according to claim 1, the plate (14) that it is characterized in that insulating has the sandwich construction of a plurality of insulation plates (14a, 14b).
16, semiconductor device according to claim 1 is characterized in that insulating material (15A) is formed between insulating element (14A) and the upper interconnect (17), and the upper surface of insulation plate (14A) and the upper surface flush of insulating material (15A).
17, a kind of method, semi-conductor device manufacturing method comprises:
A plurality of semiconductor components (3) are set on substrate (31), wherein each semiconductor component has a Semiconductor substrate (5) and a plurality of connection pads (6), simultaneously semiconductor component is separated from each other and the insulation plate (14) that at least one has opening portion (33) is set on the position of corresponding semiconductor component (3);
From the upside heating and the pressurization insulation plate (14) of insulation plate (14), thereby the plate (14) that will insulate melts and is solidificated between the semiconductor component;
Form one deck upper interconnect (17,54) at least, this upper interconnect has connection pads part and is connected on corresponding of a plurality of connection pads (6) of one of a plurality of semiconductor components (3), so that to should connection pads partly being placed on the insulation plate (14) upper interconnect; With
Cutting insulation plate (14) between semiconductor component (3), thus a plurality of semiconductor device obtained, and wherein the connection pads of upper interconnect (17,54) partly is arranged on the insulation plate (14).
18, method, semi-conductor device manufacturing method according to claim 17 is characterized in that semiconductor component (3) comprises connection pads (6), is connected to the column external connecting electrode (12) of connection pads (6) and is formed on external connecting electrode (12) diaphragm seal (13) on every side.
19, method, semi-conductor device manufacturing method according to claim 17 is characterized in that insulation plate (14) is cut into and makes each semiconductor device comprise a plurality of semiconductor components (3) when cutting insulation plate (14).
20, method, semi-conductor device manufacturing method according to claim 17 is characterized in that removing substrate (31) at cutting insulation plate (14) before.
21, method, semi-conductor device manufacturing method according to claim 17 is characterized in that cutting insulated substrate (14) afterwards, removes substrate (31).
22, method, semi-conductor device manufacturing method according to claim 17 is characterized in that carrying out being provided with when heat/pressure is handled the pressure limit surface.
23, method, semi-conductor device manufacturing method according to claim 17, the size that the size of the opening portion (33) of plate (14) that it is characterized in that insulating is a bit larger tham semiconductor component (3).
24, method, semi-conductor device manufacturing method according to claim 23 is characterized in that being arranged on the thickness of the thickness of the insulation plate (14) on the substrate (31) greater than semiconductor component (3).
25, method, semi-conductor device manufacturing method according to claim 17, the plate (14) that it is characterized in that insulating are mainly by constituting by the material for preparing with the thermosetting resin impregnation of fibers.
26, method, semi-conductor device manufacturing method according to claim 17 is characterized in that also being included in the step that forms insulating material (15) between (14) and the upper interconnect (17).
27, method, semi-conductor device manufacturing method according to claim 26 is characterized in that insulating material (15) is a plate.
28, method, semi-conductor device manufacturing method according to claim 17 is characterized in that also being included in and semiconductor component (3) and insulation plate (14) is set before on the substrate (31), goes up the film (1a) that formation will be removed from substrate (31) at substrate (31).
29, method, semi-conductor device manufacturing method according to claim 28 is characterized in that film (1a) mainly is made of metal.
30, method, semi-conductor device manufacturing method according to claim 28 is characterized in that cutting film (1a) with insulation plate (14) when cutting insulation plate (14).
31, method, semi-conductor device manufacturing method according to claim 28 is characterized in that being provided with semiconductor component (3) and insulation plate (14) afterwards on film (1a), make the temporary transient curing of insulation plate (14).
32, method, semi-conductor device manufacturing method according to claim 31 is characterized in that removing substrate (31) after temporary transient curing.
33, method, semi-conductor device manufacturing method according to claim 28 is characterized in that removing substrate (31) afterwards, goes up at film (1a) and forms another film (1b, 2).
34, method, semi-conductor device manufacturing method according to claim 28 is characterized in that film (1a) is a metal forming, and described another film (1b) is a metal forming.
35, method, semi-conductor device manufacturing method according to claim 28 is characterized in that described another film (2) mainly made by insulating material.
36, a kind of method, semi-conductor device manufacturing method is characterized in that described another film (1b, 2) is to form by piling up a plurality of layers of being made by different materials.
37, method, semi-conductor device manufacturing method according to claim 33 is characterized in that when cutting insulation plate (14), cutting insulation plate (14), film (1a) and described another film (1b, 2).
38, method, semi-conductor device manufacturing method according to claim 17 is characterized in that when cutting insulation plate, cutting insulation plate (14), and while cutting substrate (31) is so that semiconductor device has substrate (31).
39, method, semi-conductor device manufacturing method according to claim 17 is characterized in that also comprising the step that forms top dielectric film (18,55), and this top dielectric film (18,55) covers the connection pads part part in addition of upper interconnect (17,54).
40,, it is characterized in that the connection pads that also is included in upper interconnect (17,54) partly goes up the step that forms solder ball (20) according to the described method, semi-conductor device manufacturing method of claim 39.
41, method, semi-conductor device manufacturing method according to claim 17, it is characterized in that also being included in formation through hole (42) in the insulation plate (14), form lower interconnect (41) and form vertical electrical connections (43) on the lower surface of insulation plate (14) in through hole (42), wherein vertical electrical connections (43) connects upper interconnect (17) and lower interconnect (41).
42,, it is characterized in that removing substrate forming through hole (42), lower interconnect (41) and vertical electrical connections (43) before according to the described method, semi-conductor device manufacturing method of claim 41.
43, method, semi-conductor device manufacturing method according to claim 17, it is characterized in that this method also is included in substrate (31) and goes up formation top dielectric film (15a), and semiconductor component (3) is arranged on the top dielectric film (15a), form one and top dielectric film (15a) facing surfaces simultaneously, on this surface, form described connection pads.
44,, it is characterized in that semiconductor component (3) comprises connection pads (6), is connected to the column external connecting electrode (12) of connection pads (6) and is formed on external connecting electrode (12) diaphragm seal (13) on every side according to the described method, semi-conductor device manufacturing method of claim 43.
45,, it is characterized in that insulating element (14) is arranged on the top dielectric film (15a) according to the described method, semi-conductor device manufacturing method of claim 43.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
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| JP008552/2003 | 2003-01-16 | ||
| JP008551/2003 | 2003-01-16 | ||
| JP2003008551A JP2004221417A (en) | 2003-01-16 | 2003-01-16 | Semiconductor device and its producing method |
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| CN1698198A true CN1698198A (en) | 2005-11-16 |
| CN100397629C CN100397629C (en) | 2008-06-25 |
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| CNB2004800000580A Expired - Fee Related CN100397629C (en) | 2003-01-16 | 2004-01-16 | Semiconductor device and method of manufacturing the same |
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| JP (1) | JP2004221417A (en) |
| CN (1) | CN100397629C (en) |
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| JP2004221417A (en) | 2004-08-05 |
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