JP2006269594A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2006269594A
JP2006269594A JP2005083403A JP2005083403A JP2006269594A JP 2006269594 A JP2006269594 A JP 2006269594A JP 2005083403 A JP2005083403 A JP 2005083403A JP 2005083403 A JP2005083403 A JP 2005083403A JP 2006269594 A JP2006269594 A JP 2006269594A
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semiconductor device
layer
insulating layer
semiconductor structure
external connection
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Manabu Yamada
学 山田
Jun Yoshizawa
潤 吉澤
Yutaka Yoshino
裕 吉野
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Nippon CMK Corp
CMK Corp
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Nippon CMK Corp
CMK Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with a thin total thickness and excellent in connection reliability, and to provide a manufacturing method thereof. <P>SOLUTION: The semiconductor device includes a semiconductor structure 2 having a plurality of external connection electrodes 4, a support for supporting the semiconductor structure 2, insulation layers 8b, 8c formed at the side of the semiconductor structure 2, and conductor layers 5 located on external connection electrodes 4 of the semiconductor structure 2 and the insulation layers 8b, 8c at sides of the semiconductor structure 2. The manufacturing method of the semiconductor device includes steps of arranging the semiconductor structure 2 on the upper side of which a plurality of the external connection electrodes 4 are arranged via an adhesive agent 3, arranging and laminating the insulation layers 8b, 8c at the sides of the semiconductor structure 2, precipitating electroless/electrolytic metallic plating after the lamination step, and forming a wire circuit 1 by a photographic method after the plating precipitation step. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、ウエハーレベルＣＳＰ (wafer-level chip size package)を有機基板に内蔵した半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device in which a wafer level CSP (wafer-level chip size package) is built in an organic substrate and a manufacturing method thereof.

最近、電子機器の軽薄短小化が進み、機器に搭載されるウエハーレベルＣＳＰ(wafer-level chip size package）と呼ばれる半導体装置が使用されている。このウエハーレベルＣＳＰは、一般に複数の外部接続用の接続パッドが形成されたベアーの半導体装置の上面にパッシベーション膜を設け、次いで、該パッシベーション膜の各接続パッドに対応する開口部を形成し、次いで、該開口部を介して各接続パッドに接続される再配線を形成し、次いで、各再配線の他の接続部に柱状の外部接続用電極を形成するとともに、絶縁樹脂で封止後、研磨にて外部接続用電極が露出するまで研磨し、次いで、露出した外部接続用電極にはんだを形成することによって製造されている（例えば、特許文献１参照）。   In recent years, electronic devices have become lighter, thinner, and smaller, and a semiconductor device called a wafer level CSP (wafer-level chip size package) mounted on the device is used. In this wafer level CSP, generally, a passivation film is provided on the upper surface of a bare semiconductor device in which a plurality of connection pads for external connection are formed, and then an opening corresponding to each connection pad of the passivation film is formed. Then, a rewiring connected to each connection pad through the opening is formed, and then a columnar external connection electrode is formed on the other connection portion of each rewiring, and after sealing with an insulating resin, polishing The external connection electrode is polished until exposed, and then solder is formed on the exposed external connection electrode (see, for example, Patent Document 1).

しかしながら、通常ウエハーレベルＣＳＰは、ベアチップの半導体装置の上面に外部接続用電極をマトリクス状に配列するため、外部接続用電極数の多い半導体装置では外部接続用電極サイズ及びピッチが極端に小さくなってしまう結果、マザーボードとの接続が困難になる問題があった。すなわち、外部接続用電極のピッチが小さくなればマザーボードとの位置合わせが困難であるばかりでなく接合強度が不足し、ボンディング時に電極間の短絡が発生する。また、シリコンからなる半導体装置とマザーボードでは線膨張係数の差に起因して発生する応力により外部接続用電極が断線してしまう問題が発生する。   However, the wafer level CSP usually has external connection electrodes arranged in a matrix on the top surface of a bare chip semiconductor device, so that the size and pitch of the external connection electrodes are extremely small in a semiconductor device having a large number of external connection electrodes. As a result, there is a problem that it is difficult to connect to the motherboard. That is, if the pitch of the electrodes for external connection is reduced, not only the alignment with the mother board is difficult, but also the bonding strength is insufficient, and a short circuit between the electrodes occurs during bonding. In addition, there is a problem that the external connection electrode is disconnected due to the stress generated due to the difference in linear expansion coefficient between the semiconductor device made of silicon and the mother board.

さらに、シリコンからなる半導体装置のマトリクス状の配線を狭ピッチにすることは可能だが、マザーボードと精度よく接続する関係からこれ以上半導体装置を小さくできないという問題も発生していた。   Furthermore, although it is possible to reduce the matrix wiring of the semiconductor device made of silicon to a narrow pitch, there has been a problem that the semiconductor device cannot be further reduced due to the high-precision connection with the mother board.

そこで、シリコンからなる半導体装置を小さくして、マトリクス状の狭ピッチ配線を形成し、外部接続用電極を形成し、絶縁樹脂で封止し、個片化した半導体構成体を有機基板に埋め込み再配線することでマザーボードに精度よく実装できる配線ピッチが可能となる半導体装置が提案されている（例えば、特許文献２参照）。
特開２００１−１６８１２８号公報 特開２００４−２２１４１７号公報 Therefore, the semiconductor device made of silicon is reduced to form a matrix-like narrow pitch wiring, an external connection electrode is formed, sealed with an insulating resin, and the separated semiconductor structure is embedded in an organic substrate. There has been proposed a semiconductor device capable of wiring pitch that can be mounted on a mother board with high accuracy by wiring (for example, see Patent Document 2).
JP 2001-168128 A JP 2004-221417 A

しかしながら、半導体構成体の上層に複数層の絶縁層を重ね、再配線を繰り返すとどうしても総板厚が厚くなるため、特に、携帯電子機器などのモバイル製品に適用しようとしても、厚み制限で採用されないという問題が発生していた。   However, if a plurality of insulating layers are stacked on the upper layer of the semiconductor structure and rewiring is repeated, the total plate thickness inevitably increases. Therefore, even if it is applied to mobile products such as portable electronic devices, it is not adopted due to thickness restrictions. The problem that occurred.

一方、シリコンからなる半導体装置と側方に形成される絶縁層の線膨張係数の差を緩和するためにはどうしても外部接続用電極の高さを５０μｍ以下にすることができず、しかも、シリコンを薄くするには時間がかかる上、ウエハーの反りやウエハーへのマイクロクラックが発生し易いため、ウエハーレベルＣＳＰを薄く加工することは困難なのが実状であった。   On the other hand, in order to alleviate the difference in coefficient of linear expansion between the semiconductor device made of silicon and the insulating layer formed on the side, the height of the external connection electrode cannot be reduced to 50 μm or less. It takes a long time to make the wafer thin, and the wafer warp and microcracks are likely to occur on the wafer, so that it is difficult to thin the wafer level CSP.

本発明は、上記の問題と実状に鑑みてなされたもので、総板厚の薄い、しかも接続信頼性に優れた半導体装置及びその製造法を提供することを課題とする。   The present invention has been made in view of the above problems and actual circumstances, and an object thereof is to provide a semiconductor device having a thin total plate thickness and excellent in connection reliability and a method for manufacturing the same.

本発明は、上面に複数の外部接続部を有する半導体構成体と、前記半導体構成体を支える支持体と、前記半導体構成体の側方に設けられた絶縁層とを有し、かつ前記半導体構成体の外部接続用電極上及び前記側方に設けられた絶縁層上に導体層が設けられている半導体装置により上記課題を解決したものである。   The present invention includes a semiconductor structure having a plurality of external connection portions on an upper surface, a support that supports the semiconductor structure, and an insulating layer provided on a side of the semiconductor structure, and the semiconductor structure This problem is solved by a semiconductor device in which a conductor layer is provided on an external connection electrode of a body and an insulating layer provided on the side.

また、本発明は、支持体に接着剤を介して、上面に複数の外部接続用電極を有する半導体構成体を配置する工程と、前記半導体構成体の側方に絶縁層を配置し積層する工程と、前記積層工程後、無電解・電解金属めっきを析出する工程と、前記めっき析出工程後、写真法にて配線回路を形成する工程とを有する半導体装置の製造方法により上記課題を解決したものである。   The present invention also includes a step of disposing a semiconductor structure having a plurality of external connection electrodes on the upper surface via an adhesive on the support, and a step of disposing and laminating an insulating layer on the side of the semiconductor structure. And a method of manufacturing a semiconductor device comprising: a step of depositing electroless / electrolytic metal plating after the laminating step; and a step of forming a wiring circuit by a photographic method after the plating deposition step. It is.

また、本発明は、支持体に接着剤を介して、上面に複数の外部接続用電極を有する半導体構成体を配置する工程と、前記半導体構成体の側方に絶縁層を配置し積層する工程と、前記積層工程後、スパッタリングで金属皮膜を成膜する工程と、前記成膜工程後、電解金属めっきを形成する工程と、前記めっき析出工程後、写真法にて配線回路を形成する工程とを有する半導体装置の製造方法により上記課題を解決したものである。   The present invention also includes a step of disposing a semiconductor structure having a plurality of external connection electrodes on the upper surface via an adhesive on the support, and a step of disposing and laminating an insulating layer on the side of the semiconductor structure. And a step of forming a metal film by sputtering after the laminating step, a step of forming electrolytic metal plating after the film forming step, and a step of forming a wiring circuit by a photographic method after the plating deposition step, The above-described problems are solved by a method for manufacturing a semiconductor device having the above.

本発明半導体装置は、半導体構成体の外部接続用電極上及び側方の絶縁層上に導体層が設けられているため、換言すれば従来配線回路を設けていない層に導体回路を設けているため、上層の配線層を１層以上減らすことができる結果、ウエハーレベルＣＳＰ内蔵基板の総板厚を薄くすることができる。   In the semiconductor device according to the present invention, the conductor layer is provided on the external connection electrode and the side insulating layer of the semiconductor structure. In other words, the conductor circuit is provided in the layer where the conventional wiring circuit is not provided. Therefore, as a result of reducing one or more upper wiring layers, the total thickness of the wafer level CSP built-in substrate can be reduced.

また、従来は支持体に離間して半導体構成体をおおよその位置に配置していたため、上層への再配線層を形成する際に外部接続用電極と再配線層との間にズレが生じることがあったが、本発明において、外部接続用電極上に外部接続用電極よりも大きな径で導体層を形成する態様で実施すれば、上層の再配線層とのズレを吸収することができ、接続信頼性が向上する。   In addition, since the semiconductor structure is conventionally arranged at an approximate position apart from the support, there is a gap between the external connection electrode and the rewiring layer when the rewiring layer is formed on the upper layer. However, in the present invention, if the conductor layer is formed on the external connection electrode with a diameter larger than that of the external connection electrode, the deviation from the upper rewiring layer can be absorbed. Connection reliability is improved.

図１を用いて本発明の第１の半導体装置例について説明する。   A first semiconductor device example of the present invention will be described with reference to FIG.

図１において、支持体たる配線回路１の上面には、半導体構成体２が接着剤３を介して搭載されている。ここで、配線回路１は、放熱機能を有するものが好ましい。また当該半導体構成体２は、複数の外部接続用電極４を備えていると共に、該外部接続用電極４を覆うように導体層５が形成されている。ここで、導体層５は、配線回路や接続パッドなども含まれる。当該半導体構成体２の側方には、絶縁層として多層配線基板８が配置されている。この側方に配置される多層配線基板８は、例えばコア配線基板として両面ＢＶＨ（ブラインドバイアホール）を備えた両面配線基板８ａを用い、その上下に、上下対称構造となるように絶縁層８ｂ、８ｃを重ね、更に層間接続ビア７を形成して構成される。層間接続ビア７は、貫通めっきスルーホールでも表裏の導通が得られるものであれば構わない。当該側方の絶縁層８ｂ、８ｃとしては、例えば、絶縁樹脂シート化したボンディングシートや、ガラスクロスにエポキシ樹脂を含浸させたプリプレグ、液状樹脂などの材料から成るものが挙げられ、当該材料は適宜組み合わせて使用することもできる。   In FIG. 1, a semiconductor structure 2 is mounted on an upper surface of a wiring circuit 1 as a support via an adhesive 3. Here, the wiring circuit 1 preferably has a heat dissipation function. The semiconductor structure 2 includes a plurality of external connection electrodes 4, and a conductor layer 5 is formed so as to cover the external connection electrodes 4. Here, the conductor layer 5 includes a wiring circuit, a connection pad, and the like. On the side of the semiconductor structure 2, a multilayer wiring board 8 is disposed as an insulating layer. The multilayer wiring board 8 disposed on the side uses, for example, a double-sided wiring board 8a provided with a double-sided BVH (blind via hole) as a core wiring board, and an insulating layer 8b that has a vertically symmetrical structure above and below it. 8c is overlapped and an interlayer connection via 7 is formed. The interlayer connection via 7 may be any through-plated through hole as long as it can provide conduction on the front and back sides. Examples of the side insulating layers 8b and 8c include a bonding sheet formed into an insulating resin sheet, a prepreg obtained by impregnating a glass cloth with an epoxy resin, a liquid resin, and the like. It can also be used in combination.

また、上記半導体構成体２の外部接続用電極４上と同様に、当該側方の多層配線基板８の表面にも導体層５が形成されており、当該半導体構成体２の外部接続用電極４上の導体層５は、外部接続用電極４よりやや大きい径で設けられている。   Similarly to the external connection electrode 4 of the semiconductor structure 2, the conductor layer 5 is also formed on the surface of the side multilayer wiring substrate 8, and the external connection electrode 4 of the semiconductor structure 2 is formed. The upper conductor layer 5 is provided with a diameter slightly larger than that of the external connection electrode 4.

次に、図２を用いて、更に上層及び下層に絶縁層と再配線層を形成した本発明の第２の半導体装置例について説明する。   Next, a second semiconductor device example of the present invention in which an insulating layer and a rewiring layer are further formed in the upper layer and the lower layer will be described with reference to FIG.

図２において、半導体構成体２と側方の多層配線基板８の上層には再配線を形成するための上層絶縁層９が配置されていると共に、半導体構成体２の配線回路１と側方の多層配線基板８下層には下層絶縁層１０が配置されている。当該上層及び下層絶縁層としては、ビルドアップ材を使用するのが好ましい。ビルドアップ材としては、例えばエポキシ樹脂やＢＴ樹脂の熱硬化性樹脂中に繊維やフィラー等の補強材を含有させたものなどが挙げられる。この場合、繊維としては、ガラス繊維、アラミド繊維が、また、フィラーとしては、シリカ、セラミックス系などのフィラーが好適に使用される。
また、支持体として薄い金属箔を用いた場合、半導体構成体２と側方の絶縁層の固定をより強固にするために、上層あるいは下層の絶縁層９、１０に、今まで以上に剛性を強化したシート状の絶縁層を用いるのが好ましい。斯かるシート状絶縁層としては、例えば、アラミドフィルムの上下に熱硬化性樹脂を塗布したものや、ガラスクロスに熱硬化性樹脂を含浸させたプリプレグシートなどが好適に使用される。上層及び下層絶縁層のみを積層しても良いが、樹脂付き銅箔や絶縁層に銅箔を重ねて積層しても構わない。 In FIG. 2, an upper insulating layer 9 for forming a rewiring is disposed on the upper side of the semiconductor structure 2 and the multilayer wiring board 8 on the side, and the wiring circuit 1 of the semiconductor structure 2 and the side of the side of the wiring structure 1. A lower insulating layer 10 is disposed below the multilayer wiring board 8. As the upper and lower insulating layers, it is preferable to use a buildup material. Examples of the buildup material include a material in which a reinforcing material such as a fiber or a filler is contained in a thermosetting resin such as an epoxy resin or a BT resin. In this case, glass fibers and aramid fibers are suitably used as the fibers, and silica and ceramic fillers are suitably used as the fillers.
In addition, when a thin metal foil is used as the support, the upper or lower insulating layers 9 and 10 are more rigid than ever in order to make the semiconductor structure 2 and the side insulating layers more firmly fixed. It is preferable to use a reinforced sheet-like insulating layer. As such a sheet-like insulating layer, for example, a prepreg sheet in which a thermosetting resin is applied to the upper and lower sides of an aramid film or a glass cloth impregnated with a thermosetting resin is preferably used. Only the upper layer and the lower insulating layer may be laminated, or the copper foil with resin or the copper foil may be laminated on the insulating layer.

前記上層及び下層絶縁層９、１０上には、第１の上層再配線層１１と第１の下層の再配線層１２が設けられ、上層の第１の再配線層１１上にソルダーレジスト１３からなる保護層が、また、下層の第１の再配線層１２上にソルダーレジスト１４からなる保護層がそれぞれ設けられている。ソルダーレジスト１３の開口部には、はんだボールからなる突起物１５が形成され、マトリクス状に配置されている。   A first upper redistribution layer 11 and a first lower redistribution layer 12 are provided on the upper and lower insulating layers 9 and 10, and the solder resist 13 is formed on the upper first redistribution layer 11. A protective layer made of a solder resist 14 is provided on the lower first rewiring layer 12. Projections 15 made of solder balls are formed in the openings of the solder resist 13 and arranged in a matrix.

次に、図３〜図６を用いて、本発明半導体装置の第１の製造方法例について説明する。   Next, a first manufacturing method example of the semiconductor device of the present invention will be described with reference to FIGS.

図３（ａ）：まず、支持体３１に、複数の外部接続用電極３４を有する半導体構成体３２を接着剤３３を介して複数搭載する。ここに支持体３１としては、キャリア付き銅箔やステンレスなどの金属板や絶縁基材、あるいは絶縁基材に回路形成が施された配線基板などが用いられる。半導体構成体３２はそのシリコン部分に接着剤３３を塗布した後、これを支持体３１と接合する。
図３（ｂ）：次いで、支持体３１に、半導体構成体３２に対応する部分に開口部を設けた多層配線基板３５を配置する。
図３（ｃ）：次いで、加熱加圧にて積層する。多層配線基板３５は、例えば両面銅張積層板に銅めっきを充填する方法でＢＶＨ（ブラインドバイアホール）を形成した両面配線基板３５ａに、ガラス繊維にエポキシ樹脂を含浸させたプリプレグ（絶縁層）３５ｂ、３５ｃを上下に重ね、さらにその上面に銅箔を重ね積層して製造される。また、多層配線基板３５の構成としては、銅張積層板を加工した両面配線基板などとプリプレグシートなどの組み合わせが好適に使用される。 FIG. 3A: First, a plurality of semiconductor structures 32 having a plurality of external connection electrodes 34 are mounted on a support 31 via an adhesive 33. Here, as the support 31, a metal foil such as a copper foil with a carrier or stainless steel, an insulating base, or a wiring board in which a circuit is formed on the insulating base is used. The semiconductor structure 32 is bonded to the support 31 after the adhesive 33 is applied to the silicon portion.
FIG. 3B: Next, the multilayer wiring board 35 provided with an opening in a portion corresponding to the semiconductor structure 32 is disposed on the support 31.
FIG. 3C: Next, lamination is performed by heating and pressing. The multilayer wiring board 35 is, for example, a prepreg (insulating layer) 35b in which a glass fiber is impregnated with an epoxy resin on a double-sided wiring board 35a in which BVH (blind via holes) are formed by filling a double-sided copper-clad laminate with copper plating. , 35c are stacked one above the other and copper foil is further stacked on the upper surface thereof. Moreover, as a structure of the multilayer wiring board 35, the combination of the double-sided wiring board etc. which processed the copper clad laminated board, and a prepreg sheet is used suitably.

図４（ｄ）：次いで、多層配線基板３５の絶縁層３５ｂ、３５ｃに非貫通穴３６をレーザ加工にて形成し、ウエットあるいはドライデスミア処理する。
図４（ｅ）：次いで、半導体構成体３２上を含む上下の略全面に無電解・電解金属めっき３７を施す。ここで金属めっきは、一般に安価で回路形成が施し易い銅などが好適に使用される。
図４（ｆ）：次いで、写真法にて導体層（配線回路や接続パットを含む）３８を施す。 FIG. 4D: Next, non-through holes 36 are formed in the insulating layers 35b and 35c of the multilayer wiring board 35 by laser processing, and wet or dry desmear processing is performed.
FIG. 4E: Next, electroless / electrolytic metal plating 37 is applied to substantially the entire upper and lower surfaces including the semiconductor structure 32. Here, for the metal plating, copper or the like that is generally inexpensive and easy to form a circuit is preferably used.
FIG. 4F: Next, a conductor layer (including a wiring circuit and a connection pad) 38 is applied by a photographic method.

図５（ｇ）：次いで、半導体構成体３２及び側方の多層配線基板３５の上方及び下方に上方絶縁層３９と下方絶縁層４０を配置し、加熱加圧にて積層する。ここに、上層及び下層絶縁層としては、一般にビルドアップ材といわれるエポキシ樹脂やＢＴ樹脂等の熱硬化性樹脂にガラス繊維やフィラー等の補強材を含有させたものが好適に使用される。また、支持体に薄い金属箔を用いた場合、半導体構成体と側方の絶縁層の固定をより強固にするために、上層あるいは下層の絶縁層に、今まで以上に剛性を強化したシート状の絶縁層を用いるのが好ましい。斯かるシート状絶縁層としては、例えば、アラミドフィルムの上下に熱硬化性樹脂を塗布したものや、ガラスクロスに熱硬化性樹脂を含浸させたプリプレグシートなどが好適に使用される。上層及び下層絶縁層のみを積層しても良いが、樹脂付き銅箔や絶縁層に銅箔を重ねて積層しても構わない。   FIG. 5G: Next, the upper insulating layer 39 and the lower insulating layer 40 are arranged above and below the semiconductor structure 32 and the side multilayer wiring board 35, and are laminated by heating and pressing. Here, as the upper layer and the lower layer insulating layer, those in which a reinforcing material such as glass fiber or filler is contained in a thermosetting resin such as an epoxy resin or a BT resin generally called a build-up material are preferably used. In addition, when a thin metal foil is used for the support, in order to strengthen the fixation of the semiconductor structure and the side insulating layer, the upper or lower insulating layer has a sheet shape with enhanced rigidity. It is preferable to use the insulating layer. As such a sheet-like insulating layer, for example, a prepreg sheet in which a thermosetting resin is applied to the top and bottom of an aramid film or a glass cloth impregnated with a thermosetting resin is preferably used. Only the upper layer and the lower insulating layer may be laminated, or the copper foil with resin or the copper foil may be laminated on the insulating layer.

図５（ｈ）：次いで、上層及び下層絶縁層に非貫通穴３６をレーザ加工で形成し、デスミア処理する。
図５（ｉ）：次いで、上下両面に無電解・電解金属めっき処理３７を施す。
図６（ｊ）：次いで、写真法にて上層第１再配線層４１及び下層第１再配線層４２を形成する。
図６（ｋ）：次いで、最外層の上層再配線層に上層ソルダーレジスト４３からなる保護層と、最外層の下層再配線層に下層ソルダーレジスト４４からなる保護層を形成する。
図６（ｌ）：次いで、ダイシング加工にて個片化して半導体装置４５を得る。 FIG. 5H: Next, non-through holes 36 are formed in the upper and lower insulating layers by laser processing, and desmear processing is performed.
FIG. 5I: Next, an electroless / electrolytic metal plating process 37 is performed on the upper and lower surfaces.
FIG. 6J: Next, the upper first rewiring layer 41 and the lower first rewiring layer 42 are formed by photographic method.
FIG. 6K: Next, a protective layer made of the upper layer solder resist 43 is formed on the uppermost redistribution layer of the outermost layer, and a protective layer made of the lower layer solder resist 44 is formed on the lower layer rewiring layer of the outermost layer.
FIG. 6L: Next, the semiconductor device 45 is obtained by dicing into pieces.

次に、図７〜図９を用いて、本発明半導体装置の第２の製造方法例について説明する。
図７（ａ）：まず、支持体７１に、複数の外部接続用電極７４を有する半導体構成体７２を接着剤７３を介して複数搭載する。ここに支持体７１としては、キャリア付き銅箔やステンレスなどの金属板や絶縁基材、あるいは絶縁基材に回路形成が施された配線基板などが用いられる。半導体構成体７２はそのシリコン部分に接着剤７３を塗布した後、これを支持体７１と接合する。
図７（ｂ）：次いで、支持体７１に、半導体構成体７２に対応する部分に開口部を設けた多層配線基板７５を配置する。
図７（ｃ）：次いで、加熱加圧にて積層する。多層配線基板７５は、例えば、両面銅張積層板に銅めっきを充填する方法でＢＶＨ（ブラインドバイアホール）を形成した両面配線基板７５ａに、ガラスクロスにエポキシ樹脂を含浸させたプリプレグ（絶縁層）７５ｂ、７５ｃを上下に重ねて積層して製造される。また、多層配線基板の構成としては、例えば、ガラス繊維にエポキシ樹脂を含浸させたプリプレグシートや銅張積層板を加工した両面配線基板などとプリプレグシートなどの組み合わせが好適に使用される。 Next, a second manufacturing method example of the semiconductor device of the present invention will be described with reference to FIGS.
FIG. 7A: First, a plurality of semiconductor structures 72 having a plurality of external connection electrodes 74 are mounted on the support 71 via an adhesive 73. Here, as the support 71, a metal plate such as a copper foil with a carrier or stainless steel, an insulating base, or a wiring board in which a circuit is formed on the insulating base is used. The semiconductor structure 72 is bonded to the support 71 after the adhesive 73 is applied to the silicon portion.
FIG. 7B: Next, a multilayer wiring board 75 having an opening provided in a portion corresponding to the semiconductor structure 72 is disposed on the support 71.
FIG. 7C: Next, lamination is performed by heating and pressing. The multilayer wiring board 75 is, for example, a prepreg (insulating layer) in which a glass cloth is impregnated with an epoxy resin on a double-sided wiring board 75a in which BVH (blind via hole) is formed by filling a double-sided copper-clad laminate with copper plating. It is manufactured by stacking 75b and 75c on top and bottom. Moreover, as a structure of a multilayer wiring board, the combination of a prepreg sheet | seat etc. with the prepreg sheet | seat which impregnated the epoxy resin to the glass fiber, the double-sided wiring board which processed the copper clad laminated board, etc. is used suitably, for example.

図８（ｄ）：次いで、多層配線基板７５の絶縁層７５ｂ、７５ｃに非貫通穴７６を形成する。
図８（ｅ）：次いで、半導体構成体７２と側方の多層配線基板７５の上下両面にスパッタリングで金属皮膜７７を全面に成膜させる。因に、半導体構成体７２と側方の多層配線基板７５の異なる樹脂表面に金属めっき膜を成膜するには、スパッタリング７７による成膜方法が樹脂の内部までめっき膜が食い込むため密着性がより安定しているので好ましい。
ここでスパッタリング７７の条件としては、例えば、ＤＣスパッタリング装置を用い、ターゲットには銅を用いて行い、チャンバー内に半導体装置をセットし、１０-2Ｐａ以下になるまで真空引きし、アルゴンガスなどをガス圧０．０５〜１０Ｐａの流量でチャンバー内に導入し、放電電圧２００〜５００Ｖで１〜１０分間スパッタリングを行うことで、銅皮膜１００〜５００００Åを成膜することができる。
図８（ｆ）：次いで、当該金属皮膜７７の表面に電解金属めっき７８を施す。
図９（ｇ）：次いで、導体層（配線回路及び接続パッドを含む）７９を写真法にて形成する。 FIG. 8D: Next, non-through holes 76 are formed in the insulating layers 75b and 75c of the multilayer wiring board 75.
FIG. 8E: Next, a metal film 77 is formed on the entire surface of the semiconductor structure 72 and the lateral multilayer wiring board 75 by sputtering on the entire upper and lower surfaces. Incidentally, in order to form a metal plating film on different resin surfaces of the semiconductor structure 72 and the side multilayer wiring board 75, the film formation method by sputtering 77 penetrates into the inside of the resin, so that the adhesion is further improved. It is preferable because it is stable.
Here, as the conditions for sputtering 77, for example, a DC sputtering apparatus is used, copper is used as a target, a semiconductor device is set in a chamber, vacuum is drawn to 10 −2 Pa or less, argon gas, etc. Is introduced into the chamber at a gas flow rate of 0.05 to 10 Pa, and sputtering is performed at a discharge voltage of 200 to 500 V for 1 to 10 minutes, whereby a copper film of 100 to 50000 can be formed.
FIG. 8F: Next, electrolytic metal plating 78 is applied to the surface of the metal film 77.
FIG. 9G: Next, a conductor layer (including a wiring circuit and connection pads) 79 is formed by a photographic method.

図９（ｈ）：次いで、最外層に、上層ソルダーレジスト８０と下層ソルダーレジスト８１からなる保護層を形成する。
図９（ｉ）：次いで、ダイシング加工にて個片化して半導体装置８２を得る。 FIG. 9H: Next, a protective layer composed of the upper solder resist 80 and the lower solder resist 81 is formed on the outermost layer.
FIG. 9I: Next, the semiconductor device 82 is obtained by dicing into individual pieces.

尚、図９（ｇ）の工程後、半導体構成体７２と側方の多層配線基板７５上に、絶縁層と再配線層を必要に応じて更に形成することもできる。   After the step of FIG. 9G, an insulating layer and a rewiring layer can be further formed on the semiconductor structure 72 and the side multilayer wiring board 75 as necessary.

本発明の第１の半導体装置例を示す概略断面説明図。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional explanatory view showing a first semiconductor device example of the present invention. 本発明の第２の半導体装置例を示す概略断面説明図。FIG. 6 is a schematic cross-sectional explanatory view showing a second semiconductor device example of the present invention. 本発明半導体装置の第１の製造方法例を示す概略断面工程説明図。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 図３に続く概略断面工程説明図。FIG. 4 is a schematic cross-sectional process explanatory diagram following FIG. 3. 図４に続く概略断面工程説明図。FIG. 5 is a schematic cross-sectional process explanatory diagram subsequent to FIG. 4. 図５に続く概略断面工程説明図。FIG. 6 is a schematic cross-sectional process explanatory diagram following FIG. 5. 本発明半導体装置の第２の製造方法例を示す概略断面工程説明図。FIG. 10 is a schematic cross-sectional process explanatory diagram illustrating a second example of a manufacturing method of a semiconductor device of the present invention. 図７に続く概略断面工程説明図。FIG. 8 is a schematic cross-sectional process explanatory diagram following FIG. 7. 図８に続く概略断面工程説明図。FIG. 9 is a schematic cross-sectional process explanatory diagram following FIG. 8.

符号の説明Explanation of symbols

１：配線回路
２、３２、７２：半導体構成体
３、３３、７３：接着剤
４、３４、７４：外部接続用電極
５、３８、７９：導体層（配線回路や接続パッドを含む）
７：層間接続ビア
８、３５、７５：多層配線基板
８ａ、３５ａ、７５ａ：両面配線基板
８ｂ、８ｃ、３５ｂ、３５ｃ、７５ｂ、７５ｃ：絶縁層
９、３９：上層絶縁層
１０、４０：下層絶縁層
１１、４１：上層第１再配線層
１２、４２：下層第１再配線層
１３、４３、８０：上層ソルダーレジスト
１４、４４、８１：下層ソルダーレジスト
１５：はんだからなる突起物
３１、７１：支持体
３６、７６：非貫通穴
３７：無電解・電解金属めっき
４５、８２：半導体装置
７７：金属皮膜
７８：電解金属めっき 1: Wiring circuits 2, 32, 72: Semiconductor structures 3, 33, 73: Adhesives 4, 34, 74: External connection electrodes 5, 38, 79: Conductor layers (including wiring circuits and connection pads)
7: Interlayer connection vias 8, 35, 75: Multilayer wiring boards 8a, 35a, 75a: Double-sided wiring boards 8b, 8c, 35b, 35c, 75b, 75c: Insulating layers 9, 39: Upper insulating layers 10, 40: Lower insulating layers Layers 11, 41: Upper first rewiring layer 12, 42: Lower first rewiring layer 13, 43, 80: Upper solder resist 14, 44, 81: Lower solder resist 15: Protrusions 31, 71 made of solder Supports 36, 76: Non-through hole 37: Electroless / electrolytic metal plating 45, 82: Semiconductor device 77: Metal film 78: Electrolytic metal plating

Claims (18)

上面に複数の外部接続用電極を有する半導体構成体と、前記半導体構成体を支える支持体と、前記半導体構成体の側方に設けられた絶縁層とを有し、かつ前記半導体構成体の外部接続用電極上及び前記側方に設けられた絶縁層上に導体層が設けられていることを特徴とする半導体装置。   A semiconductor structure having a plurality of electrodes for external connection on an upper surface; a support that supports the semiconductor structure; and an insulating layer provided on a side of the semiconductor structure; and the outside of the semiconductor structure A semiconductor device, wherein a conductor layer is provided on a connection electrode and an insulating layer provided on the side. 前記外部接続用電極上の導体層と前記側方に設けられた絶縁層上の導体層が接続されていることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein a conductor layer on the external connection electrode and a conductor layer on an insulating layer provided on the side are connected. 前記外部接続用電極上の導体層は、外部接続用電極よりも径が大きいことを特徴とする請求項１又は２記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the conductor layer on the external connection electrode has a larger diameter than the external connection electrode. 前記側方に設けられた絶縁層が、多層配線基板であることを特徴とする請求項１〜３の何れか１項記載の半導体装置。   The semiconductor device according to claim 1, wherein the insulating layer provided on the side is a multilayer wiring board. 前記半導体構成体を支えている支持体が、配線回路であることを特徴とする請求項１〜４の何れか１項記載の半導体装置。   The semiconductor device according to claim 1, wherein the support that supports the semiconductor structure is a wiring circuit. 前記配線回路が、放熱機能を有することを特徴とする請求項５記載の半導体装置。   The semiconductor device according to claim 5, wherein the wiring circuit has a heat dissipation function. 前記側方に設けられた絶縁層に、層間接続ビアが設けられていることを特徴とする請求項１〜６の何れか１項記載の半導体装置。   The semiconductor device according to claim 1, wherein an interlayer connection via is provided in the insulating layer provided on the side. 前記層間接続ビアが、貫通めっきスルーホールであることを特徴とする請求項７記載の半導体装置。   The semiconductor device according to claim 7, wherein the interlayer connection via is a through plating through hole. 前記外部接続用電極上に、少なくとも１層以上の絶縁層と再配線層が設けられていることを特徴とする請求項１〜８の何れか１項記載の半導体装置。   9. The semiconductor device according to claim 1, wherein at least one insulating layer and a rewiring layer are provided on the external connection electrode. 前記半導体構成体を支えている支持体の下層に、少なくとも１層以上の絶縁層と再配線層が設けられていることを特徴とする請求項１〜９の何れか１項記載の半導体装置。   The semiconductor device according to claim 1, wherein at least one insulating layer and a rewiring layer are provided in a lower layer of a support that supports the semiconductor structure. 前記外部接続用電極上の絶縁層及び／又は前記支持体の下層の絶縁層が、剛性の強いアラミドシート又はガラスクロスを含むプリプレグから成ることを特徴とする請求項９又は１０記載の半導体装置。   11. The semiconductor device according to claim 9, wherein the insulating layer on the external connection electrode and / or the insulating layer under the support is made of a prepreg including a rigid aramid sheet or glass cloth. 前記側方に設けられた絶縁層は、コア配線基板を中心に配置され、上下対称構造となっていることを特徴とする請求項１〜１０の何れか１項記載の半導体装置。   The semiconductor device according to claim 1, wherein the insulating layer provided on the side is disposed around the core wiring substrate and has a vertically symmetrical structure. 最上層及び／又は最下層の再配線層上に、ソルダーレジストが設けられていることを特徴とする請求項１〜１２の何れか１項記載の半導体装置。   13. The semiconductor device according to claim 1, wherein a solder resist is provided on the uppermost layer and / or the lowermost rewiring layer. 支持体に接着剤を介して、上面に複数の外部接続用電極を有する半導体構成体を配置する工程と、前記半導体構成体の側方に絶縁層を配置し積層する工程と、前記積層工程後、無電解・電解金属めっきを析出する工程と、前記めっき析出工程後、写真法にて配線回路を形成する工程とを有することを特徴とする半導体装置の製造方法。   A step of disposing a semiconductor structure having a plurality of electrodes for external connection on the upper surface via an adhesive on a support; a step of disposing an insulating layer on a side of the semiconductor structure; and a step of laminating; A method of manufacturing a semiconductor device, comprising: a step of depositing electroless / electrolytic metal plating; and a step of forming a wiring circuit by a photographic method after the plating deposition step. 支持体に接着剤を介して、上面に複数の外部接続用電極を有する半導体構成体を配置する工程と、前記半導体構成体の側方に絶縁層を配置し積層する工程と、前記積層工程後、スパッタリングで金属皮膜を成膜する工程と、前記成膜工程後、電解金属めっきを析出する工程と、前記めっき析出工程後、写真法にて配線回路を形成する工程とを有することを特徴とする半導体装置の製造方法。   A step of disposing a semiconductor structure having a plurality of electrodes for external connection on the upper surface via an adhesive on a support; a step of disposing an insulating layer on a side of the semiconductor structure; and a step of laminating; A step of forming a metal film by sputtering, a step of depositing electrolytic metal plating after the film formation step, and a step of forming a wiring circuit by photographic method after the plating deposition step. A method for manufacturing a semiconductor device. 更に、半導体構成体の上層に、少なくとも１層以上の絶縁層と再配線層を形成する工程を有することを特徴とする請求項１４又は１５記載の半導体装置の製造方法。   16. The method of manufacturing a semiconductor device according to claim 14, further comprising a step of forming at least one insulating layer and a rewiring layer on an upper layer of the semiconductor structure. 更に、半導体構成体を支えている支持体の下層に、少なくとも１層以上の絶縁層と再配線層を形成する工程を有することを特徴とする請求項１４〜１６の何れか１項記載の半導体装置の製造方法。   The semiconductor according to any one of claims 14 to 16, further comprising a step of forming at least one insulating layer and a rewiring layer in a lower layer of a support supporting the semiconductor structure. Device manufacturing method. 更に、最上層及び／又は最下層の再配線層上に、ソルダーレジストを形成する工程を有することを特徴とする請求項１４〜１７の何れか１項記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 14, further comprising a step of forming a solder resist on the uppermost layer and / or the lowermost rewiring layer.
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