KR102039712B1 - Fan-out semiconductor package - Google Patents

Abstract

The present disclosure includes a plurality of insulating layers, a plurality of wiring layers disposed on the plurality of insulating layers, and a plurality of connecting via layers penetrating the plurality of insulating layers and electrically connecting the plurality of wiring layers, A frame having a recess in which a stopper layer is disposed; A semiconductor chip having a connection pad, an active surface on which the connection pad is disposed, and an inactive surface opposite to the active surface, the semiconductor chip being disposed in the recess portion such that the inactive surface is connected to the stopper layer; An encapsulant covering at least a portion of the semiconductor chip and filling at least a portion of the recess portion; And a redistribution layer disposed on the frame and the active surface of the semiconductor chip, the redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pad of the semiconductor chip. And a guide pattern disposed to be adjacent to the wall surface of the recess portion, and a groove portion is formed at an edge of the bottom surface of the recess portion.

Description

Fan-Out Semiconductor Packages {FAN-OUT SEMICONDUCTOR PACKAGE}

The present disclosure relates to a semiconductor package, for example, a fan-out semiconductor package that can extend the electrical connection structure beyond the region where the semiconductor chip is disposed.

One of the main trends in the recent development of technology for semiconductor chips is to reduce the size of components, and thus, in the field of packaging, it is required to implement a large number of pins with small sizes in response to the rapid increase in demand for small semiconductor chips. .

One of the proposed semiconductor package technologies is a fan-out semiconductor package. The fan-out package reroutes the connection terminals beyond the area where the semiconductor chip is placed, enabling a small number of pins.

On the other hand, instead of implementing a separate backside redistribution layer on the inactive surface of the semiconductor chip, a semiconductor package for forming a blind-type recessed portion opened to one side only in the frame, and implements the redistribution structure in the frame portion of the other side Can be used.

One of several objects of the present disclosure is to implement a semiconductor package by introducing a frame having a blind recess, but to provide a fan-out semiconductor package that can control the profile of the wall of the blind recess.

One of several solutions proposed through the present disclosure is to control the profile of the wall surface of the recess through the guide pattern formed inside the frame.

For example, a fan-out semiconductor package according to an example may include a plurality of insulating layers, a plurality of wiring layers disposed on the plurality of insulating layers, and a plurality of wiring layers that electrically pass through the plurality of insulating layers and electrically connect the plurality of wiring layers. A frame including a connection via layer, the frame having a recess on which a stopper layer is disposed; A semiconductor chip having a connection pad, an active surface on which the connection pad is disposed, and an inactive surface opposite to the active surface, the semiconductor chip being disposed in the recess portion such that the inactive surface is connected to the stopper layer; An encapsulant covering at least a portion of the semiconductor chip and filling at least a portion of the recess portion; And a redistribution layer disposed on the frame and the active surface of the semiconductor chip, the redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pad of the semiconductor chip. It includes, and the guide pattern disposed to be adjacent to the wall surface of the recess portion is disposed in the inside of the frame, a groove portion may be formed in the corner of the bottom surface of the recess portion.

As one of various effects of the present disclosure, a semiconductor package may be implemented by introducing a frame having a blind recess, and a fan-out semiconductor package capable of controlling a profile of a wall surface of the blind recess may be provided.

1 is a block diagram schematically illustrating an example of an electronic device system.
2 is a perspective view schematically showing an example of an electronic device.
3 is a cross-sectional view schematically showing before and after packaging of a fan-in semiconductor package.
4 is a cross-sectional view schematically illustrating a packaging process of a fan-in semiconductor package.
5 is a cross-sectional view schematically illustrating a case where a fan-in semiconductor package is mounted on a BGA substrate and finally mounted on a main board of an electronic device.
6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in a BGA substrate and finally mounted on a main board of an electronic device.
7 is a cross-sectional view illustrating a schematic view of a fan-out semiconductor package.
8 is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a main board of an electronic device.
9 is a schematic cross-sectional view of a fan-out semiconductor package according to an example.
10A and 10B are schematic plan views of the fan-out semiconductor package of FIG. 9, taken along line II ′ and II-II ′, respectively.
11A and 11B are plan views schematically illustrating other examples of guide patterns employable in the fan-out semiconductor package of FIG. 9.
12A through 12E are schematic cross-sectional views illustrating a process of forming a frame of the fan-out semiconductor package of FIG. 9.
13A to 13E are schematic cross-sectional views illustrating a manufacturing process of the fan-out semiconductor package of FIG. 9.
14 is a schematic cross-sectional view of a fan-out semiconductor package according to another example.
15A to 15D are schematic cross-sectional views illustrating a process of forming a frame of the fan-out semiconductor package of FIG. 14.
16 is a schematic cross-sectional view of a fan-out semiconductor package according to another example.
17A to 17D are schematic cross-sectional views illustrating a process of forming a frame of the fan-out semiconductor package of FIG. 16.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. Shape and size of the elements in the drawings may be exaggerated or reduced for more clear description.

Electronics

1 is a block diagram schematically illustrating an example of an electronic device system.

Referring to the drawings, the electronic apparatus 1000 accommodates the main board 1010. The chip-related component 1020, the network-related component 1030, and the other component 1040 are physically and / or electrically connected to the main board 1010. These are also combined with other components described below to form various signal lines 1090.

The chip related component 1020 may include a memory chip such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as central processors (eg, CPUs), graphics processors (eg, GPUs), digital signal processors, cryptographic processors, microprocessors, microcontrollers; Logic chips such as analog-to-digital converters and application-specific ICs (ASICs) may be included, but are not limited thereto. In addition, other types of chip-related components may be included. Of course, these components 1020 may be combined with each other.

Network-related components 1030 include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM And any other wireless and wired protocols designated as GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond. Any of the standards or protocols may be included. In addition, of course, the network related component 1030 may be combined with the chip related component 1020.

Other components 1040 include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electro magnetic interference (EMI) filters, multi-layer ceramic condenser (MLCC), and the like. However, the present invention is not limited thereto, and may include passive components used for various other purposes. In addition, other components 1040 may be combined with each other, along with chip-related component 1020 and / or network-related component 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other components include camera 1050, antenna 1060, display 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown), compass ( Not shown), accelerometer (not shown), gyroscope (not shown), speakers (not shown), mass storage (e.g., hard disk drive) (not shown), compact disk (not shown), and DVD (digital versatile disk) (not shown) and the like, but is not limited thereto. In addition, other components used for various purposes may be included according to the type of the electronic device 1000.

The electronic device 1000 may include a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer ( computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, and the like. However, the present invention is not limited thereto, and may be any other electronic device that processes data.

2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, the semiconductor package is applied to various electronic devices as described above for various uses. For example, a motherboard 1110 is accommodated in the body 1101 of the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components, such as camera 1130, may or may not be physically and / or electrically connected to mainboard 1010. Some of the components 1120 may be chip related components, and the semiconductor package 100 may be, for example, an application processor, but is not limited thereto. The electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

Semiconductor package

Generally, a semiconductor chip is integrated with a large number of fine electric circuits, but it cannot function as a finished semiconductor by itself, and there is a possibility of being damaged by an external physical or chemical impact. Therefore, instead of using the semiconductor chip itself, the semiconductor chip is packaged and used for electronic devices in a packaged state.

The need for semiconductor packaging is due to the difference in circuit width between the semiconductor chip and the mainboard of the electronics, in terms of electrical connections. Specifically, in the case of a semiconductor chip, the size of the connection pad and the distance between the connection pads are very small, whereas in the case of a main board used in electronic equipment, the size of the component mounting pad and the spacing of the component mounting pads are much larger than the scale of the semiconductor chip. . Therefore, it is difficult to directly mount a semiconductor chip on such a main board and a packaging technology that can buffer a difference in circuit width between each other is required.

The semiconductor package manufactured by the packaging technology may be classified into a fan-in semiconductor package and a fan-out semiconductor package according to structure and use.

Hereinafter, a fan-in semiconductor package and a fan-out semiconductor package will be described in more detail with reference to the accompanying drawings.

(Fan-in Semiconductor Package)

3 is a cross-sectional view schematically showing before and after packaging of a fan-in semiconductor package.

4 is a cross-sectional view schematically illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawing, the semiconductor chip 2220 may include a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), and the like, such as aluminum (Al) formed on one surface of the body 2221. For example, including a connection pad 2222 including a conductive material, and a passivation film 2223 formed on one surface of the body 2221 and covering at least a portion of the connection pad 2222, such as an oxide film or a nitride film. It may be an integrated circuit (IC) in a bare state. At this time, since the connection pad 2222 is very small, the integrated circuit IC may be hardly mounted on a middle level printed circuit board (PCB) as well as a main board of an electronic device.

Accordingly, in order to redistribute the connection pads 2222, the connection members 2240 are formed on the semiconductor chips 2220 in accordance with the size of the semiconductor chips 2220. The connection member 2240 forms an insulating layer 2241 on the semiconductor chip 2220 with an insulating material such as a photosensitive insulating resin (PID), and forms a via hole 2243 for opening the connection pad 2222. The wiring pattern 2242 and the vias 2243 may be formed and formed. Thereafter, a passivation layer 2250 is formed to protect the connecting member 2240, an opening 2251 is formed, and an under bump metal layer 2260 is formed. That is, through a series of processes, for example, the fan-in semiconductor package 2200 including the semiconductor chip 2220, the connection member 2240, the passivation layer 2250, and the under bump metal layer 2260 is manufactured. do.

As described above, the fan-in semiconductor package is a package in which all connection pads of the semiconductor chip, for example, I / O (Input / Output) terminals are arranged inside the device, and the fan-in semiconductor package has good electrical characteristics and can be produced at low cost. have. Therefore, many devices in a smart phone are manufactured in the form of a fan-in semiconductor package, and in particular, developments have been made to realize a small and fast signal transmission.

However, in the fan-in semiconductor package, all the I / O terminals must be disposed inside the semiconductor chip. Therefore, such a structure is difficult to apply to a semiconductor chip having a large number of I / O terminals or a small semiconductor chip. In addition, due to this vulnerability, a fan-in semiconductor package cannot be directly mounted and used on the main board of the electronic device. Even if the size and spacing of the I / O terminals of the semiconductor chip are enlarged by the rewiring process, they do not have the size and spacing enough to be directly mounted on the main board of the electronic device.

5 is a cross-sectional view schematically illustrating a case where a fan-in semiconductor package is mounted on a BGA substrate and finally mounted on a main board of an electronic device.

6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in a BGA substrate and finally mounted on a main board of an electronic device.

Referring to the drawing, in the fan-in semiconductor package 2200, the connection pads 2222, that is, the I / O terminals of the semiconductor chip 2220 are redistributed once again through the BGA substrate 2301. The fan-in semiconductor package 2200 may be mounted on the BGA substrate 2301 on the main board 2500 of the electronic device. In this case, the ball-like low melting point metal 2270 may be fixed with the underfill resin 2280, etc., and the outside may be covered with the suture 2290. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate BGA substrate 2302, and the connection pads 2222 of the semiconductor chip 2220 may be embedded by the BGA substrate 2302 in the embedded state. ), Ie, the I / O terminals may be redistributed once again and finally mounted on the motherboard 2500 of the electronic device.

As such, since the fan-in semiconductor package is difficult to be mounted directly on the main board of the electronic device, the fan-in semiconductor package is mounted on a separate BGA board and then again packaged and mounted on the main board of the electronic device or in the BGA board. It is mounted on the mainboard of the electronic device while being used.

(Fan-Out Semiconductor Package)

7 is a cross-sectional view illustrating a schematic view of a fan-out semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 2100, for example, the outside of the semiconductor chip 2120 is protected by the encapsulant 2130, and the connection pad 2122 of the semiconductor chip 2120 is connected to the connection member. By 2140, the semiconductor chip 2120 is rearranged to the outside of the semiconductor chip 2120. In this case, a passivation layer 2202 may be further formed on the connection member 2140, and an under bump metal layer 2160 may be further formed in the opening of the passivation layer 2202. A low melting point metal 2170 may be further formed on the under bump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation layer (not shown), and the like. The connection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2241, and a via 2143 for electrically connecting the connection pad 2122 and the redistribution layer 2142. Can be.

In the manufacturing process, after forming the encapsulant 2130 on the outside of the semiconductor chip 2120, the connection member 2140 may be formed. In this case, since the connecting member 2140 is processed from a via and a redistribution layer connecting to the connection pad 2122 of the semiconductor chip 2120, the via 2143 is formed to have a smaller width as it is closer to the semiconductor chip. Can be.

As described above, the fan-out semiconductor package is a form in which I / O terminals are rearranged to the outside of the semiconductor chip through a connection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all the I / O terminals of the semiconductor chip must be disposed inside the semiconductor chip, and as the device size becomes smaller, the ball size and pitch must be reduced, so that a standardized ball layout cannot be used. On the other hand, the fan-out semiconductor package is a type in which I / O terminals are rearranged to the outside of the semiconductor chip through a connection member formed on the semiconductor chip. Can be used as it is, as described below can be mounted on the main board of the electronic device without a separate BGA substrate.

8 is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a main board of an electronic device.

Referring to the drawings, the fan-out semiconductor package 2100 may be mounted on the main board 2500 of the electronic device through the low melting point metal 2170. That is, as described above, the fan-out semiconductor package 2100 may connect the connection pads 2122 on the semiconductor chip 2120 to a fan-out area beyond the size of the semiconductor chip 2120. Since 2140 is formed, a standardized ball layout may be used as it is, and as a result, it may be mounted on the main board 2500 of the electronic device without a separate BGA substrate.

As such, since the fan-out semiconductor package can be mounted on the main board of the electronic device without a separate BGA substrate, the fan-out semiconductor package can be made thinner and thinner than the fan-in semiconductor package using the BGA substrate. Its excellent thermal and electrical properties make it particularly suitable for mobile products. In addition, it is possible to implement a more compact than a general package on package (POP) type using a printed circuit board (PCB), it is possible to solve the problem caused by the warpage phenomenon.

Meanwhile, the fan-out semiconductor package refers to a package technology for mounting a semiconductor chip on a main board of an electronic device and the like, and protecting the semiconductor chip from external shocks. The concept is different from printed circuit boards (PCBs) such as BGA substrates in which fan-in semiconductor packages are embedded.

Hereinafter, a fan-out semiconductor package having a guide pattern capable of adjusting a profile of a recess wall, will be described in detail with reference to the accompanying drawings.

9 is a schematic cross-sectional view of a fan-out semiconductor package according to an example.

10A and 10B are schematic plan views of the fan-out semiconductor package of FIG. 9, taken along line II ′ and II-II ′, respectively.

Referring to FIG. 9, a fan-out semiconductor package 100 according to an example may include a first surface 110A having a recess 110H and a second surface 110B opposite to the first surface 110A. ) And a frame 110, a stopper layer BL disposed on the bottom surface of the recess 110H, a semiconductor chip 120 disposed on the stopper layer BL, and the recessed portion. And an encapsulant 130 filling at least a portion of the 110H and covering the semiconductor chip 120.

The semiconductor chip 120 has an active surface on which the connection pad 120P is disposed and an inactive surface opposite to the active surface, and the inactive surface of the semiconductor chip 120 has the stopper layer BL and the adhesive member ( 125). For example, the adhesive member 125 may be a known adhesive means such as a die attach film (DAF).

The frame 110 employed in the present exemplary embodiment includes a first insulating layer 111a corresponding to a core layer, and second and third insulating layers 111b and 111c disposed on both surfaces of the first insulating layer 111a. And a wiring structure 115 connecting the first surface 110A and the second surface 110B. The wiring structure 115 includes a connection via layer 113 and a wiring layer 112 electrically connected to the connection via layer 113.

The fan-out semiconductor package 100 according to the present exemplary embodiment further includes a connection member 140 disposed on the first surface 110A of the frame 110. The connection member 140 may include redistribution structures 142 and 143 connected to the wiring structure 115 and the connection pad 120P. The redistribution layer includes a connection via 143 and a redistribution layer 142 electrically connected to the connection via 143. The metal bumps 120B are formed on the connection pads 120P of the semiconductor chip 120, and the connection vias of the connection pads 120P and the redistribution layer are formed by the metal bumps 120B exposed on the surface of the encapsulant 130. 143 may be connected to each other.

The fan-out semiconductor package 100 according to the present exemplary embodiment may include a first passivation layer 171 disposed on the connection member 140 and a second passivation layer disposed on the second surface of the frame 110. 172). The first passivation layer 171 has an opening that exposes a portion of the redistribution layer 142. An under bump metal layer 160 is disposed on an opening of the first passivation layer 171 to be connected to a partial region of the redistribution layer 142. An electrical connection structure 170 is disposed on the under bump metal layer 160 to be electrically connected to the redistribution layer 142 through the under bump metal layer 160.

The recessed portion 110H employed in the present embodiment is opened at the first surface 110A of the frame 110 and is formed in a blind recess portion blocked at the second surface 110B of the frame 110. Has

The recess 110H may be formed by selectively applying an etching process such as a sand blast to the first surface 110A of the frame 110. In this process, the stopper layer BL may be used to etch to a predetermined position. The stopper layer BL may define a bottom surface of the recess 110H. The stopper layer BL may be formed of a material having a lower etch rate than the insulating layers of the frame 110. For example, the stopper layer BL may include a metal such as copper (Cu). In the present exemplary embodiment, the stopper layer BL may be a metal pattern formed together with the wiring layer (ie, the second wiring pattern 112b) of the wiring structure 115 positioned at the same level.

In another example, the stopper layer BL is not limited to a metal and may include an insulating material. For example, the stopper layer BL may be a photosensitive polymer such as a dry film photoresist (DFR).

The fan-out semiconductor package 100 according to the present exemplary embodiment includes a guide pattern BP disposed in the frame 110 along an edge of a bottom surface of the recess 110H. The guide pattern BP may be used as an etch barrier structure for forming a recess along with the above-described stopper layer BL.

The guide pattern BP employed in the present embodiment may be used to adjust the profile of the tapered wall surface S of the recess 110H, in particular the inclination angle θ. The width Wf of the inclined region based on the vertical line of the upper end of the recess 110H may be defined by the inclination angle θ of the recess portion wall surface S. FIG. In the inclined area, when the width Wf becomes large, a larger area must be etched in the upper area of the recess 110H in order to secure a desired seating space (that is, the bottom surface area of the recess 110H). . Therefore, there is a problem that the area for forming the wiring structure 115 of the frame 110 becomes narrow around the upper area of the recess 110H.

In this manner, the width Wf of the inclined region of the recess portion wall surface S is not only designed for the freedom of the wiring structure 115 around the upper region of the recess portion 110H, but also for the semiconductor chip 120. The mounting failure rate can be determined.

However, in general, in the process of forming the recess 110H by an etching process such as sand blast, the inclination of the wall surface S is abrupt at the beginning, and when the etching depth approaches the stopper layer BL, the workability is drastically dropped. The lower slope of the secondary wall (S) has a gentle slope. In this case, the seating space (that is, the bottom surface area of the recess portion) may be narrowed, which may cause serious defects in which the semiconductor chip 120 is inclined.

In the present exemplary embodiment, the guide pattern BP is positioned at the same level as the stopper layer BL, but is disposed to be spaced apart from the stopper layer BL, and the spaced area is along the edge of the bottom surface of the recess 110H. Located. In the spaced area, the insulating layer area of the frame 110 may be exposed. Therefore, the groove G may be formed in the exposed insulating layer.

In the process of forming the recess, the machinability becomes higher in the spaced area located along the edge than in the region where the stopper layer BL is located, and as a result, the inclination angle is lowered to a level similar to that of the upper part of the wall of the recess part S. I can keep it.

The stopper layer BL and the guide pattern BP may be positioned at the same level as the second wiring layer 112b. In detail, the second wiring layer includes the stopper layer BL and the guide pattern BP on the surface between the first and third insulating layers 111a and 111c, that is, on the surface where the second wiring layer of the first insulating layer 111a is located. It may be formed together with (112b).

The stopper layer BL and the guide pattern BP may be formed of the same material. For example, the stopper layer BL and the guide pattern BP may include a metal such as copper (Cu). In the present exemplary embodiment, the stopper layer BL and the guide pattern BP may be a metal pattern formed in the same process together with the second wiring pattern 112b.

The guide pattern BG may be configured not to be directly connected to the second wiring layer 112b, but is not limited thereto. For example, the guide pattern BP may be connected to ground, or may be partially connected to the stopper layer BL (see FIG. 11B).

FIG. 10B is a cross-sectional view taken along the line II-II 'of the semiconductor package 100, showing the bottom surface of the recess and its surrounding area.

Referring to FIG. 10B, the above-described stopper layer BL is disposed in the center area of the bottom surface of the recess, and the guide pattern BP is formed along the edge CL of the bottom surface of the recess 110. It can be placed inside.

The outer boundary of the spaced area where the machinability becomes higher may be defined by the guide pattern BP. Substantially, the edge CL of the bottom surface of the recess 110H may be determined by the guide pattern BP. 9 and 10B, the frame 110 may have a groove G formed along an edge CL of the bottom surface of the recess 110H. The groove G may be located in a spaced apart region between the stopper layer BL and the guide pattern BP as an overetched portion. The groove G may have a ring shape forming a closed loop along an edge of the bottom surface of the recess 110H, but is not limited thereto.

As in the present embodiment, the guide pattern BP may be positioned inside the frame so as to be adjacent to the corner but not exposed to the outside, but is not limited thereto. In another embodiment, a portion of the guide pattern BP may be exposed at the edge of the bottom surface of the recess 110H. This may be determined according to the etching degree for forming the recess 110H.

As such, the bottom surface size of the recess 110H and / or the length Wf of the inclined region may be adjusted by the width of the region spaced apart from the position of the guide pattern BP. Specifically, by setting the position of the guide pattern BP so as to substantially correspond to the open area of the mask (250 in FIG. 12D) when forming the recessed part 110H, the inclination angle θ is substantially secured by sufficiently securing the spaced area. It is possible to obtain a recess wall profile that is vertical and has a very short length Wf.

Hereinafter, each configuration included in the fan-out semiconductor package 100 according to the present embodiment will be described in more detail.

The frame 110 may reinforce the rigidity of the semiconductor package 100 according to a specific material and may serve to assist the thickness uniformity of the encapsulant 130. The frame 110 has a wiring structure 115 including first to fourth wiring layers 112a, 112b, 112c and 112d and first to third connection via layers 113a, 113b and 113c. The frame 110 includes a third wiring layer 112c disposed on an inactive surface of the semiconductor chip 120, and takes the blind type recessed portion 110H without the process of forming a separate backside redistribution layer. It may serve as a backside redistribution layer for 120.

The frame 110 penetrates through the first insulating layer 111a, the first and second wiring layers 112a and 112b disposed on both surfaces of the first insulating layer 111a, and the first insulating layer 111a. And a first connection via layer 113a connecting the first and second wiring layers 112a and 112b. In addition, the frame 110 is disposed on one surface of the first insulating layer 111a to cover the first wiring layer 112a and the other surface of the first insulating layer 111a. The third insulating layer 111c covering the second wiring layer 112b, the third wiring layer 112c disposed on the second insulating layer 111b, and the fourth wiring layer disposed on the third insulating layer 111c ( 112d and a second connection via layer 113b and a third insulating layer 111c that pass through the second insulating layer 111b and electrically connect the first and third wiring layers 112a and 112c. And a third connection via layer 113c electrically connecting the second and fourth wiring layers 112b and 112d.

In the present exemplary embodiment, the recess 110H penetrates through the first and second insulating layers 111a and 111b, and the third insulating layer 111c is not penetrated by the stopper layer BL. The first and second insulating layers 111a and 111b provide a wall surface of the recess 110H, and the stopper layer BL is formed together with the guide pattern BP and the second wiring layer 112b. On the second same level on 111c).

The first to third insulating layers 111a, 111b, and 111c may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide. In a particular example, the first to third insulating layers 111a, 111b, and 111c may be mixed with an inorganic filler or may be a resin, for example, prepreg impregnated with glass fiber or the like together with the inorganic filler. , Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT) and the like can be used. If a rigid material such as prepreg containing glass fiber or the like is used, the frame 110 may be used as a support member for warpage control of the semiconductor package 100.

The first insulating layer 111a may have a thickness greater than the thicknesses of the second and third insulating layers 111b and 111c. The first insulating layer 111a may be relatively thick in order to maintain rigidity, and a larger number of wiring layers 112c and 112d may be formed by introducing the second insulating layer 111b and the third insulating layer 111c. Can be formed. That is, the first insulating layer 111a functions as a core insulating layer, and the second and third insulating layers 111b and 111c each function as a buildup insulating layer for building up in different directions. The second and third insulating layers 111b and 111c may include an insulating material different from the first insulating layer 111a. For example, the first insulating layer 111a may be, for example, a prepreg in which the insulating resin is impregnated with glass fiber together with the inorganic filler, and the second and third insulating layers 111b and 111c may be the inorganic filler and the insulating material. It may be an ABF film or a PID film including a resin, but is not limited thereto. The first connection via layer 113a penetrating the first insulating layer 111a may have a diameter larger than the diameters of the second and third connection via layers 113b and 113c.

The first to fourth wiring layers 112a, 112b, 112c, and 112d may redistribute the connection pads 120P of the semiconductor chip 120 together with the redistribution layers 142 and 143 of the connection member. For example, the first to fourth wiring layers 112a, 112b, 112c, and 112d may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), It may include a conductive material such as lead (Pb), titanium (Ti), or an alloy thereof. The first to fourth wiring layers 112a, 112b, 112c, and 112d may perform various functions according to the design design of the corresponding layer. For example, the first to fourth wiring layers 112a, 112b, 112c, and 112d may include a ground (GrouND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, and the like. Here, the signal S pattern includes various signals except for a ground GND pattern, a power PWR pattern, and the like, for example, a data signal.

The thicknesses of the first to fourth wiring layers 112a, 112b, 112c, and 112d may be greater than the thickness of the redistribution layer 142 of the connection member 140. Since the wiring structure 115 of the frame 110 is formed by a substrate process, the wiring structure 115 is formed in a relatively large size, and the redistribution layers 142 and 143 of the connection member 140 may be formed in a semiconductor process and thus may be formed in a relatively small size. Can be.

The first to third connection via layers 113a, 113b, and 113c electrically connect the first to fourth wiring layers 112a, 112b, 112c, and 112d formed on different layers to provide an electrical path in the frame 110. do. The first to third connection via layers 113a, 113b, and 113c may be formed of a conductive material. The first connecting via layer 113a may have a cylindrical cross-sectional shape or an hourglass cross-sectional shape, and the second and third connecting via layers 113b and 113c may be in opposite directions with respect to the first insulating layer 111a. It may have a tapered cross-sectional shape.

Each of the semiconductor chips 120 may be an integrated circuit (IC) in which hundreds to millions or more of devices are integrated in one chip. The semiconductor chip 120 may be, for example, a central processor (eg, a CPU), a graphics processor (eg, a GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or the like. The processor chip may be an application processor (AP), but is not limited thereto. The memory chip may be a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), a flash memory, and the like, but is not limited thereto.

The semiconductor chip 120 may be formed based on an active wafer, and as a base material of the body, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used. Various circuits may be formed in the body. The connection pad 120P is for electrically connecting the semiconductor chip 120 to other components, and a conductive material such as aluminum (Al) may be used as a forming material. The passivation film exposing the connection pad 120P may be formed on the body, and the passivation film may be an oxide film, a nitride film, or the like, or a double layer of the oxide film and the nitride film. An insulating film or the like may be further disposed at other necessary positions. Each of the semiconductor chips 120 may be a bare die, but if necessary, a redistribution layer may be formed on the active surface.

The semiconductor chips 120 may include metal bumps 120B disposed on the connection pads 120P and connected thereto, respectively. The metal bumps 120B may be made of metal such as copper (Cu), or may be low melting point metal such as Sn-Au-Cu. The encapsulant 130 employed in the present exemplary embodiment may have a surface having a top surface substantially flat with the top surface of the third wiring layer 112c of the frame 110 and the top surface of the metal bump 120B of the semiconductor chip 120. (See FIG. 13B). In some cases, the upper surface of the second connecting via layer 113b of the frame 110 is exposed as a result of the grinding, so that the encapsulant 130 is formed on the upper surface of the metal bump 120B and the upper surface of the second connecting via layer 113b. It may have a surface with a substantially flat top surface. The encapsulant 130 may be formed to protect the frame 110 and the semiconductor chip 120. The sealing form is not particularly limited, and may be any form of packaging the frame 110 and the semiconductor chip 120. For example, the encapsulant 130 may cover the first surface 110A of the frame 110 and the active surface of the semiconductor chip 120, and the wall surface S of the recess 110H and the semiconductor chip ( 120 may fill the space between the sides. The encapsulant 130 may fill the recess 110H, thereby reducing the buckling while serving as an adhesive according to a specific material.

The encapsulant 130 may include an insulating material and may include, for example, a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide. In a particular example, the encapsulant 130 may be mixed with an inorganic filler or may include a resin impregnated with glass fibers with the inorganic filler. For example, the encapsulant 130 may be prepreg, ABF, FR-4, BT and the like. If necessary, the encapsulant 130 may include a photo identifiable insulating (PIE) resin.

The connection member 140 may redistribute the connection pads 120P of the semiconductor chip 120, and the first to fourth wiring layers 112a, 112b, 112c, and 112d of the frame 110 may be replaced by the semiconductor chip 120. Can be electrically connected to the connection pad 120P. Connection pads 120P of several tens of millions of semiconductor chips 120 having various functions may be redistributed through the connection member 140, and may be physically and / or externally connected to the function through the electrical connection structure 170. Can be electrically connected. The connection member 140 may include an insulating layer 141 disposed on the active surface of the frame 110 and the semiconductor chip 120, a redistribution layer 142 disposed on the insulating layer 141, and the insulating layer. The connection via 120 includes a connection via 143 connecting the connection pad 120P and the third wiring layer 112c to the adjacent redistribution layer 142 or connecting the redistribution layer 142 of another layer.

The insulating layer 141 may use a photosensitive insulating material such as PID resin in addition to the above-described insulating material. When the insulating layer 141 has a photosensitive property, the insulating layer 141 may be formed thinner, and the fine pitch of the connection via 143 may be more easily achieved. The insulating layer 141 may be a photosensitive insulating layer including an insulating resin and an inorganic filler, respectively. When the insulating layer 141 is a multilayer, these materials may be identical to each other, and may be different from each other as necessary. If the insulating layers 141 are multilayer, they may be integrated according to the process so that the boundaries themselves may be unclear.

The redistribution layer 142 of the connection member 140 may serve to substantially redistribute the connection pads 120P. For example, the redistribution layer 142 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), Or conductive materials such as alloys thereof. The redistribution layers 142 and 143 may perform various functions according to the design design of the corresponding layer, and may include, for example, a ground (GND) pattern, a power (PWR) pattern, a signal pattern, and the like.

The connection via 143 electrically connects the redistribution layer 142, the connection pad 120P, and the third wiring layer 112c formed on different layers, thereby forming an electrical path in the semiconductor package 100.

The first and second passivation layers 171 and 172 may protect the connecting member 140 and the frame 110 from external physical and chemical damage. The first passivation layer 171 may have an opening that exposes at least a portion of the redistribution layer 142 of the connection member 140. The second passivation layer 172 may have an opening that exposes at least a portion of the fourth wiring layer 112d of the frame 110. These openings may be formed in the first and second passivation layer (171, 172) of several tens to millions of. Solder resists may be used for the first and second passivation layers 171 and 172 as well as the above-described insulating material.

The under bump metal layer 160 improves the connection reliability of the electrical connection structure 170, and as a result, improves the board level reliability of the semiconductor package 100. The under bump metal layer 160 is connected to the redistribution layer 142 of the connection member 140 exposed through the opening of the first passivation layer 171. The under bump metal layer 160 may be formed in the opening of the first passivation layer 171 by a known metallization method using a known conductive material, that is, a metal, but is not limited thereto.

The electrical connection structure 170 physically and / or electrically connects the fan-out semiconductor package 100 to the outside. For example, the fan-out semiconductor package 100 may be mounted on the main board of the electronic device through the electrical connection structure 170. The electrical connection structure 170 may be formed of a conductive material, for example, a low melting point metal such as Sn-Al-Cu alloy, but this is only an example and the material is not particularly limited thereto. The electrical connection structure 170 may be a land, a ball, a pin, or the like. The electrical connection structure 170 may be formed of multiple layers or a single layer.

The number, spacing, arrangement, etc. of the electrical connection structure 170 is not particularly limited, and can be sufficiently modified according to design matters by those skilled in the art. For example, the number of the electrical connection structure 170 may be several tens to thousands, depending on the number of connection pads 120P, may have a number more or less. When the electrical connection structure 170 is a low melting point metal body, the electrical connection structure 170 may cover the side surface formed extending on one surface of the first passivation layer 171 of the under bump metal layer 160, and the connection reliability is high. It can be better.

At least one of the electrical connection structures 170 is disposed in the fan-out area. The fan-out area refers to an area outside the area where the semiconductor chip 120 is disposed. Fan-out semiconductor packages are more reliable than fan-in semiconductor packages, enable multiple I / O terminals, and facilitate 3D interconnection. In addition, compared to a ball grid array (BGA) package and a land grid array (LGA) package, the package thickness can be manufactured thinner, and the price is excellent.

Although not shown, a metal film may be formed on the wall surface S of the recess 110H as necessary for heat radiation and / or electromagnetic shielding. In addition, if necessary, a plurality of semiconductor chips 120 that perform the same or different functions may be disposed in the recess 110H. In addition, a separate passive component such as an inductor or a capacitor may be disposed in the recess 110H. For example, a surface mount (SMT) type component such as an inductor or a capacitor may be disposed on the surfaces of the first and second passivation layers 171 and 172.

The stopper layer BL employed in the present embodiment may be used as a heat dissipation means for dissipating heat generated from the semiconductor chip 120. If necessary, the stopper layer BL may be connected to ground and used as an EMI shielding means.

The guide pattern BP employed in the present embodiment is illustrated in a monolithic form as shown in FIG. 10B, but is not limited thereto. For example, the guide pattern BP may be formed in a plurality of patterns. For example, as illustrated in FIG. 11A, four patterns BP1, BP2, BP3, and BP4 disposed at each corner of the recess 110H having a rectangular cross section may be formed. Since some corners are formed along the edge CL of the bottom surface of the recess, similar effects to the guide pattern BP shown in FIG. 10B may be expected.

The guide pattern BP illustrated in FIG. 10B is illustrated as being completely separated from the stopper layer BL, that is, physically spaced apart from one another, but is not limited thereto. For example, the guide pattern BP may be partially connected to the stopper layer BL. For example, as illustrated in FIG. 11B, the guide pattern BP formed along the edge CL of the bottom surface of the recess may be connected to the stopper layer at each corner. Except for some corners, the guide pattern BP and the stopper layer BL provide areas spaced apart from each other, and thus, the groove G is formed along the edge CL of the bottom of the recess part, and thus the recess part wall surface S is formed. The lower profile can be effectively controlled. At this time, the groove (G) may be in the form of a plurality of grooves each formed along the edge of the bottom surface.

12A through 12E are schematic cross-sectional views illustrating a process of forming a frame of the fan-out semiconductor package of FIG. 9.

First, referring to FIG. 12A, a first insulating layer 111a is prepared, and first and second wiring layers 112a and 112b and a first connection via layer 113a are formed on the first insulating layer 111a. The stopper layer BL and the guide pattern BP are formed on the surface on which the second wiring layer 112b is disposed. The first insulating layer 111a may be, for example, a copper clad laminate (CCL). The hole for the first connecting via layer 113a may be formed using a mechanical drill and / or a laser drill. The first and second wiring layers 112a and 112b and the first connection via layer 113a may be formed using a known plating process. A stopper layer BL and a guide pattern BP are formed on a surface of the first insulating layer on which the second wiring layer is located. In the subsequent recess portion forming process, the stopper layer BL is used as an etch barrier that defines the depth of the recess portion formation, and the guide pattern BP is spaced apart from the stopper layer BL to define the outline of the bottom surface of the recess portion. It plays a role. The spaced area GS serves to adjust the profile of the bottom of the wall of the recess part by inducing an overetch in the latter part of the etching. The stopper layer BL and the guide pattern BP may be formed of the same material. For example, the stopper layer BL and the guide pattern BP may include a metal such as copper (Cu). In the present exemplary embodiment, the stopper layer BL and the guide pattern BP may be a metal pattern formed in the same process together with the second wiring pattern 112b.

12B, second and third insulating layers 111b and 111c and a desired wiring structure 115 are formed on both surfaces of the first insulating layer 111a. In this process, the second and third insulating layers 111b and 111c may be formed by laminating and curing an insulating film such as ABF. The third and fourth wiring layers 112c and 112d and the second and third connection via layers 113a and 113b may be formed on the second and third insulating layers 111b and 111c by using plating processes, respectively. Holes for the second and third connection via layers 113b and 113c may also be formed using a mechanical drill and / or a laser drill, similarly to the holes for the first connection via layer 113a.

Next, referring to FIG. 12C, the second passivation layer 172 is formed on the second surface 110B of the frame 110 provided in the above-described process, and the carrier film 200 is attached. The second passivation layer 172 may be a solder resist in addition to the various insulating materials described above. The carrier film 200 is disposed on the second surface 110B on which the second passivation layer 172 is formed, and may be used as a support for handling the frame 110 in a subsequent process such as forming a recess. The carrier film 200 employed in the present embodiment may be a copper foil laminate such as a DCF including an insulating layer 201 and a metal layer 202.

Next, referring to FIG. 12D, a mask layer 250 having an open area is formed on the first surface 110A of the frame 110, and an etching process for forming a recess is performed. By forming and patterning the dry film photoresist DFR on the first surface 110A of the frame 110, a mask layer 250 having an open area defining a recess is formed. The recess 110H penetrating the first and second insulating layers 111a and 111b is formed using an etching process such as sand blast. In this case, the stopper layer BL may act as an etching stopper to define the depth of the recess 110H. The open area of the mask layer 250 may be a peripheral area of the stopper layer BL, that is, a spaced area between the stopper layer BL and the guide pattern BP during the recess portion formation process (particularly, the second half). The third insulating layer 111b) may be exposed. The guide pattern BP is spaced apart from the stopper layer BL to define the periphery of the bottom surface of the recess, and the spaced apart area induces over-etching in the latter part of the etching. As a result, the groove G is formed as in the present embodiment. Can be formed. In this process, the inclination angle is kept high even at the lower end of the recess wall surface S, and the length of the inclination area ("Wf" in FIG. 9) can be reduced.

When the recess portion forming process is finished, as illustrated in FIG. 12E, the mask layer 250 may be removed to provide a frame 110 in which the recess portion 110H and the wiring structure 115 are formed. The recess 110H formed in the present exemplary embodiment may have a wall surface S having a large inclination angle by using the guide pattern BP and the stopper layer BL.

13A to 13E are schematic cross-sectional views illustrating a manufacturing process of the fan-out semiconductor package of FIG. 9.

The manufacturing process may be understood as a process of manufacturing a semiconductor package using a frame manufactured in the foregoing process.

Referring to FIG. 13A, the semiconductor chip 120 is disposed in the recess 110H and attached to the stopper layer BL. Attaching the stopper layer BL may be performed using an adhesive member 125 such as a die attach film DAF. Meanwhile, the semiconductor chip 120 may be attached to the connection pad 120P in a state in which a metal bump 120B such as a copper pillar is formed. The metal bumps 120B may be formed at least higher than the first surface 110A of the frame 110.

Next, referring to FIG. 13B, the first surface 110A of the frame 110 and the semiconductor chip 120 are sealed using the encapsulant 130, and the metal bumps 120B and the third wiring layer 112c are sealed. The polishing process can be performed to expose this. The encapsulant 130 may be formed by laminating a film such as ABF and then curing the film. The encapsulant 130 may be formed to cover the metal bumps 120B together with at least the first surface 110A of the frame 110. The metal bumps 120B and the third wiring layer 112c are exposed on the surface of the encapsulant 130 through the polishing process, and the surfaces of the encapsulant 130 and the metal bumps 120B and the third wiring layer 112c are exposed. The top surfaces can have a substantially flat coplanar surface.

Subsequently, referring to FIG. 13C, the connection member 140 having the redistribution layers 142 and 143 is formed on the encapsulant 130. The insulating layer 141 is formed by applying and curing an insulating material such as PID, and the redistribution layers 142 and 143 are formed by a plating process. The redistribution layers 142 and 143 include the redistribution layer 142 and the connection vias 143, and the metal bumps 120B and the third wiring layer 112c through the connection vias 143 formed in the adjacent insulating layer 141. Can be connected to. The insulating layer 141, the redistribution layer 142, and the connection via 143 may be formed in different layers depending on the design.

Next, referring to FIG. 13D, the first passivation layer 171 may be formed on the connection member 140, and the under bump metal layer 160 may be formed by a known metallization method. An opening is formed in the first passivation layer 171 to expose a portion of the redistribution layer 142, and the under bump metal layer (152) is formed on the opening of the first passivation layer 151 so as to be connected to a portion of the redistribution layer 142. 160). The under bump metal layer 160 may be formed in the opening of the first passivation layer 151 by a known metallization method using a known conductive material, that is, a metal, but is not limited thereto.

Subsequently, referring to FIG. 13E, after the carrier film 200 is removed, the electrical connection structure 170 is formed on the under bump metal layer 160. The electrical connection structure 170 may be formed of a conductive material, for example, a low melting point metal such as Sn-Al-Cu alloy. The electrical connection structure 170 may be a land, a ball, a pin, or the like. The electrical connection structure 170 may be formed of multiple layers or a single layer. The number, spacing, arrangement, etc. of the electrical connection structure 170 is not particularly limited, and can be sufficiently modified according to design matters by those skilled in the art. For example, the number of the electrical connection structure 170 may be several tens to thousands, depending on the number of connection pads 120P, may have a number more or less. The electrical connection structure 170 may be disposed on the main board or other package of the electronic device and fixed to the main board or other package together with the electrical connection through a reflow process.

14 is a schematic cross-sectional view of a fan-out semiconductor package according to another example.

Referring to FIG. 14, the fan-out semiconductor package 100A according to another example may include the recess 110H at a level between the bottom surface of the recess 110H and the first surface 110A of the frame 110. It can be understood to be similar to the fan-out semiconductor package 100 shown in FIGS. 9 to 10B except for including an additional guide pattern BP ′ surrounding the. The description of the components of the present exemplary embodiment may refer to the description of the same or similar components of the fan-out semiconductor package 100 illustrated in FIGS. 9 to 10B unless specifically described otherwise.

The semiconductor package 100A according to the present exemplary embodiment includes a first guide pattern BP and a stopper layer BL, similarly to the guide pattern BP and the stopper layer BL shown in FIG. 9. The second guide pattern BP ′ is included at a level higher than the first guide pattern BP, that is, at a level between the bottom surface of the recess 110H and the first surface 110A of the frame 110. .

Similar to the first guide pattern BP, the second guide pattern BP ′ may be formed of a material having an etching rate lower than that of the insulating layers of the frame 110. For example, the second guide pattern BP ′ may include a metal such as copper (Cu). The second guide pattern BP ′ is disposed to be adjacent to the recess portion wall surface S ′, and the second guide pattern BP ′ is partially exposed to the recess portion wall surface S ′ as in the present embodiment. But it is not limited thereto. The wiring structure 115 of the frame 110 may include a wiring layer (not shown) positioned at the same level as the second guide pattern BP ′. In another embodiment, the second guide pattern BP ′ may be disposed between the first and second insulating layers 111a and 111b to be formed together with the first wiring layer 112a. The second guide pattern BP ′ may also be configured not to be directly connected to the wiring layer positioned at the same level, but is not limited thereto.

The fan-out semiconductor package 100 according to the present exemplary embodiment includes a guide pattern BP disposed in the frame 110 along an edge of a bottom surface of the recess 110H. The guide pattern BP may be used as an etch barrier structure for forming a recess along with the above-described stopper layer BL.

The second guide pattern BP ′ is positioned at an intermediate level of the recessed wall S ′ and thus, similar to the first guide pattern BP, the profile of the wall surface S of the recess 110H (eg, the inclination angle). Can be used to The second guide pattern BP ′ and the other stopper layer (BL ′ of FIG. 15A) may control the profile of the upper region S1 of the wall portion S ′ of the recess part by adjusting a position and a gap. Subsequently, the first guide pattern BP and the stopper layer BL may control the profile of the lower region S2 of the wall portion S ′ of the recess part by adjusting a position and a gap. The upper region S1 and the lower region S2 of the recess portion wall surface S ′ obtained in this embodiment may have different profiles (eg, inclination angles).

The second guide pattern BP ′ employed in the present embodiment may be advantageously used to control the wall profile of the relatively deep recess or precisely control the wall profile. In addition, the second guide pattern BP ′ may serve to protect the wiring structure 115 of the frame 110 positioned adjacent to the recess 110H.

In the present exemplary embodiment, the second guide pattern BP ′ may have the same shape as the first guide pattern BP, but may have another shape (see FIGS. 11A and 11B). In addition, although the second guide pattern BP ′ is illustrated as being used together with the first guide pattern BP, only the second guide pattern BP ′ may be employed as necessary, and in this case, the recess The stopper layer BL disposed on the lower bottom surface may be formed to cover the entire bottom surface of the recess part.

15A to 15D are schematic cross-sectional views illustrating a process of forming a frame of the fan-out semiconductor package of FIG. 14.

First, referring to FIG. 15A, a frame 110 ′ is disposed on a carrier film 220, and a mask layer 250 having an open area is formed on the first surface 110A of the frame 110 ′. . The frame 110 ′ employed in this embodiment is formed of a material disposed between the first and third insulating layers 111a and 111c together with a wiring structure 115 similar to that of the frame 110 shown in FIGS. 12B and 12C. The first stopper layer BL and the first guide pattern BP are included. In addition, the frame 110 'includes a second stopper layer BL' and a second guide pattern BP 'disposed at a level higher than that of the first guide pattern BP, that is, within the first insulating layer 111a. do. The second stopper layer BL 'and the second guide pattern BP' may be formed to be spaced apart from each other similarly to the arrangement of the first stopper layer BL and the first guide pattern BP.

Next, referring to FIG. 15B, a first etching process for forming a recess is performed using the mask layer 250 having an open area. The first etching process may be performed up to the second stopper layer BL '. When the etching depth is adjacent to the second stopper layer BL ', the etching progresses slowly on the second stopper layer BL' and is spaced apart between the second stopper layer BL 'and the second guide pattern BP'. In the region, the over-etching may be performed to form the groove G1. In this process, the wall surface S1 of the upper region may have a steep inclination angle. That is, the inclined area can be narrowed. In this case, the bottom edge of the recess may be defined by the second guide pattern BP ′.

Subsequently, as shown in FIG. 15C, the second stopper layer is removed, and as shown in FIG. 15D, a second etching process for forming a recess is performed using the mask layer 250 having the open area. do. The secondary etching process may be performed up to the first stopper layer BL. When the etching depth is adjacent to the first stopper layer BL, the etching proceeds slowly on the first stopper layer BL and is overetched in the spaced apart region between the first stopper layer BL and the first guide pattern BP. This may proceed to form the groove (G). In this process, the inclined region of the wall surface S2 of the lower region may be narrowed. In this case, the bottom edge of the recess may be defined by the first guide pattern BP. As such, the frame 110 ′ having the recess 110H and the wiring structure 115 together with the guide pattern BP ′ of the intermediate level may be provided. According to the present exemplary embodiment, the recess 110H having the desired wall profile may be formed together with the first guide pattern BP by using the second guide pattern BP ′ positioned at an intermediate level.

As a subsequent process, the semiconductor package shown in FIG. 14 may be provided by applying the semiconductor manufacturing process shown in FIGS. 13A to 13F.

16 is a schematic cross-sectional view of a fan-out semiconductor package according to another example.

Referring to FIG. 16, the fan-out semiconductor package 100B according to another example may have a guide pattern BP at a level between the bottom surface of the recess 110H and the first surface 110A of the frame 110. Arranged so as to surround the recessed portion 110H, the end portion of the stopper layer BL is wider than the area of the bottom surface of the recessed portion 110H is embedded in the frame 110, and consequently the stopper layer BL It can be understood that similar to the fan-out semiconductor package 100A according to another example shown in FIG. 14 except that it is formed in the groove (G). The description of the components of the present exemplary embodiment may refer to the description of the same or similar components of the fan-out semiconductor package 100A according to another example shown in FIG. 14 unless otherwise described.

In the semiconductor package 100B according to the present exemplary embodiment, a stopper layer BL is disposed on the bottom surface of the recess 110H without arranging a guide pattern, and the upper portion of the semiconductor package 100B is disposed above the stopper layer BL. The guide pattern BP is disposed at a level between the bottom surface of 110H and the first surface 110A of the frame 110.

The guide pattern BP is disposed to be adjacent to the recess portion wall surface S ′, and the guide pattern BP may be partially exposed to the recess portion wall surface S ′ as in the present embodiment, but is not limited thereto. Do not. The wiring structure 115 of the frame 110 may include a wiring layer (not shown) positioned at the same level as the guide pattern BP. In another embodiment, the guide pattern BP may be disposed between the first and second insulating layers 111a and 111b and formed together with the first wiring layer 112a. The guide pattern BP may also be configured not to be directly connected to the wiring layer positioned at the same level, but is not limited thereto.

The guide pattern BP may be positioned at an intermediate level of the recess portion wall surface S ′ and used to adjust a profile (eg, an inclination angle) of the wall surface S of the recess portion 110H. The guide pattern BP and the other stopper layer (BL 'of FIG. 16A) can control the profile of the upper region S1 and the lower region S2 of the recess wall wall S' by adjusting the position and spacing. Can be. The upper region S1 and the lower region S2 of the recess portion wall surface S ′ obtained in this embodiment may have different profiles (eg, inclination angles).

The guide pattern BP employed in the present embodiment can be advantageously used to control the wall profile of the relatively deep recess or to precisely control the wall profile. In addition, the guide pattern BP may serve to protect the wiring structure 115 of the frame 110 positioned adjacent to the recess 110H.

In the present embodiment, the stopper layer BL may be formed to cover the entire bottom surface of the recess 110H, and as a result, the groove G may be formed in the stopper layer BL. In this case, the thickness of the region where the groove G of the stopper layer BL is formed may be thinner than the thickness of other regions.

17A to 17D are schematic cross-sectional views illustrating a process of forming a frame of the fan-out semiconductor package of FIG. 16.

First, referring to FIG. 17A, a frame 110 ′ is disposed on a carrier film 220, and a mask layer 250 having an open area is formed on the first surface 110A of the frame 110 ′. . The frame 110 ′ employed in the present embodiment is formed of a material disposed between the first and third insulating layers 111a and 111c together with a wiring structure 115 similar to that of the frame 110 shown in FIGS. 12B and 12C. One stopper layer BL is included. In addition, the semiconductor device includes a second stopper layer BL 'and a guide pattern BP disposed at a level higher than that of the stopper layer BL, that is, inside the first insulating layer 111a. The second stopper layer BL ′ and the guide pattern BP may be formed to be spaced apart from each other.

Next, referring to FIG. 17B, a first etching process for forming a recess is performed using the mask layer 250 having an open area. The first etching process may be performed up to the second stopper layer BL '. When the etching depth is adjacent to the second stopper layer BL ', the etching progresses slowly on the second stopper layer BL' and overeating in the spaced apart region between the second stopper layer BL 'and the guide pattern BP. An angle may be progressed to form a groove G1. In this process, the wall surface S1 of the upper region may have a steep inclination angle. That is, the inclined area can be narrowed. In this case, the bottom edge of the recess may be defined by the guide pattern BP.

Subsequently, as shown in FIG. 17C, the second stopper layer is removed, and as shown in FIG. 17D, a second etching process for forming a recess is performed using the mask layer 250 having the open area. do. The secondary etching process may be performed up to the first stopper layer BL. When the etching depth is adjacent to the first stopper layer BL, the etching progresses slowly on the first stopper layer BL, and the overetch is performed in the region adjacent to the wall surface of the recess of the first stopper layer BL. G) can be formed. In this process, the inclined region of the wall surface S2 of the lower region may be narrowed. As such, the frame 110 ′ having the recess 110H and the wiring structure 115 together with the guide pattern BP of the intermediate level may be provided. According to the present exemplary embodiment, the recess 110H having a desired wall profile may be formed using the guide pattern BP positioned at an intermediate level.

As a subsequent process, the semiconductor package shown in FIG. 16 may be provided by applying the semiconductor manufacturing process shown in FIGS. 13A to 13F.

The expression example used in the present disclosure does not mean the same embodiment, but is provided to emphasize different unique features. However, the examples presented above do not exclude implementations in combination with the features of other examples. For example, although a matter described in one particular example is not described in another example, it may be understood as a description related to another example unless otherwise described or contradicted with the matter in another example.

The terms used in the present disclosure are merely used to describe examples and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" include plural forms unless the context clearly indicates otherwise.

Claims (23)

A plurality of insulating layers, a plurality of wiring layers disposed on the plurality of insulating layers, and a plurality of connecting via layers penetrating the plurality of insulating layers and electrically connecting the plurality of wiring layers, and a stopper layer on the bottom surface thereof. A frame having recesses arranged;
A semiconductor chip having a connection pad, an active surface on which the connection pad is disposed, and an inactive surface opposite to the active surface, the semiconductor chip being disposed in the recess portion such that the inactive surface is connected to the stopper layer;
An encapsulant covering at least a portion of the semiconductor chip and filling at least a portion of the recess portion; And
A connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pad of the semiconductor chip; Including;
The guide pattern is disposed in the frame adjacent to the wall surface of the recess,
Grooves are formed at the corners of the bottom surface of the recess,
Fan-out semiconductor package.
The method of claim 1,
The guide pattern is disposed above the stopper layer,
The groove portion is formed in the stopper layer,
Fan-out semiconductor package.
The method of claim 2,
The thickness of the region where the groove portion of the stopper layer is formed is thinner than the thickness of other regions,
Fan-out semiconductor package.
The method of claim 1,
The guide pattern is disposed at the same level as the stopper layer,
The groove portion is formed in the insulating layer between the guide pattern and the stopper layer,
Fan-out semiconductor package.
The method of claim 4, wherein
The guide pattern and the stopper layer are physically spaced apart,
Fan-out semiconductor package.
The method of claim 5,
The groove portion has a ring shape forming a closed loop along an edge of the bottom surface of the recess portion,
Fan-out semiconductor package.
The method of claim 4, wherein
The guide pattern is partially connected to the stopper layer,
Fan-out semiconductor package.
The method of claim 7, wherein
The groove portion is a plurality of groove portions each formed along the edge of the bottom surface of the recess portion,
Fan-out semiconductor package.
The method of claim 1,
The guide pattern and the stopper layer each comprise a metal,
At least one wiring layer of the plurality of wiring layers includes ground,
At least one of the guide pattern and the stopper layer is electrically connected to the ground,
Fan-out semiconductor package.
Claim 10 has been abandoned upon payment of a setup registration fee. The method of claim 1,
The stopper layer has a larger planar area than the inactive surface of the semiconductor chip,
Fan-out semiconductor package.
Claim 11 was abandoned upon payment of a set-up fee. The method of claim 1,
The bottom surface of the recess portion is wider than the inactive surface of the semiconductor chip,
Fan-out semiconductor package.
Claim 12 was abandoned upon payment of a set-up fee. The method of claim 1,
Inactive surface of the semiconductor chip is attached to the stopper layer through an adhesive member,
Fan-out semiconductor package.
Claim 13 was abandoned upon payment of a set-up fee. The method of claim 1,
The wall surface of the recess is tapered,
Fan-out semiconductor package.
The method of claim 1,
The wall surface of the recess portion has a plurality of different profiles,
Fan-out semiconductor package.
Claim 15 was abandoned upon payment of a set-up fee. The method of claim 1,
Metal bumps are disposed on the connection pads of the semiconductor chip,
The top surface of the metal bump is coplanar with the top surface of the encapsulant,
Fan-out semiconductor package.
Claim 16 was abandoned upon payment of a set-up fee. The method of claim 15,
The upper surface of the uppermost wiring layer of the plurality of wiring layers of the frame or the upper surface of the connecting via layer of the uppermost of the plurality of connecting via layers is coplanar with the upper surface of the metal bump and the upper surface of the encapsulant,
Fan-out semiconductor package.
Claim 17 was abandoned upon payment of a set-up fee. The method of claim 1,
The plurality of insulating layers includes a core insulating layer, at least one first buildup insulating layer disposed below the core insulating layer, and at least one second buildup insulating layer disposed above the core insulating layer,
The core insulating layer is thicker than each of the first and second build-up insulating layers,
Fan-out semiconductor package.
Claim 18 was abandoned when the set registration fee was paid. The method of claim 17,
The number of layers of the first build-up insulating layer and the number of layers of the second build-up insulating layer are the same,
Fan-out semiconductor package.
Claim 19 was abandoned upon payment of a set-up fee. The method of claim 17,
The recess portion penetrates at least the core insulating layer and penetrates at least one build-up insulating layer of the one or more first and second build-up insulating layers.
Fan-out semiconductor package.
Claim 20 was abandoned when the set registration fee was paid. The method of claim 17,
A first connection via penetrating the first build-up insulating layer and a second connection via penetrating the second build-up insulating layer are tapered in opposite directions;
Fan-out semiconductor package.
Claim 21 has been abandoned upon payment of a set-up fee. The method of claim 1,
A first passivation layer disposed above the connection member and having an opening exposing at least a portion of the redistribution layer;
An under bump metal layer disposed on an opening of the first passivation layer and connected to at least a portion of the exposed redistribution layer; And
An electrical connection structure disposed on the first passivation layer and connected to the under bump metal layer; Further comprising,
Fan-out semiconductor package.
Claim 22 was abandoned upon payment of a set-up fee. The method of claim 21,
A second passivation layer disposed below the frame, the second passivation layer having an opening that exposes at least a portion of the wiring layers disposed on a lowermost side of the plurality of wiring layers; Including more;
Fan-out semiconductor package. Claim 23 has been abandoned upon payment of a set-up fee. The method of claim 1,
At least one of the plurality of wiring layers is disposed below the stopper layer,
Fan-out semiconductor package.

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