CN105990173B - Pad thickness monitoring method and wafer with pad thickness monitoring of structures - Google Patents
Pad thickness monitoring method and wafer with pad thickness monitoring of structures Download PDFInfo
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- CN105990173B CN105990173B CN201510054213.7A CN201510054213A CN105990173B CN 105990173 B CN105990173 B CN 105990173B CN 201510054213 A CN201510054213 A CN 201510054213A CN 105990173 B CN105990173 B CN 105990173B
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Abstract
The invention discloses a kind of pad thickness monitoring methods, comprising the following steps: provides the semiconductor base for being located at wafer test area；Intermetallic dielectric layer is formed on a semiconductor substrate；Intermetallic dielectric layer is performed etching and forms the first metal area after being filled using the first metal；Second metal layer is formed in intermetallic dielectric layer and the first metal area surface deposition, loss amount of first metal under etching technics is less than bimetallic loss amount；Etch at least partly second metal layer on the first metal area surface；Interlayer dielectric layer is formed in the first metal area, second metal layer surface and intermetallic dielectric layer surface deposition；Etch at least partly interlayer dielectric layer on second metal layer surface and the first metal area surface；The difference in height of second metal layer upper surface and the first metal area upper surface is measured, pad thickness is obtained.Above-mentioned pad thickness monitoring method can realize effective monitoring to pad thickness.Also disclose a kind of wafer with pad thickness monitoring of structures.
Description
Technical field
The present invention relates to technical field of semiconductor preparation, more particularly to a kind of pad thickness detection method and have weldering
The wafer of disc thickness monitoring of structures.
Background technique
In the final stage of chip preparation, need to define some pads (pad) on chip, for connecing lead, test electricity
Learn performance and yield etc..It for connecing the region of lead needs that there is good electric conductivity, therefore the usual aluminium of material, so
Referred to as aluminium pad (AL pad).Its surrounding is surrounded by medium, plays the role of isolation and protection.It is sequentially in technique preparation
First deposit is used to form the metal (such as aluminium) of pad, and redeposited medium finally falls the dielectric etch of metal surface, so that metal
It reveals to form pad.Because of technologic fluctuation, in the excessively thin or etching process of top-level metallic (Top metal) deposition
Metal loss (loss) excessively, can all cause final remaining pad thickness excessively thin, form section structure as shown in Figure 1.?
When electric property and yield are tested, pin, which pricks, certain pressure on pad.Under the action of certain needle pressure, pad
The ability to bear for having exceeded itself, causes pad to crack, and can not work so as to cause test result is abnormal with chip.Therefore it needs
The pad thickness being prepared is monitored, to guarantee its yields.Industry shortage effectively supervises pad thickness at present
The test structure and method of survey.
Summary of the invention
In order to solve the problems, such as it is existing in the prior art lack the method that is effectively monitored to pad thickness, it is of the invention
A kind of pad thickness monitoring method is provided.
A kind of pad thickness monitoring method, comprising the following steps: the semiconductor base for being located at wafer test area is provided；Institute
It states and forms intermetallic dielectric layer on semiconductor base；The intermetallic dielectric layer is performed etching and is filled out using the first metal
The first metal area is formed after filling；Second metal layer is formed in the intermetallic dielectric layer and the first metal area surface deposition,
Loss amount of first metal under etching technics is less than the bimetallic loss amount；Etch the first metal area table
At least partly described second metal layer in face；Between first metal area, the second metal layer surface and the metal
Dielectric layer surface deposits to form interlayer dielectric layer；Etch the second metal layer surface and first metal area surface extremely
Interlayer dielectric layer described in small part；The difference in height of the second metal layer upper surface Yu the first metal area upper surface is measured, is obtained
Pad thickness.
Etching at least partly described second metal layer on first metal area surface in one of the embodiments,
In step, the second metal layer on first metal area surface is that partial etching makes the second metal layer extend to described the
One metal area；The width that the second metal layer extends to first metal area is greater than or equal to 3 microns.
Etching the second metal layer surface and first metal area surface extremely in one of the embodiments,
Described in small part the step of interlayer dielectric layer in, the inter-level dielectric on first metal area surface is partially etched so that described
Interlayer dielectric layer extends to first metal area；The width that the interlayer dielectric layer extends to first metal area be greater than or
Equal to 3 microns.
In one of the embodiments, in the height for measuring the second metal layer upper surface and the first metal area upper surface
It is that the second metal layer upper surface and the first metal are measured by atomic force microscope in the step of difference, acquisition pad thickness
The difference in height of area upper surface obtains pad thickness.
The intermetallic dielectric layer is being performed etching and is being filled using the first metal in one of the embodiments,
After further comprise the steps of: after the step of forming the first metal area the intermetallic dielectric layer and first metal area are carried out it is flat
Smoothization processing.
First metal uses tungsten in one of the embodiments,.
Second metal uses aluminium in one of the embodiments,.
To solve the above-mentioned problems, the present invention also provides a kind of wafers with pad thickness monitoring of structures.
A kind of wafer with pad thickness monitoring of structures, including device region and test section；The device region includes partly leading
Body device architecture；The test section includes pad thickness monitoring of structures；The pad thickness monitoring of structures includes: semiconductor-based
Bottom；The intermetallic dielectric layer and the first metal area being formed on the semiconductor base；It is formed in inter-metal medium area table
Face and the second metal layer for extending to first metal area, loss amount of first metal under etching technics are less than described
Bimetallic loss amount；It is formed in the second metal layer and the inter-metal medium layer surface and by part second gold medal
Belong to the interlayer dielectric layer that layer and first metal area reveal.
The area of the second metal layer and first metal area that reveal in one of the embodiments, is
20~70 square microns.
The width that the second metal layer extends to first metal area in one of the embodiments, is greater than or equal to
3 microns.
Above-mentioned pad thickness monitoring method and the wafer with pad thickness monitoring of structures, are formed by the second Metal deposition
Pad and the first metal area between be formed with step, the step height be etch after pad thickness.Therefore, to pad
During thickness monitor, it is only necessary to difference in height, that is, step height of second metal layer upper surface and the first metal area upper surface
It measures, can realize effective monitoring to pad thickness, so as to find pad thickness abnormal conditions in time and carry out
It improves, causes large-tonnage product to scrap after preventing bad products slice, the yields of product can be effectively improved.
Detailed description of the invention
Fig. 1 is the diagrammatic cross-section for the pad structure being prepared in traditional chip fabrication process；
Fig. 2 is the flow chart of the pad thickness monitoring method in an embodiment；
Fig. 3 is that the wafer test area with pad thickness monitoring of structures after step S130 is completed in embodiment illustrated in fig. 2
Cross-sectional view；
Fig. 4 is that the wafer test area with pad thickness monitoring of structures after step S150 is completed in embodiment illustrated in fig. 2
Cross-sectional view；
Fig. 5 is that the wafer test area with pad thickness monitoring of structures after step S160 is completed in embodiment illustrated in fig. 2
Cross-sectional view；
Fig. 6 is the cross-sectional view in the wafer test area with pad thickness monitoring of structures in an embodiment；
Fig. 7 is the top view in the wafer test area with pad thickness monitoring of structures in embodiment illustrated in fig. 6.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Fig. 2 is the flow chart of the pad thickness monitoring method in an embodiment, is included the following steps,
S110 provides the semiconductor base positioned at wafer test area.
In the preparation process of semiconductor, often will to carry out some performance tests to the semiconductor devices being prepared
Zoning on wafer (wafer) in addition to semiconductor devices area separates partial region as test section, so that on wafer
Including semiconductor devices area and test section.And for realizing the pad thickness monitoring of structures (test of pad monitoring in the present embodiment
Key) then it is formed in the region.
S120 forms intermetallic dielectric layer on a semiconductor substrate.
Form intermetallic dielectric layer (Inter Metal Dielectric, IMD) on a semiconductor substrate.In the present embodiment
In, formed intermetallic dielectric layer the step of with wafer on semiconductor devices preparation process in formed intermetallic dielectric layer step
It is rapid identical.
S130 is performed etching intermetallic dielectric layer and forms the first metal area after being filled using the first metal.
The intermetallic dielectric layer in the region of the first metal area to be formed is subjected to dry etching according to the definition of photolithography plate, and
It is filled to form the first metal area using the first metal.First metal of filling should have etches loss in etching technics
Small feature is measured, that is, needs to guarantee in etching process, the loss amount of the first metal area will be much smaller than the loss amount of pad.
In the present embodiment, the first metal of filling is tungsten (W).
Fig. 3 is the cross-sectional view of device architecture after completing step S130.Such as Fig. 3, intermetallic dielectric layer 102 and the first metal area
104 are formed on semiconductor base 100.It in the present embodiment, can also be to intermetallic dielectric layer after carrying out the first metal filling
Planarization process is carried out with the first metal area.
S140 forms second metal layer in intermetallic dielectric layer and the first metal area surface deposition.
The step of this step is with metal layer needed for formation pad in the preparation process of semiconductor devices in wafer is identical, from
And guarantee that the metal layer thickness formed in the second metal thickness and semiconductor devices that are formed is consistent.The thickness root of second metal layer
It is determined according to pad thickness to be formed.In the present embodiment, second metal layer use aluminium, formation with a thickness of
S150 etches at least partly second metal layer on the first metal area surface.
Dry etching is carried out to second metal layer, at least partly second metal etch on the first metal area surface is fallen, is made
It obtains second metal layer and extends to the first metal area surface.Fig. 4 is the cross-sectional view of device architecture after completing step S150.Second metal
Layer 106 extends to the width of the first metal area 104 as width shown in b in Fig. 4, which is at least 3 microns, so that it is guaranteed that the
Two metal layers 106 are connected with the first metal area 104.In other examples, the second of 104 surface of the first metal area surface
Metal layer 106 can also be all etched away.
S160, deposit form interlayer dielectric layer.
Interlayer dielectric layer is formed in second metal layer surface, the first metal area and intermetallic dielectric layer surface deposition
(Inter Layer Dielectric, ILD).In the present embodiment, the material of interlayer dielectric layer is silicon nitride and silica
Mixture, in other examples, interlayer dielectric layer may be silicon nitride or silica.Fig. 5 is to complete step
The cross-sectional view of device architecture after S160, the thickness of interlayer dielectric layer 108 exist
S170 etches at least partly interlayer dielectric layer on second metal layer surface and the first metal area surface.
In this step, the depth performed etching to inter-level dielectric is identical as semiconductor devices preparation process, to guarantee most
End form at pad thickness can really reflect the pad thickness of semiconductor devices.According to definition by second metal layer surface
At least partly inter-level dielectric etches away, to reveal second metal in the region to form pad.Simultaneously by the first metal
At least partly inter-level dielectric on area surface etches away, and the surface open of the first metal area is come out.Carrying out inter-level dielectric etching
In the process, the second metal on pad can also have certain loss, so that the actual (real) thickness of finally obtained pad is small
In the thickness of second metal layer, as shown in Figure 6.In the present embodiment, the interlayer dielectric layer 108 on 104 surface of the first metal area is
It is partially etched, so that interlayer dielectric layer 108 extends to the first metal area 104.Interlayer dielectric layer 108 extends to
The width of one metal area 104 is width shown in c in Fig. 6, which is at least 3 microns, so that it is guaranteed that intermetallic dielectric layer 102
It is not exposed at a time, will not be etched away.In other examples, the interlayer dielectric layer 108 on the first metal area surface can also
To be etched completely away.In the present embodiment, the second metal layer that reveals forms pad 110, and the revealed
The area of the area of two metal layers and the first metal area 104 is 20~70 square microns, facilitates the scanning of atomic force microscope
Measurement.
S180 measures pad thickness.
Since the loss amount of the first metal in etching technics is smaller, it is much smaller than bimetallic loss amount, therefore can be with
Ignore loss amount of first metal in the presence of etching technics.Therefore by second metal layer upper surface and the first metal area
The height difference H on surface more can really reflect the actual (real) thickness of pad 110.Specifically, pass through AFM (Atomic
Force Microscope, atomic force microscope) probe scanning pad and the first metal area stepped area, i.e., from pad area
Domain is scanned to the first metal area, thus step difference (the i.e. table on pad upper surface and the first metal area between two regions of measurement
The difference in height in face), the actual thickness of pad is obtained, to realize the function of on-line monitoring pad thickness.
On-line monitoring pad thickness may be implemented in above-mentioned pad thickness monitoring method, compensates for the blank of the parameter monitoring,
The pad thickness because of caused by technological fluctuation can be prevented abnormal so caused by pad cracking and packaging and testing it is abnormal, and can be with
It finds the problem and improves online in time, cause large yields scrapped, be conducive to improve product after preventing bad products slice.
The present invention also provides a kind of wafer with pad thickness monitoring of structures, the cross-sectional view of test section such as Fig. 6 institutes
Show；Fig. 7 is then the top view in the wafer test area with pad thickness monitoring of structures in Fig. 6.Due to not right in the present invention
Semiconductor device structure in the device region of wafer improves, therefore Fig. 6 and Fig. 7 show only the structural representation in wafer test area
Figure.A kind of wafer with pad thickness monitoring of structures includes device region (not shown) and test section.Wherein, device region includes
Semiconductor device structure, test section then include pad thickness monitoring of structures 10.Pad thickness monitoring of structures 10 includes semiconductor-based
Bottom 100；The intermetallic dielectric layer 102 and the first metal area 104 being formed on semiconductor base 100；It is formed in inter-metal medium
102 surface of layer and the second metal layer 106 for extending to the first metal area 104；It is formed in second metal layer 106 and inter-metal medium
Part second metal layer 106 and the first metal area 104 are simultaneously revealed the interlayer dielectric layer to form pad 110 by 102 surface of layer
108.The area of the second metal layer (i.e. pad 110) and the first metal area 104 (i.e. region shown in a in Fig. 6) that reveal is equal
For 20~70 square microns.
In the present embodiment, it is width shown in b, width in Fig. 6 that pad 110, which extends to the width of the first metal area 104,
Degree is greater than or equal to 3 microns, so as to ensure that pad 110 and the first metal area 104 are connected with each other.Interlayer dielectric layer 108
Material is the mixture of silicon nitride and silica, in other examples, interlayer dielectric layer 108 or silicon nitride or
Person's silica.The width that interlayer dielectric layer 108 extends to the first metal area 104 is that width shown in c, the width are same in Fig. 6
Sample, so that it is guaranteed that intermetallic dielectric layer 102 will not reveal, will not be etched away also greater than or equal to 3 microns, so as to
Guarantee the flatness on the surface of the first metal area 104 revealed.In other examples, the first metal area 104 is complete
It reveals entirely, i.e., the edge of the edge of second metal layer 106 and the first metal area 104 is located at same perpendicular, and interlayer is situated between
The edge of the edge of matter layer 108 and the first metal area 104 is similarly positioned in same perpendicular.
First metal area 104 needs have the characteristics that loss amount is lesser under etching technics, so that the first metal area
104 loss amount under etching technics is much smaller than the loss amount of second metal layer 106.Accordingly, with respect under etching technics second
The loss amount of the loss amount of metal layer 106 (i.e. pad 110), the first metal area 104 can be ignored, so that being formed in pad
The height difference H of 104 upper surface of 110 upper surfaces and the first metal area can reflect out the actual thickness of pad 110.In the present embodiment
In, the first metal area 104 uses tungsten, and second metal layer 106 uses aluminium.It therefore, can be real by carrying out survey monitoring to height difference H
The thickness for now monitoring pad 110 on-line, compensates for the blank of the parameter monitoring, and pad is thick caused by can preventing because of technological fluctuation
It spends abnormal and then caused pad cracking and packaging and testing is abnormal, and can find the problem and improve online in time, prevent not
Large yields scrapped, be conducive to improve product is caused after good product slice.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of pad thickness monitoring method, comprising the following steps:
The semiconductor base for being located at wafer test area is provided；
Intermetallic dielectric layer is formed on the semiconductor base；
The intermetallic dielectric layer is performed etching and forms the first metal area after being filled using the first metal；
Second metal layer is formed in the intermetallic dielectric layer and the first metal area surface deposition, first metal is being carved
Loss amount under etching technique is less than the bimetallic loss amount；
Etch at least partly described second metal layer on first metal area surface；
Interlayer is formed in first metal area, the second metal layer surface and the intermetallic dielectric layer surface deposition to be situated between
Matter layer；
Etch at least partly described interlayer dielectric layer on the second metal layer surface and first metal area surface；
The difference in height of the second metal layer upper surface Yu the first metal area upper surface is measured, pad thickness is obtained.
2. pad thickness monitoring method according to claim 1, which is characterized in that on etching first metal area surface
At least partly second metal layer the step of in, the second metal layer on first metal area surface makes for partial etching
The second metal layer extends to first metal area；The width that the second metal layer extends to first metal area is big
In or equal to 3 microns.
3. pad thickness monitoring method according to claim 1, which is characterized in that etching the second metal layer surface
And first metal area surface at least partly interlayer dielectric layer the step of in, the layer on first metal area surface
Between medium be partially etched so that the interlayer dielectric layer extends to first metal area；The interlayer dielectric layer extends to
The width of first metal area is greater than or equal to 3 microns.
4. pad thickness monitoring method according to claim 1, which is characterized in that the table on measuring the second metal layer
The difference in height in face and the first metal area upper surface, obtain pad thickness the step of in, be measured by atomic force microscope described in
The difference in height of second metal layer upper surface and the first metal area upper surface obtains pad thickness.
5. pad thickness monitoring method according to claim 1, which is characterized in that carried out to the intermetallic dielectric layer
It is further comprised the steps of: after the step of etching and forming the first metal area after being filled using the first metal
Planarization process is carried out to the intermetallic dielectric layer and first metal area.
6. pad thickness monitoring method according to claim 1, which is characterized in that first metal uses tungsten.
7. pad thickness monitoring method according to claim 1, which is characterized in that second metal uses aluminium.
8. a kind of wafer with pad thickness monitoring of structures, including device region and test section；The device region includes semiconductor
Device architecture；It is characterized in that, the test section includes pad thickness monitoring of structures；The pad thickness monitoring of structures includes:
Semiconductor base；
The intermetallic dielectric layer and the first metal area being formed on the semiconductor base；
It is formed in inter-metal medium area surface and extends to the second metal layer of first metal area, first metal
Loss amount under etching technics is less than the bimetallic loss amount；
It is formed in the second metal layer and the inter-metal medium layer surface and by the part second metal layer and described
The interlayer dielectric layer that one metal area reveals.
9. the wafer according to claim 8 with pad thickness monitoring of structures, which is characterized in that is revealed is described
The area of second metal layer and first metal area is 20~70 square microns.
10. the wafer according to claim 8 with pad thickness monitoring of structures, which is characterized in that second metal
The width that layer extends to first metal area is greater than or equal to 3 microns.
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| CN105334414B (en) * | 2015-10-31 | 2018-11-06 | 上海与德通讯技术有限公司 | A kind of conductive part high measure device and test method |
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| US5326428A (en) * | 1993-09-03 | 1994-07-05 | Micron Semiconductor, Inc. | Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability |
| JPH07297326A (en) * | 1994-04-20 | 1995-11-10 | Hitachi Ltd | Socket for testing semiconductor chip |
| CN102299094A (en) * | 2010-06-24 | 2011-12-28 | 无锡华润上华半导体有限公司 | manufacturing method of fuse wire structure |
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2015
- 2015-02-02 CN CN201510054213.7A patent/CN105990173B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5326428A (en) * | 1993-09-03 | 1994-07-05 | Micron Semiconductor, Inc. | Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability |
| JPH07297326A (en) * | 1994-04-20 | 1995-11-10 | Hitachi Ltd | Socket for testing semiconductor chip |
| CN102299094A (en) * | 2010-06-24 | 2011-12-28 | 无锡华润上华半导体有限公司 | manufacturing method of fuse wire structure |
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