CN108091561B - Uniform layer removing method for aluminum process chip - Google Patents
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- CN108091561B CN108091561B CN201711375704.7A CN201711375704A CN108091561B CN 108091561 B CN108091561 B CN 108091561B CN 201711375704 A CN201711375704 A CN 201711375704A CN 108091561 B CN108091561 B CN 108091561B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
Abstract
The invention discloses a uniform layer removing method for an aluminum process chip, which comprises the following steps: obtaining layer thickness information of the chip, wherein the layer thickness information comprises the thickness of a metal wiring layer, the thickness of a medium through hole layer and the thickness of a barrier layer; determining first etching time according to the layer thickness information and the etching rate, and etching a first barrier layer in a preset etching gas, wherein the first barrier layer is a barrier layer positioned on the outer surface side of the metal wiring layer; removing the metal wiring layer by using a rubber; and etching a second barrier layer in the etching gas, wherein the second barrier layer is a barrier layer positioned on the inner surface side of the metal wiring layer. The method takes the eraser as a tool for grinding the metal wiring layer, can selectively etch aluminum, and avoids the via phenomenon and the edge effect.
Description
Technical Field
The invention relates to the technical field of chip failure analysis, in particular to a uniform layer removing method for an aluminum process chip.
Background
The chip is composed of a multi-layer metal wiring structure and a dielectric via layer structure, and the metal wiring layer is a three-layer structure as shown in fig. 1, where M1-M6 respectively represent six layers, M1 is the first layer closest to the machine layer, and so on. When the chip is failed internally, the chip is required to be layered layer by layer to analyze failure reasons; when the chip circuit detail analysis is carried out, the chip is required to be removed layer by layer to observe the internal structure of the chip. The step of chip delaminating is to remove the metal layer of the chip and the dielectric via layer (or passivation layer) on the metal layer flatly, the flatness of the failure area needs to be ensured in the failure analysis field, and the flatness of the whole chip needs to be ensured in the chip circuit detail analysis field.
The prior art is divided into two major directions: the Etching, grinding and polishing method is mainly applied to the field of failure analysis, and comprises the steps of Etching a medium through hole layer (or a passivation layer) through RIE (Reactive Ion Etching), and grinding a metal layer and a barrier layer (titanium Ti) in a CMP (Chemical Mechanical polishing) mode until the whole layer is ground; the method has the characteristics that the edge effect is very heavy, the chip surface is easy to be staggered (the chip surface is not the same metal layer), and other factors influencing the chip state are not introduced. The etching corrosion grinding and polishing method is mainly applied to the field of circuit detail analysis, a dielectric through hole layer (or a passivation layer) is etched through RIE, an aluminum layer is reacted by using acid liquor or alkali liquor, and then a barrier layer is ground in a CMP mode until the whole layer is ground; in the method, all analyzed chips are qualified, and only the internal information of the chips needs to be reserved, so that chemical substances such as acid and alkali are introduced only to have no influence on the detailed circuit analysis of the chips. The method has the characteristics that the degree of the edge effect depends on the capability of an engineer, great uncertainty exists, and meanwhile, the hole falling (through hole corrosion) is easily caused during the acid-base reaction, so that the detailed analysis of a chip circuit is influenced.
In the process of implementing the invention, the inventor finds that at least the following problems exist in the prior art:
the main problem of the etching grinding and polishing method is the problem of staggered layers caused by the overweight edge effect, and because the edge grinding and polishing speed is always higher than the middle grinding and polishing speed in the CMP grinding and polishing process, the metal layer to be ground is thicker and the barrier layer is more wear-resistant, the edge metal layer is at a lower level because the grinding and polishing speed of the edge is far higher than that of the middle metal in the layer removing process, namely, the staggered layers are generated. Long-term experiments prove that almost every two layers of metal are ground, so that the edge metal layer and the middle metal layer are different by one layer. If two failure points with large distance exist on the chip, the method has great disadvantages.
The main problems of the etching corrosion polishing method are that the hole dropping problem and the edge effect problem are easily caused. The problem of hole dropping is that when the aluminum layer is reacted by using acid liquor or alkali liquor, for example, the concentration, temperature and reaction time of the acid-alkali liquor are controlled improperly, the through hole is easy to be corroded, namely, the hole dropping is easy to occur. The hole dropping can cause that an engineer can not effectively judge the connection relation between the metal wires when the circuit is extracted, and the function judgment of the circuit is influenced. The problem of edge effect is that in the process of polishing a barrier layer by using CMP, the polishing speed of the edge is always greater than the polishing speed of the middle part, so that the phenomenon of layer-by-layer transmission can be caused in the process of removing the layer, when the layer is accumulated to a certain degree, a dielectric layer on an edge metal layer is much thinner than that of a middle metal layer of a chip, and edge holes are easily removed or even staggered. Because circuit detail analysis requires a very complete layer-shaping effect, polishing is greatly influenced by the experience of engineers, and the controllability is low.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a uniform layer removing method for an aluminum process chip, thereby overcoming the existing defects.
The embodiment of the invention provides a uniform layer removing method for an aluminum process chip, which comprises the following steps: obtaining layer thickness information of the chip, wherein the layer thickness information comprises the thickness of a metal wiring layer, the thickness of a medium through hole layer and the thickness of a barrier layer; determining first etching time according to the layer thickness information and the etching rate, and etching a first barrier layer in preset etching gas, wherein the first barrier layer is a barrier layer positioned on the outer surface side of the metal wiring layer; grinding the metal wiring layer by using a rubber; and etching a second barrier layer in the etching gas, wherein the second barrier layer is positioned on the inner surface side of the metal wiring layer.
In one possible implementation, the etching gas includes CF4、CHF3And O2The mixed gas of (1).
In one possible implementation, the CF4、CHF3And O2The volume ratio of (1) to (20-60) to (10-30) to (20).
In a possible implementation manner, the first etching time is:
wherein the content of the first and second substances,
v1rate of etching of dielectric via layer, v2Rate of etching of the barrier layer, d1Is the thickness of the dielectric via layer, d2Is the thickness of the first barrier layer, d3Thickness of the metal wiring layer, d4Is the second barrier thickness.
In one possible implementation, λ is 1.5.
In one possible implementation, the etching the second barrier layer in the etching gas includes:
etching a second barrier layer in the etching gas, wherein the etching time is a second etching time:
according to the uniform layer removing method for the aluminum process chip, which is provided by the embodiment of the invention, the rubber is used as a tool for grinding the metal wiring layer, aluminum can be selectively etched, and silicon dioxide and other materials are prevented from being ground and polished, so that the edge effect caused by grinding of grinding fluid or other substances such as a grinding plate in an etching grinding and polishing method is overcome, and the phenomenon that holes are easily formed in a solution in the etching grinding and polishing method can be avoided. The barrier layer is removed by adopting an etching method, so that the problem that the edge hole is easily ground or even staggered when the titanium or titanium nitride is removed by a CMP method in the etching corrosion grinding and polishing process is solved, and the edge effect can be effectively avoided. And calculating the etching time so as to ensure the etching consistency. The etching gas can ensure that the titanium or the titanium nitride is completely etched, and the etching rate of the silicon dioxide is in an acceptable range.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a chip structure of a multi-layer metal wiring structure in the prior art;
FIG. 2 is a flow chart of a uniform de-layering method for aluminum process chips in an embodiment of the present invention;
FIG. 3 is a diagram illustrating obtaining layer thickness information according to an embodiment of the present invention;
FIG. 4 is another schematic diagram of obtaining layer thickness information in an embodiment of the present invention;
FIG. 5 is a diagram illustrating a chip after etching away the first barrier layer according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a chip after a metal wiring layer is removed according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating the second barrier layer etched away in an embodiment of the invention;
FIG. 8 is a schematic diagram illustrating an effect of removing a layer and then preparing a metal layer according to an embodiment of the present invention;
FIG. 9 is a diagram illustrating the effect of de-layering on polycrystalline layer preparation according to an embodiment of the present invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, methods, means, elements well known to those skilled in the art have not been described in detail so as not to obscure the present invention.
According to an embodiment of the present invention, a method for uniform delamination of an aluminum process chip is provided, and fig. 1 is a flowchart of the method, which specifically includes steps 101-104:
step 101: and acquiring the layer thickness information of the chip, wherein the layer thickness information comprises the thickness of the metal wiring layer, the thickness of the dielectric through hole layer and the thickness of the barrier layer.
In the embodiment of the present invention, thickness information of each layer of the chip may be specifically obtained by a FIB (Focused Ion beam) or a longitudinal cutting manner, where the thickness information includes a thickness of a metal wiring layer, a thickness of a dielectric via layer, and a thickness of a blocking layer. Since the barrier layers are disposed on both the upper surface and the lower surface of the metal wiring layer, the thicknesses of the two barrier layers on the upper surface and the lower surface need to be obtained. A schematic diagram of obtaining layer thickness information is shown in fig. 3. FIG. 3 contains a plurality of dielectric via layers and metal wiring layers; the right-hand value 524.1nm is the thickness between 2 layers, i.e., the thickness of one dielectric via layer. The left numerical value of 68.47nm is the thickness of the blocking layer above the metal wiring layer; the other value on the left side is 445.1nm, which is the thickness of the metal wiring layer; the third value on the left side, 65.48nm, is the thickness of the blocking layer under the same metal wiring layer.
Step 102: and determining first etching time according to the layer thickness information and the etching rate, and etching a first barrier layer in a preset etching gas, wherein the first barrier layer is a barrier layer positioned on the outer surface side of the metal wiring layer.
In the embodiment of the present invention, the first blocking layer on the outer surface side (i.e., the upper surface) of the metal wiring layer is removed by Etching, and specifically, an RIE (Reactive Ion Etching) Etching manner may be adopted. Meanwhile, the first etching time needs to be determined according to the layer thickness information and the etching rate, so as to avoid over etching.
Step 103: and removing the metal wiring layer by using a rubber.
In the embodiment of the invention, various types of erasers are used as tools for grinding the metal wiring layer. The eraser has the advantages that Aluminum (AL) is selectively etched; the selective etching of aluminum is due to the fact that aluminum is softer, aluminum is slowly ground off by utilizing the principle of erasing handwriting, and silicon dioxide (SiO) is guaranteed at the same time2Which is the main material of the dielectric via layer) and other materials are not polished, thereby overcoming the edge effect caused by the grinding of other materials such as grinding fluid or grinding plate in the etching polishing method, and avoiding the problem that the solution in the etching polishing method is easy to cause the via-holeThe phenomenon of (2).
Step 104: and etching a second barrier layer in the etching gas, wherein the second barrier layer is a barrier layer positioned on the inner surface side of the metal wiring layer.
In the embodiment of the invention, after the metal wiring layer is ground, the barrier layer on the inner surface side (namely the lower surface) of the metal wiring layer is removed in an etching mode again, the barrier layer is removed by adopting an etching method, titanium or titanium nitride can be completely etched, and the etching rate of silicon dioxide is in an acceptable range. Therefore, the problem that the removal of titanium or titanium nitride by a CMP method in the etching corrosion grinding and polishing process easily causes the grinding and even the layer staggering of the edge hole is solved, and the edge effect can be effectively avoided.
According to the uniform layer removing method for the aluminum process chip, which is provided by the embodiment of the invention, the rubber is used as a tool for grinding the metal wiring layer, aluminum can be selectively etched, and silicon dioxide and other materials are prevented from being ground and polished, so that the edge effect caused by grinding of grinding fluid or other substances such as a grinding plate in an etching grinding and polishing method is overcome, and the phenomenon that holes are easily formed in a solution in the etching grinding and polishing method can be avoided. The barrier layer is removed by adopting an etching method, so that the problem that the edge hole is easily ground or even staggered when the titanium or titanium nitride is removed by a CMP method in the etching corrosion grinding and polishing process is solved, and the edge effect can be effectively avoided.
Optionally, the etching gas comprises CF4、CHF3And O2The mixed gas of (1). Specifically, the composition of the above three gases may be used. Preferably, CF4、CHF3And O2The volume ratio of (1) to (20-60) to (10-30) to (20). The etching gas can ensure that the titanium or the titanium nitride is completely etched, and the etching rate of the silicon dioxide is in an acceptable range.
The flow of the method is described in detail below by means of an example.
In the embodiment of the invention, the thickness information of each layer of the chip is acquired by an FIB (Focused Ion beam) or a longitudinal cutting mode, and the thickness information comprises the thickness of a metal wiring layer, the thickness of a medium through hole and the thickness of a blocking layer. A schematic diagram of obtaining layer thickness information is shown in fig. 4.
As shown in FIG. 4, the outermost borders are all represented by SiO2The dielectric via region is formed, and when the delaminating method is executed, only the thickness of a part of the dielectric via layer needs to be calculated, namely d in fig. 11. AL in fig. 4 denotes a metal wiring layer, and the upper and lower two layers denote a first barrier layer and a second barrier layer, respectively; in FIG. 4, d2Is the thickness of the first barrier layer, d3Thickness of the metal wiring layer, d4Is the second barrier thickness.
And then calculating the etching time of the dielectric layer, namely the first etching time, etching the first barrier layer in the etching gas until the first barrier layer is near the lower surface of the chip metal wiring layer, and reserving a dielectric through hole layer which is multiplied by lambda for playing a buffering role when etching the second barrier layer. The schematic diagram of the etched chip is shown in fig. 5.
In an embodiment of the invention, the etching gas comprises CF4、CHF3And O2And the volume ratio of the three components is (20-60): 10-30): 20. Meanwhile, in order to make the finally etched chip more flat, the first etching time is as follows:
After the first barrier layer is etched away, the aluminum metal (i.e., the metal wiring layer) is erased by using a rubber, and the aluminum metal is cleaned. A schematic of the chip after aluminum removal is shown in fig. 6.
Then etching in the etching gas again to etch off the second barrier layer for t2：
The schematic diagram after etching away the second barrier layer is shown in fig. 7.
In the embodiment of the invention, the dielectric through hole layer with the thickness being multiplied by lambda is reserved during the first etching, so that the second barrier layer and the dielectric through hole layer after the second etching are positioned on the same plane, the etching consistency can be ensured, and the smooth chip layer removing effect can be obtained. In the embodiment of the present invention, after the delamination operation is performed, the effect images observed under an SEM (scanning electron microscope) are shown in fig. 8 and 9.
According to the uniform layer removing method for the aluminum process chip, which is provided by the embodiment of the invention, the rubber is used as a tool for grinding the metal wiring layer, aluminum can be selectively etched, and silicon dioxide and other materials are prevented from being ground and polished, so that the edge effect caused by grinding of grinding fluid or other substances such as a grinding plate in an etching grinding and polishing method is overcome, and the phenomenon that holes are easily formed in a solution in the etching grinding and polishing method can be avoided. The barrier layer is removed by adopting an etching method, so that the problem that the edge hole is easily ground or even staggered when the titanium or titanium nitride is removed by a CMP method in the etching corrosion grinding and polishing process is solved, and the edge effect can be effectively avoided. The etching gas can ensure that the titanium or the titanium nitride is completely etched, and the etching rate of the silicon dioxide is in an acceptable range.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (5)
1. A uniform layer removing method for an aluminum process chip, wherein a certain layer structure of the aluminum process chip comprises a metal wiring layer, a first barrier layer positioned on the outer surface of the metal wiring layer, a second barrier layer positioned on the inner surface of the metal wiring layer and a medium through hole layer surrounding the first barrier layer, the metal wiring layer and the second barrier layer, and the metal wiring layer is made of aluminum, and the uniform layer removing method comprises the following steps:
acquiring thickness information of the metal wiring layer, thickness information of the first barrier layer, thickness information of the second barrier layer and thickness information of a dielectric through hole layer on the surface of the first barrier layer;
determining a first etching time t according to a first calculation formula1And at the first etching time t1Etching the dielectric via layer and the first barrier layer with a preset etching gas, wherein the first barrier layer is formed by etchingThe calculation formula is as follows:
grinding the metal wiring layer by using a rubber;
and etching away the second barrier layer by using the etching gas.
2. The method of claim 1, wherein the etching gas comprises CF4、CHF3And O2The mixed gas of (1).
3. The method of claim 2, wherein the CF is4、CHF3And O2The volume ratio of (1) to (20-60) to (10-30) to (20).
4. The method of claim 1, wherein λ ═ 1.5.
5. The method of claim 1, wherein the etching away the second barrier layer with the etching gas comprises:
determining a second etching time t according to a second calculation formula2And at the second etching time t2Etching off the second barrier layer by using the etching gas, wherein the second calculation formula is
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| TW501212B (en) * | 2000-11-14 | 2002-09-01 | Vanguard Int Semiconduct Corp | Failure analysis method of metal delayer |
| CN102253325A (en) * | 2010-05-21 | 2011-11-23 | 中芯国际集成电路制造(上海)有限公司 | Method for analyzing chip failure |
| CN103499476A (en) * | 2013-09-30 | 2014-01-08 | 上海华力微电子有限公司 | Method for removing layers in chip failure analysis process |
| CN104020408A (en) * | 2014-05-26 | 2014-09-03 | 武汉新芯集成电路制造有限公司 | Memory chip bit line failure analyzing method |
| CN104241156A (en) * | 2014-08-21 | 2014-12-24 | 武汉新芯集成电路制造有限公司 | Method for analyzing defects |
| CN105047557A (en) * | 2015-09-10 | 2015-11-11 | 宜特(上海)检测技术有限公司 | High-order chip failure physical de-layering analysis method |
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