1274392 18022twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體電路的分析方法，且特別是 有關於一種可以避免窗廉效應的積體電路分析方法。 【先前技術】 在半導體產業中，各種分析儀器大量被應用於產品開 發、製程監控及故障分析等。當設計規格縮小時，要改盖 、及維持半導體製程良率更加_，而缺陷為影響制 程良率中最為重要的_。因此，缺關鑑定分析以^ 低，對於積體電路製造良率的提升有重大的關係。 智知為了檢測半導體元件中的缺陷，而採用聚焦離子 束顯微鏡的技術，以蝕刻之方式依序移除半導體元件上 各層’並依賴各層作分析。亦即，在進行半 缺陷檢測時’自上層開始依其順序逐層往下進聽^ 程，使有缺陷處之下層逐一分層露出，並對 _ = 分析，直難槪最下g。 ％仃硯察 然而，上述的分析技術會因試片結構上的 穿随現象，—般稱之為窗簾效應(c她in Effect)。以動能t1274392 18022twf.doc/g IX. Description of the Invention: [Technical Field] The present invention relates to an analysis method of an integrated circuit, and more particularly to an integrated circuit analysis method capable of avoiding a window effect. [Prior Art] In the semiconductor industry, various analytical instruments are widely used in product development, process monitoring, and failure analysis. When the design specifications shrink, it is necessary to change the coverage and maintain the semiconductor process yield, and the defects are the most important factors affecting the process yield. Therefore, the identification analysis of the defect is low, which has a great relationship with the improvement of the manufacturing yield of the integrated circuit. In order to detect defects in the semiconductor device, the technique of focusing ion beam microscopy is used to sequentially remove the layers on the semiconductor device by etching and rely on the layers for analysis. That is to say, when performing the semi-defect detection, the sub-layers are stepped down from the upper layer in order, so that the lower layers of the defective layer are layered one by one, and the _ = analysis is difficult. %仃砚 However, the above analysis technique will be called the curtain effect (c she in Effect) due to the wearing phenomenon of the test piece structure. Kinetic energy
機=子取記健結構μ，此穿隧現象—般發生在電H 觸=〇ntaet)’由於電容和接觸窗的結構具有多數縫 因此聚焦離子束會經由這些縫隙大量㈣至底元杜’ ==率不一致，使得剖面影像如同窗簾般:成 無法硯察及判斷缺陷。 时&成 以下利用圖^从及沈來說明傳統聚焦離子 5 1274392 18022twf.doc/g 束顯微鏡製作動態隨機存 以說明窗簾效庫的現參θ ^心_ 4面樣品的流程， ΓΓ左Ε 士 應的現象。圖1入及1Β所給示Λ开彡#亡氣此 隨機存取記憶體100的^不為形成有動悲 給+盔闰1 Α 7曰片的上視不意圖0圖2Α盥2Β所 ㈣圖Μ及圖1Β中沿剖面❸ ：:2Β所 請苓照圖1Α及圄lLa六匕 〕口]面不思圖。 I02 100 , 、陷位置106即對庳s 2A :思體〇〇的缺陷位f 106。缺 陷108的位置。 中動態隨機存取記憶體⑽的缺 子束ίί子IT圖1B，利用雙粒子束(DualBeam，即離 于束/、屯子束)邊切割邊觀察直 出一開口 110。之德: 的位置，而切割 I，所得到的他0心子束觀察沿® 1B的剖面線卜 在囝川由。圖衫像，此影像的示意圖如圖2B所示。 f圖2B中，由於窗簾效應112嚴重， 實判斷缺陷1G8的影像。 L你C亚確 利解決此問題’習知技術提出一種防治方法。以下 隨機存取記情體說明利用此防治方法製作動態 一 、μ體100的剖面樣品的流程。圖3A與3B所緣 成有動態隨機存取記憶體100的晶片的上視示意 二一 ^及4Β所綠示為圖3Α、3Β中沿剖面線j j，的剖 不二圖。首先，提供如圖1Α及2Α所繪示的晶片。同樣 inn δα用聚焦離子束顯微鏡定位出動態隨機存取記憶體 、缺陷位置106。缺陷位置1〇6即對應圖2A中動態隨 子取心It體1GG的缺陷⑽的位置。 12743¾ 2twf.doc/g 接者’請參照圖3A及圖4A，以手動研磨的方式，將 電容104研磨去除或至電容104的底層。然後，請參照圖 3B及圖4B，利用雙粒子束邊切邊觀察包括缺陷1〇8在内 的範圍的影像，並切割出一開口 200。之後，以電子束沿 圖3B的剖面線I - I，觀察所得到的剖面圖影像，此影像的 示意圖如圖4B所示。在圖4B中，窗簾效應112的情形已 不復見。然而，此防治方法有下列缺點：試片容易研磨過 頭或研磨不足；研磨後試片在聚焦離子束顯微鏡下不易定 位；以及利用聚焦離子束顯微鏡切割試片時，容易損傷試 片的底層。 【發明内容】 本發明的目的就是在提供一種積體電路的分析方 法，以避免窗簾效應。 本發明的另一目的是使試片在聚焦離子束顯微鏡下 容易定位，並避免損傷試片的底層。 本發明提供一種積體電路的分析方法，適用於FIB故 障分析，以避免窗簾效應。此方法包括提供晶片，此晶片 中已形成有數個半導體元件。這些半導體元件中形成有一 個缺陷。接著，定位此缺陷的位置，並於此晶片中形成一 個開口。定位出之缺陷的位置位於此開口中，且此開口具 2一深度。然後，於此開口中填入均質材料，並切割此均 夤材料，直到此缺陷的位置。之後，觀察此缺陷。 、依照本發明的較佳實施例所述之積體電路的分析方 法，其中於此晶片中形成開口的方法例如是利用聚焦離子 7 1274392 18022twf.doc/g 束(Focus I〇n Beam，FIB)對此晶片進行切割。 依照本發明的較佳實施綱述之㈣電 t割其中切割均f材料的方法例如是利用聚焦離子i進行 依照本發明的較佳實施例所述之積 法’其中觀察此缺陷的方法例如是利用電；束進方 、依照本發明的較佳實施綱述之積體電路° 法，其中均質材料的_速率小於半導 、2斤方 明的較佳實施例所述之積餘= j疋虱化矽，此金屬材料例如是鉑或鎢。 法，佳實施例所述之積體電路的分析方 上述於s H d//70件例如是動紐機存取記紐。此外， μ曰曰片中形成開口的步驟例如是移 取記憶體的部分電容麵分接職(C(fnt=:動4機存 法，關料之频€料分析方 料時損傷均質材料件?避免於切割均質材 法，的較佳實關料之_電路的分析方 開口的長度為5微米，寬度為2微米。 法，其中於的較佳實施例所述之積體電路的分析方 v開口中填入均質材料的方法例如是利用聚 8 1274392 18022twf.doc/g 焦離子束來沈積。 由於本發明利用均質材料來替代蝕刻速率不均的半 導體元件，因此可以有效的避免窗簾效應。此外，由於無 須進行研磨，晶片在聚焦離子束顯微鏡下容易定位；而且 以聚焦離子束進行_來製作試片，可以精確地設定開口 及切割的深度m湘緻密且低侧速率的氧化 石夕、翻或鎢來做為上述的均質材料，可以在聚鱗子束切 割時，避免損傷到試片底層。 為讓本_之上述和其他目的、舰和伽能更明顯 =下下謂舉較佳實關，並配合騎圖式，作詳細說 【實施方式】 ra。ΓΛ以*本發明的紐電路分析料的步驟流程 驟曰5片1=體電路分析方法是先進行步 部分半導^ ^ °此晶片中已形成有數個半導體元件或 已知缺r。二的構件’且於這些半導體元件中形成有-缺陷例：在^半導體元件例如是動態隨機存取記憶體。 配置二置’且其與晶片表面之間還 難。 〜4 +導體構件，因此造成缺陷分析的困 伐者 I2743922twf_d〇c/g 缺陷相對於晶片的座標數值。 然後’進行步驟504 :於晶片中形成開口，且定位出 之缺陷的位置位於開口中，且開口具有一深度。形成開口 的方法例如是以聚焦離子束對此晶片進行切割。 之後’進行步驟506 :於此開口中填入均質材料。例 如是以聚焦離子束來進行沈積。Machine = sub-recording structure μ, this tunneling phenomenon occurs in the electric H-touch = 〇ntaet) 'Because the structure of the capacitor and the contact window has a large number of slits, the focused ion beam will pass through these gaps a lot (four) to the bottom element The == rate is inconsistent, making the profile image look like a curtain: it is impossible to observe and judge defects. Time & use the following figure to illustrate the flow of the conventional focused ion 5 1274392 18022twf.doc/g beam microscope to explain the current θ ^心_ 4 surface sample of the curtain effect library, ΓΓ左Ε The phenomenon of Shi Ying. Figure 1 into the 1Β 给 给 Λ 彡 亡 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机 随机Figure Μ and Figure 1 Β along the section ❸ ::2 Β please refer to Figure 1 Α and 圄lLa 匕 匕 mouth] face does not think. I02 100, the trap position 106 is the defect s 2A: the defect bit f 106 of the body. The location of the defect 108. The missing bundle of the medium dynamic random access memory (10) is shown in Fig. 1B, and an opening 110 is observed by cutting with a double-beam (DualBeam, i.e., from the bundle/, bundle). De: The position, while cutting I, the resulting 0-heart beam is observed along the section line of the 1B in the Chuanchuan. A picture of the figure, a schematic view of the image is shown in Figure 2B. f In Fig. 2B, since the curtain effect 112 is severe, the image of the defective 1G8 is judged. L You C Yali solve this problem. The conventional technology proposes a prevention method. The following random access case describes the flow of the cross-section sample of the dynamic one and the μ body 100 by this control method. 3A and 3B are schematic views of the wafer having the dynamic random access memory 100. The greens are shown in Fig. 3A and Fig. 3, along the section line jj. First, a wafer as shown in FIGS. 1A and 2B is provided. Similarly, inn δα uses a focused ion beam microscope to locate the dynamic random access memory and defect location 106. The defect position 1〇6 corresponds to the position of the defect (10) of the dynamic tangential It body 1GG in Fig. 2A. 127433⁄4 2twf.doc/g Contactor Referring to Figures 3A and 4A, the capacitor 104 is ground or removed to the bottom layer of the capacitor 104 by hand grinding. Then, referring to Fig. 3B and Fig. 4B, the image of the range including the defect 1〇8 is observed by the double particle beam trimming, and an opening 200 is cut. Thereafter, the resulting cross-sectional image is observed by the electron beam along the section line I - I of Fig. 3B, and a schematic view of the image is shown in Fig. 4B. In Fig. 4B, the situation of the curtain effect 112 is no longer seen. However, this control method has the following disadvantages: the test piece is easily over-polished or under-grinded; the test piece is not easily positioned under the focused ion beam microscope after the grinding; and the underlying layer of the test piece is easily damaged when the test piece is cut by the focused ion beam microscope. SUMMARY OF THE INVENTION An object of the present invention is to provide an analysis method of an integrated circuit to avoid a curtain effect. Another object of the present invention is to facilitate the positioning of the test piece under a focused ion beam microscope and to avoid damage to the underlying layer of the test piece. The present invention provides an analytical method for an integrated circuit that is suitable for FIB fault analysis to avoid curtain effects. The method includes providing a wafer in which a plurality of semiconductor elements have been formed. A defect is formed in these semiconductor elements. Next, the location of the defect is located and an opening is formed in the wafer. The location of the located defect is located in this opening, and the opening has a depth of two. Then, a homogenous material is filled in the opening, and the uniform material is cut until the position of the defect. After that, observe this defect. An analysis method of an integrated circuit according to a preferred embodiment of the present invention, wherein the method of forming an opening in the wafer is, for example, using a focused ion 7 1274392 18022 twf.doc/g beam (Focus I〇n Beam, FIB) This wafer was cut. According to a preferred embodiment of the present invention, the method of cutting the material of the f is, for example, performing the method according to the preferred embodiment of the present invention by using the focused ion i. The method for observing the defect is, for example, Using the integrated circuit according to the preferred embodiment of the present invention, wherein the homogeneous material has a _ rate less than the semi-conducting, 2 kg squared embodiment of the preferred embodiment = j疋This metal material is, for example, platinum or tungsten. The analysis method of the integrated circuit described in the preferred embodiment is as described above in the s H d//70. In addition, the step of forming an opening in the μ 曰曰 film is, for example, a partial capacitive surface tapping of the memory (C (fnt=: dynamic 4 machine storage method, the material of the material is damaged when the material is analyzed) Avoiding the method of cutting the homogeneous material method, the length of the analysis opening of the circuit is 5 micrometers and the width is 2 micrometers. The method is the analysis method of the integrated circuit described in the preferred embodiment. The method of filling the opening with a homogeneous material is, for example, deposition using a poly 8 1 274 392 18022 twf.doc/g coke ion beam. Since the present invention utilizes a homogeneous material instead of a semiconductor element having an uneven etching rate, the curtain effect can be effectively avoided. In addition, since it is not necessary to perform grinding, the wafer is easily positioned under a focused ion beam microscope; and by performing a focused ion beam to produce a test piece, it is possible to accurately set the depth of the opening and the cut, and the dense and low-side rate of the oxide oxide. Turning or tungsten as the above homogeneous material can avoid damage to the bottom layer of the test piece when cutting the cluster of the scale. To make the above and other purposes, ship and gamma energy more obvious = lower It is better to turn it on, and to cooperate with the riding pattern, for details. [Embodiment] ra. ΓΛ * * 本 本 本 本 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 = = = = = = = = = = = = = = = = = = ^ ^ ° In this wafer, a plurality of semiconductor elements or components which are known to be missing R. Two are formed and formed in these semiconductor elements - a defect example: the semiconductor element is, for example, a dynamic random access memory. 'And it is difficult to interface with the wafer. ~4 + conductor members, thus causing the defect analysis of the defecter I2743922twf_d〇c / g defects relative to the coordinates of the wafer. Then 'go to step 504: form an opening in the wafer, And the location of the located defect is located in the opening, and the opening has a depth. The method of forming the opening is, for example, cutting the wafer by focusing the ion beam. Then, proceeding to step 506: filling the opening with a homogeneous material. For example, The deposition is performed with a focused ion beam.
、、M之進行步驟508 :切割均質材料，直到缺陷的位 置。其例如是以聚焦離子束來進行切割或蝕刻。.均質材料 的厚度取決於上述開口的深度，此厚度例如是足以抵擋此 切割的步驟。均質材料的材質與開口外的晶片比較，例如 具有較強的抗蝕刻能力。 、^最後，進行步驟510 :觀察缺陷。例如是以電子束來 進行觀察，而完成缺陷的分析。 ,、以下说明將參照圖5的步驟，以圖6A至圖7D來進 行”兒明，且仍以聚焦離子束顯微鏡製作動態隨機存取記憶 =j〇〇剖面樣品試片為例，但不以此為限。圖6A至6D所 =不為形成有動態隨機存取記憶體剛的晶片的上視示意 θ圖7Α至7D所緣示為圖6Α至6D中沿剖面線π - π， 的剖面示意圖。 π >照圖0A與7A，首先，進行步驟5〇〇 ··提供晶片。 德=片中已形成有數個動態隨機存取記憶體削。動態隨 〇子取記憶體100包括閘極結構1G2、電容刚與接觸窗 ―丰且於問極結構102處例如形成有缺陷108。接著，進 乂驟502 ·定位缺陷1〇8的位置。定位缺陷⑽在上視Step 508: M. Cut the homogeneous material until the position of the defect. It is for example cut or etched with a focused ion beam. The thickness of the homogeneous material depends on the depth of the opening described above, which is, for example, a step sufficient to withstand this cutting. The material of the homogeneous material is, for example, more resistant to etching than the wafer outside the opening. Finally, proceed to step 510: Observe the defect. For example, an electron beam is used for observation to complete the analysis of defects. The following description will refer to the steps of FIG. 5, and FIG. 6A to FIG. 7D, and still take the focused ion beam microscope to produce a dynamic random access memory=j〇〇 cross-section sample test piece as an example, but not 6A to 6D = top view of the wafer in which the dynamic random access memory is formed is not shown in Figs. 7A to 7D, and the cross section along the line π - π in Figs. 6A to 6D is shown. π > According to Figures 0A and 7A, first, the step 5 〇〇·· provides the wafer. There are several dynamic random access memory slices formed in the ** chip. The dynamic 〇 取 memory 100 includes the gate The structure 1G2, the capacitor is just in contact with the contact window, and a defect 108 is formed, for example, at the interrogation structure 102. Next, the step 502 is performed to locate the position of the defect 1〇8. The positioning defect (10) is in the upper view.
1274392 18022twf.doc/g 圖中相應的缺陷位置106。 然後，請參照圖6B與圖7B，進行步驟5〇4 :於晶片 中形成一個開口 300。缺陷位置1〇6位於開口 3〇〇中。形 成開口 300的方法例如是利用聚焦離子束對此晶片進行切 割。此外，切割的範圍例如是移除動態隨機存取記情體1〇〇 的部分電容104或部分接觸窗1()5，而於晶片中職開口 300。開口 300的深度D例如是〇.5~〇 8微米，長度l例如 是5微米，寬度W例如是2微米。 P近後，请參照圖6C與7C，進行步驟5〇6，於此開口 300中填入均質材料3〇2。均質材料3〇2例如是介電材料或 金屬材料。介電材料例如是氧切，金屬材料例如是始或 鶴。於開口 300中填入均質材料3〇2的方1274392 18022twf.doc/g Corresponding defect location 106 in the figure. Then, referring to Figures 6B and 7B, step 5〇4 is performed: an opening 300 is formed in the wafer. The defect position 1〇6 is located in the opening 3〇〇. The method of forming the opening 300 is, for example, cutting the wafer using a focused ion beam. Further, the range of the cutting is, for example, removal of the partial capacitance 104 or the partial contact window 1 () 5 of the dynamic random access memory 1 ,, and the wafer opening 300 in the wafer. The depth D of the opening 300 is, for example, 〇5 to 〇 8 μm, the length l is, for example, 5 μm, and the width W is, for example, 2 μm. After P is near, referring to Figs. 6C and 7C, step 5〇6 is performed, and the opening 300 is filled with the homogeneous material 3〇2. The homogeneous material 3〇2 is, for example, a dielectric material or a metal material. The dielectric material is, for example, oxygen cut, and the metal material is, for example, a crane or a crane. Filling the opening 300 with a square of 3〇2 of homogeneous material
焦離子束來沈積。 . K 繼之，請參照圖6D，進行步驟5〇8 :切割均質材 302’直到缺陷刚的位置。切割均質材料搬时法例如 是利用聚焦離子束進行切#卜其例如是以㈣的方式來切 割均質材料搬’而於均質材料迎中形成開口 3(η。 所沈積的均質材料302的厚度必須足夠’以避免於心 質材料302時損傷均質材料3〇2以下的動態隨機存取^ 體爾。此厚度是由開口 3〇〇的深度來決定。此外，均^ 材料搬的㈣速率必須小於動態隨機存 二 電容104或接觸窗105的蝕刻速率。 00的 之後，請參照圖6〇與7〇，進行 1〇8,而得到圖7D的剖面圖影像。圖7〇是沿剖面^ 1274392 18022twf.doc/g Π’觀察而得到的剖面圖影像。其中觀察缺陷1〇8的方 如是利用電子束來進行觀察。 综上所述，由於本發明利用均質材料來替代蝕刻速率 不均的半導體元件，因此可以有效的避免窗簾效應。此外， 因為晶片無須經過任何研磨製程，所以晶片表面大部分結 構未被破壞，在聚焦離子束顯微鏡下容易定位；而且以: 進:切，乍試片’可以精確地設定開口及: 的冰度。另一方面，利用緻密且低蝕刻速率的 ，或鶴來做為上述的均質材料，可以在聚焦離子束切割 守，避免損傷到試片底層。 ° 雖然本發明已以較佳實施例揭露如 限定本發明，任何熟習此技藝者，在;;=非用以 和範圍内，當可作些許之更齡不脫縣發明之精神 範圍當視後附之申請專利範圍所ς者=本發明之保護 【圖式簡單說明】 考為丰。 圖1Α及1Β所繪示為形成 的晶片的上視示意圖。 動久、奴機存取記憶體1〇〇 圖2Α與2Β所繪示為圖u I ’的剖面示意圖。 回B中沿剖面線I - 圖3A與3B所繪示為形成 的晶片的上視示意圖。 動怨蛟機存取記憶體100 圖4A及4B所緣示為圖3a、 剖面示意圖。 3B中沿剖面線卜I，的 程 圖5是㈣本卿的_料分㈣法的步驟流 1274392 18022twf.doc/g 圖。 圖6A至6D所繪示為形成有動態隨機存取記憶體100 的晶片的上視不意圖。 圖7A至7D所繪示為圖6A至6D中沿剖面線Π-Π’ 的剖面示意圖。 【主要元件符號說明】 100 :動態隨機存取記憶體 102:閘極結構 W 104 ··電容 105··接觸窗 106 :缺陷位置 108 :缺陷 110、200、300、304 :開口 112 :窗簾效應 302 :均質材料 L :長度 • W :寬度 D :深度 500〜510 :步驟 • I - I ’、Π-Π，：剖面線 13A focal ion beam is deposited. K Next, referring to Fig. 6D, proceed to step 5〇8: cutting the homogeneous material 302' until the defect is just positioned. The cutting homogeneous material moving time method is, for example, performing a cutting by using a focused ion beam, for example, cutting the homogeneous material in the manner of (4) and forming an opening 3 (n in the homogeneous material). The thickness of the deposited homogeneous material 302 must be Sufficient 'to avoid damage to the homogeneous material of the core material 302 when the dynamic material is below 3 〇 2 dynamic random access. This thickness is determined by the depth of the opening 3 。. In addition, the rate of material transfer (four) must be less than The etch rate of the dynamic random access capacitor 104 or the contact window 105. After 00, please refer to FIGS. 6A and 7B, and perform 1〇8 to obtain the cross-sectional image of FIG. 7D. FIG. 7〇 is along the section ^1274392 18022twf .doc/g Π 'observed cross-sectional image. The side where the defect 1 观察 8 is observed is observed by electron beam. In summary, the present invention utilizes a homogeneous material instead of a semiconductor element having an uneven etching rate. Therefore, the curtain effect can be effectively avoided. In addition, since the wafer does not have to undergo any polishing process, most of the structure of the wafer surface is not destroyed, and it is easy to set under the focused ion beam microscope. And; to: cut: 乍 test piece 'can accurately set the opening and: the ice. On the other hand, using dense and low etch rate, or crane as the above homogeneous material, can focus on the ion The beam is cut to avoid damage to the bottom layer of the test piece. ° Although the present invention has been disclosed in the preferred embodiments, as defined by the skilled artisan, any skilled person in the art can make a little more The scope of the invention is based on the scope of the patent application. The protection of the present invention [the simple description of the drawings] is abundance. Figure 1 and Figure 1 are schematic views of the wafer formed. Figure 2Α and 2Β are shown as a cross-sectional view of Figure u I '. Back to B along section line I - Figures 3A and 3B are shown as the top view of the formed wafer Figure 4A and 4B are shown in Figure 3a, a schematic cross-sectional view. 3B along the section line I, the process of Figure 5 is (4) Ben Qing's _ material division (four) method flow 1274392 18022twf.doc/g Figure 6A to 6D are shown with dynamic random access memory The upper view of the wafer of the memory 100 is not intended. Figures 7A to 7D are schematic cross-sectional views along the line Π-Π' in Figs. 6A to 6D. [Main element symbol description] 100: Dynamic random access memory 102 : gate structure W 104 · capacitor 105 · contact window 106 : defect location 108 : defect 110 , 200 , 300 , 304 : opening 112 : curtain effect 302 : homogeneous material L : length • W : width D : depth 500 ~ 510: Steps • I - I ', Π-Π,: section line 13