501212 A7 B7 6518twf.doc/〇〇6 五、發明說明（/ ) 本發明是有關於一種多層金屬內連線積體電路的故 障分析方法，且特別是有關於故障分析時，多層金屬內連 線積體電路之金屬回剝的方法。 在VLSI元件的故障分析中，各層次的回剝（Ddayer) 是一種不可避免的過程，以往不論是利用濕蝕刻或是乾蝕 刻的方法來蝕刻上層元件時，會有部份蝕刻劑經由殘留於 兀件中的介層(Via)空隙滲透到待測試之下層元件，而造成 下層元件的損傷，導致試片的損毀，且得不到正確的結果。 特別在進行金屬回剝時，不論利用何種蝕刻方法來 剝除上層金屬，必定會有部份蝕刻劑經由殘留於元件中的 介層空隙滲透到下層金屬，而造成下層金屬的損傷，導致 試片的損毀，且無法得到正確之金屬測試結果。 第1A圖至第1C圖繪示習知一種回剝金屬的故障分 析方法。請參照第1A圖，利用傳統金屬內連線製程製作 雙層金屬內連線，其中，第二金屬層13、介電層12與第 一金屬層11之間分別形成阻障層14、15、16,且在雙層 金屬內連線的製程中產生介層空隙17。 接著，請參照第1B圖，利用蝕刻技術剝除第二金 屬層13，當蝕刻完成時，因蝕刻時間過長，導致蝕刻劑移 除部份在介層空隙17下之阻障層15與第一金屬層11。 接著，請參照第1C圖，以蝕刻法剝除介電層12與 阻障層14，再對第一金屬層11與阻障層15、16進行故障 分析。因剝除第二金屬層13的過程中第一金屬層11已受 到損傷，而無法對第一金屬層11進行正確的分析。 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ·丨I _ I丨—訂·丨丨丨I丨丨— - (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 501212 6518twf. doc/006 A7 B7 五、發明說明（乙） 在上述的方法中，因上層金屬剝除時間過長，導致 部份蝕刻劑經由介層孔洞而損傷下層金屬，並使故障分析 之結果發生誤差，這個誤差會導致故障排除的困難。 本發明係提出一種回剝金屬的故障分析方法，在回 剝金屬時，可在不傷及下層金屬的情況下完成待測試之切 片，並避免在故障分析時發生錯誤結果。 本發明提出一種回剝金屬的故障分析方法，提供具 有第一金屬層、介電層、第二金屬層、阻障層與一介層孔 洞之多層金屬內連線積體電路，利用FIB移除在積體電路 之介層區域的第二金屬層，使介層的封口打開。之後，在 打開封口的介層孔洞上，利用FIB將氧化物塡充至介層孔 洞一半以上的區域中。接著，分別使用鹽酸/過氧化氫比爲 1 : 1之蝕刻液與硫酸/過氧化氫比爲1 : 1之蝕刻液移除第 二金屬層與阻絕層。最後，移除介電層，至第一金屬層露 出爲止。 本發明藉著塡充氧化物以保護在介層孔洞下方之第 一金屬層，可在移除第二金屬層的同時，避免對第一金屬 層造成損傷，並避免在故障分析時發生錯誤。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作 詳細說明如下： 圖式之簡里說明 第1A圖至第1C圖繪示習知的一種回剝金屬的故障 分析方法。 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） MB a··· am a·· · I ·ι···ι I ι (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 501212 A7 種依照本發明一較佳實施例 6518twf.doc/006 五、發明說明（多） 第2圖至第7圖繪示 的回剝金屬的故障分析方法 _式之標ιΒ說明_ 11，21 :第一金屬層 12 ’ 22 :介電層 13 ’ 23 :第二金屬層 14M5M6’24’25’26:阻障層 17 ’ 27 :介層空隙 28 :開口 29 :塡充層 實施例 第2圖至第7圖繪示一種依照本發明一較佳實施例 的一種回剝金屬的故障分析方法。首先，請參照第2圖所 示’其繪示-種依照本發明—較佳實施例之待分析元件剖 面圖。供多層金屬內連線積體電路，其結構由下至上至 少包括第一金屬層21、介電層(IMD)22、第二金屬層23與 阻絕層24、25、26，且在第一金屬層21與第二金屬層23 之間有介層孔洞27之存在。其中第一金屬層包括鋁銅矽 合金（AlSiCu)，第二金屬層包括鋁銅矽合金，介電層包括 二氧化矽（Si02)，阻絕層包括氮化鈦(TiN)。 接著，請參照第3圖所示，利用聚焦離子束(focused ion beam ’ FIB)移除上述多層金屬內連線積體電路中介層 孔洞27區域上的第二金屬層23，以打開介層孔洞27之封 口，形成開口 28。例如：利用聚焦離子束移除介層孔洞區 5 β裝丨丨—丨！丨訂· - - ！丨丨-. (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 501212 A7 B7 6518twf. doc/006 五、發明說明（¥ ) 域上之第二層鋁銅矽合金，以打開封口形成開口 28。 接著，請參照第4圖所示，利用聚焦離子束形成塡 充層29於開口 28中，塡充層29之高度至少爲開口 28高 度之50%以上，以保護第一金屬層21上之阻障層25，其 中塡充層29包括二氧化矽。 接著，請參照第5圖所示，利用蝕刻法，移除前述 之半導體元件之第二金屬層23。例如：利用濕蝕刻法，使 用配方爲鹽酸：過氧化氫=1 : 1(HCL:H202=1:1)之蝕刻劑， 浸泡2·5分鐘左右，以完全移除第二層金屬層。 接著，請參照第6圖所示，利用蝕刻法，移除前述 之半導體元件之阻障層24。例如：利用濕蝕刻法，使用配 方爲硫酸：過氧化氫=1 : 1(H2S04:H202=1:1)之蝕刻劑，浸 泡1分鐘左右，以完全移除介電層上的阻障層。 接著，請參照第7圖所示，利用乾蝕刻法，例如以 反應性離子蝕刻法（Reactive Ion Etching，RIE)，完全移除 介電層22與塡充層29，並暴露第一金屬層21，完成待分 析試片之製備。 綜觀以上所述，與習知的故障分析上之金屬回剝相 比較，本發明至少具有下列優點： 一、本發明在移除第二金屬層23與阻障層24時， 原介層孔洞27已塡充二氧化矽層29,因此所使用之蝕刻 劑並不會滲透至第一金屬層21，當蝕刻完畢後，第一金屬 層21依然毫髮無傷。 一、本發明之分析試片進行錯誤分析時，由於試片 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ϋ n n l I i ϋ ϋ 1 ϋ >1 n ϋ ϋ _ϋ I 一吞_ I n n 1 -ϋ 1· 1 ϋ I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 501212 6518twf. doc/006 _B7_ 五、發明說明（f ) 之金屬層比較完整，因此能得到較爲正確的結果，並增加 分析速度。 需要注意的是，雖然上文中係針對二層金屬之回剝 情形加以說明，但本發明並不限制於使用二層金屬之回 剝，而是可適用於一般多層金屬內連線積體電路之金屬回 剝（Metal Delayer) 〇 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作各種之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 -----------^ ---—----^0-------- (請先閱讀背面之注音3事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）501212 A7 B7 6518twf.doc / 〇〇6 V. Description of the invention (/) The present invention relates to a method for fault analysis of a multilayer metal interconnected integrated circuit, and particularly relates to a multilayer metal interconnected during fault analysis. Method for metal stripping of integrated circuits. In the failure analysis of VLSI components, peelback at various levels (Ddayer) is an unavoidable process. In the past, when wet or dry etching was used to etch the upper layer components, some of the etchant remained through The interstitial (Via) voids in the element penetrate into the lower layer components to be tested, causing damage to the lower layer components, leading to the destruction of the test piece, and no correct results can be obtained. Especially when performing metal stripping, no matter which etching method is used to strip the upper metal, some of the etchant must penetrate into the lower metal through the interstitial space remaining in the element, causing damage to the lower metal, resulting in The sheet was damaged and the correct metal test result could not be obtained. Figures 1A to 1C show a conventional fault analysis method for stripping metal. Referring to FIG. 1A, a double-layer metal interconnect is manufactured using a conventional metal interconnect process, wherein barrier layers 14, 15, and 2 are formed between the second metal layer 13, the dielectric layer 12, and the first metal layer 11, respectively. 16, and interlayer voids 17 are generated in the process of double-layer metal interconnections. Next, referring to FIG. 1B, the second metal layer 13 is stripped by using an etching technique. When the etching is completed, the etching layer has a barrier layer 15 and a first barrier layer 15 under the interlayer gap 17 due to the long etching time.一 金属 层 11。 A metal layer 11. Next, referring to FIG. 1C, the dielectric layer 12 and the barrier layer 14 are stripped by etching, and then the first metal layer 11 and the barrier layers 15 and 16 are analyzed for failure. Because the first metal layer 11 has been damaged during the process of stripping the second metal layer 13, the first metal layer 11 cannot be correctly analyzed. 3 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) · 丨 _ I 丨 —Order · 丨 丨 I 丨 丨 —-(Please read the note on the back? Matters before filling out this page ) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 501212 6518twf. Doc / 006 A7 B7 V. Description of the Invention (B) In the above method, because the upper metal stripping time is too long, part of the etchant passes through the interlayer holes Damage to the underlying metal and errors in the results of the fault analysis will cause difficulties in troubleshooting. The invention proposes a failure analysis method for peeling back metal. When peeling back the metal, the slice to be tested can be completed without harming the underlying metal, and erroneous results can be avoided during failure analysis. The invention provides a failure analysis method for peel-back metal, which provides a multilayer metal interconnection circuit with a first metal layer, a dielectric layer, a second metal layer, a barrier layer, and a via hole. The second metal layer in the interposer region of the integrated circuit opens the seal of the interposer. After that, on the opened via hole, FIB is used to fill the oxide hole to more than half of the via hole. Then, an etching solution having a hydrochloric acid / hydrogen peroxide ratio of 1: 1 and an etching solution having a sulfuric acid / hydrogen peroxide ratio of 1: 1 are respectively used to remove the second metal layer and the barrier layer. Finally, the dielectric layer is removed until the first metal layer is exposed. The present invention protects the first metal layer under the hole of the interlayer via the hafnium oxide, which can remove the second metal layer while avoiding damage to the first metal layer, and avoid errors during fault analysis. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Brief description of the drawings illustrates FIG. 1A Fig. 1 to Fig. 1C show a conventional failure analysis method of peeling metal. 4 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public love) MB a ··· am a ·· · I · ι ··· ι I ι (Please read the precautions on the back before filling in this Page) 501212 A7 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs according to a preferred embodiment of the present invention 6518twf.doc / 006 V. Description of the invention (multiple) The failure of the peeling metal shown in Figures 2-7 Analytical method_Explanation of formula_11, 21: First metal layer 12 '22: Dielectric layer 13' 23: Second metal layer 14M5M6'24'25'26: Barrier layer 17 '27: Interlayer gap 28: Opening 29: Example of rhenium filling layer FIG. 2 to FIG. 7 illustrate a failure analysis method of a peel-back metal according to a preferred embodiment of the present invention. First, please refer to FIG. 2 ', which shows a cross-sectional view of a component to be analyzed according to a preferred embodiment of the present invention. A multilayer integrated circuit for metal interconnects, the structure of which includes at least a first metal layer 21, a dielectric layer (IMD) 22, a second metal layer 23, and a barrier layer 24, 25, 26 from bottom to top. Interlayer holes 27 exist between the layer 21 and the second metal layer 23. The first metal layer includes aluminum-copper-silicon alloy (AlSiCu), the second metal layer includes aluminum-copper-silicon alloy, the dielectric layer includes silicon dioxide (SiO2), and the barrier layer includes titanium nitride (TiN). Next, referring to FIG. 3, a focused ion beam (FIB) is used to remove the second metal layer 23 on the interlayer hole 27 area of the multilayer metal interconnect interconnect integrated circuit to open the interlayer hole. Sealed at 27 to form an opening 28. For example: using a focused ion beam to remove the interstitial hole area 5 β equipment 丨 丨 —— 丨!丨 Order ·--!丨 丨-. (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives This paper is printed in accordance with China National Standard (CNS) A4 (210 X 297 mm) 501212 A7 B7 6518twf doc / 006 5. The second layer of aluminum-copper-silicon alloy on the description of the invention (¥), to open the seal to form the opening 28. Next, referring to FIG. 4, a pseudo-filled layer 29 is formed in the opening 28 by using a focused ion beam. The height of the pseudo-filled layer 29 is at least 50% of the height of the opening 28 to protect the resistance on the first metal layer 21. The barrier layer 25, wherein the pseudo-filling layer 29 includes silicon dioxide. Next, referring to FIG. 5, the second metal layer 23 of the aforementioned semiconductor element is removed by an etching method. For example, the wet etching method is used, and the etchant is hydrochloric acid: hydrogen peroxide = 1: 1 (HCL: H202 = 1: 1). Soak for about 2.5 minutes to completely remove the second metal layer. Next, referring to FIG. 6, the above-mentioned barrier layer 24 of the semiconductor device is removed by an etching method. For example, the wet etching method is used, and the etchant with sulfuric acid: hydrogen peroxide = 1: 1 (H2S04: H202 = 1: 1) is immersed for about 1 minute to completely remove the barrier layer on the dielectric layer. Next, referring to FIG. 7, the dry etching method, such as Reactive Ion Etching (RIE), is used to completely remove the dielectric layer 22 and the filling layer 29 and expose the first metal layer 21. To complete the preparation of the test piece to be analyzed. In summary, compared with the conventional metal stripping on fault analysis, the present invention has at least the following advantages: 1. When the second metal layer 23 and the barrier layer 24 are removed, the original via hole 27 The silicon dioxide layer 29 has been filled, so the used etchant will not penetrate the first metal layer 21, and after the etching is completed, the first metal layer 21 is still intact. I. The error analysis of the analysis test strip of the present invention, because the test paper 6 paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) ϋ nnl I i ϋ ϋ 1 ϋ > 1 n ϋ ϋ _ϋ I 一 吞 _ I nn 1 -ϋ 1 · 1 ϋ I (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 501212 6518twf. doc / 006 _B7_ V. Description of the invention ( f) The metal layer is relatively complete, so it can get more correct results and increase the analysis speed. It should be noted that although the above description is made on the peeling of the two-layer metal, the present invention is not limited to the use of the peel-back of the two-layer metal, but can be applied to the general multilayer metal interconnect wiring integrated circuit. Metal Delayer 〇 Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art can make it without departing from the spirit and scope of the present invention. Various changes and modifications, so the protection scope of the present invention shall be determined by the scope of the appended patent application. ----------- ^ --------- ^ 0 -------- (Please read the note 3 on the back before filling out this page) Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by Consumer Cooperatives 7 This paper is sized for China National Standard (CNS) A4 (210 X 297 mm)