JP2005093486A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP2005093486A
JP2005093486A JP2003320880A JP2003320880A JP2005093486A JP 2005093486 A JP2005093486 A JP 2005093486A JP 2003320880 A JP2003320880 A JP 2003320880A JP 2003320880 A JP2003320880 A JP 2003320880A JP 2005093486 A JP2005093486 A JP 2005093486A
Authority
JP
Japan
Prior art keywords
insulating film
hole
electrode
pad electrode
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003320880A
Other languages
Japanese (ja)
Inventor
Tsukasa Miyaji
主 宮治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2003320880A priority Critical patent/JP2005093486A/en
Publication of JP2005093486A publication Critical patent/JP2005093486A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which is capable of stably boring through-holes of fixed shape in a semiconductor substrate, and to provide a semiconductor device. <P>SOLUTION: In a method of forming an electrode 37, which is used for leading out a pad electrode 5 formed on the surface of a silicon substrate 1 through the intermediary of an interlayer insulating film 3 to the rear surface of the silicon substrate 1, the silicon substrate 1 and the interlayer insulating film 3 are etched from behind the substrate 1, to form a through-hole H whose bottom is the rear surface of the pad electrode 5, and an insulating film 21 is formed on a part of the silicon substrate 1, which serves as the side of the through-hole H and the rear surface of the silicon substrate 1. Thereafter, a metallic material of copper or the like is formed on the insulating film 21 so as to fill up the through-hole H, and the metal material filling the through-hole H is processed into a plug electrode 37 of a prescribed shape. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置の製造方法及び半導体装置に関し、特に、半導体基板の表面にあるパッド電極をその裏面に引き出すような貫通電極を備えたＩＣチップの製造方法及びＩＣチップに関するものである。   The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and more particularly to a method of manufacturing an IC chip and a IC chip having a through electrode that leads a pad electrode on the surface of a semiconductor substrate to the back surface thereof.

従来から、電子機器の小型化をより一層進展させる方法の一つとして、トランジスタ等が形成されたベア状態のＩＣチップを三次元に積層実装する（ＩＣチップを積み重ねる）技術が知られている（例えば、特許文献１参照。）。この種の実装技術では、積層されるＩＣチップ間で導通をとる必要があり、シリコン基板の表（おもて）面に形成されたパッド電極上にシリコン基板を貫通してその裏面に至るようなプラグ電極を形成していた。   2. Description of the Related Art Conventionally, as one method for further miniaturization of electronic devices, a technique of stacking and mounting three-dimensional bare IC chips on which transistors and the like are formed (stacking IC chips) is known ( For example, see Patent Document 1.) In this type of mounting technology, it is necessary to establish electrical continuity between the stacked IC chips, and the silicon substrate penetrates the pad electrode formed on the front surface of the silicon substrate and reaches the back surface thereof. Plug electrode was formed.

図９（Ａ）〜図１５（Ｂ）は、従来例に係るＩＣチップ２００の製造方法（その１〜７）を示す工程図である。図９（Ａ）において、２０１はシリコン（Ｓｉ）基板、２０３は層間絶縁膜（ＳｉＯ２）、２０５はパッド電極、２０７はパッシベーション膜、２０９は第１のレジストマスクである。シリコン基板２０１には、図示しないトランジスタ等が既に形成されており、このトランジスタのソースまたはドレイン、或いはゲート電極とパッド電極２０５とが電気的に接続している。以下、この工程図に沿って、上記のプラグ電極を含むＩＣチップ２００の製造方法について説明する。 FIG. 9A to FIG. 15B are process diagrams showing a manufacturing method (Nos. 1 to 7) of the IC chip 200 according to the conventional example. In FIG. 9A, 201 is a silicon (Si) substrate, 203 is an interlayer insulating film (SiO 2 ), 205 is a pad electrode, 207 is a passivation film, and 209 is a first resist mask. A transistor (not shown) or the like is already formed on the silicon substrate 201, and the source or drain of this transistor or the gate electrode and the pad electrode 205 are electrically connected. A method for manufacturing the IC chip 200 including the plug electrode will be described below with reference to the process chart.

図９（Ａ）において、まず始めに、シリコン基板２０１の裏面を研磨して、このシリコン基板２０１の厚さを３００［μｍ］程度に薄く加工する。次に、アルミ等からなるパッド電極２０５の中心部上に開口部を有する第１のレジストマスク２０９を形成する。そして、このレジストマスク２０９をマスクにして、パッド電極２０５にドライエッチングを施す。これにより、図９（Ｂ）に示すように、パッド電極２０５の中心部に層間絶縁膜２０３を底面とする開口部２１１を形成する。この開口部２１１の形状は平面視で略円形であり、その直径は６０〜８０［μｍ］程度である。開口部２１１を形成した後で、図９（Ｃ）に示すように、第１のレジストマスクをアッシングして除去する。   In FIG. 9A, first, the back surface of the silicon substrate 201 is polished, and the thickness of the silicon substrate 201 is reduced to about 300 [μm]. Next, a first resist mask 209 having an opening on the center portion of the pad electrode 205 made of aluminum or the like is formed. Then, dry etching is performed on the pad electrode 205 using the resist mask 209 as a mask. As a result, as shown in FIG. 9B, an opening 211 having the bottom surface of the interlayer insulating film 203 is formed at the center of the pad electrode 205. The shape of the opening 211 is substantially circular in plan view, and its diameter is about 60 to 80 [μm]. After the opening 211 is formed, as shown in FIG. 9C, the first resist mask is removed by ashing.

次に、図１０（Ａ）に示すように、開口部２１１の底面となる層間絶縁膜２０３の一部を露出し、その他を覆うような第２のレジストマスク２１３をシリコン基板２０１の上方に形成する。そして、このレジストマスク２１３をマスクにして、層間絶縁膜２０３にドライエッチングを施す。これにより、図１０（Ｂ）に示すように、シリコン基板２０１を底面とする開口部２１５を形成する。この開口部２１５を形成した後で、レジストマスク２１３をアッシングして除去する。   Next, as shown in FIG. 10A, a second resist mask 213 is formed above the silicon substrate 201 so as to expose a part of the interlayer insulating film 203 serving as the bottom surface of the opening 211 and cover the others. To do. Then, dry etching is performed on the interlayer insulating film 203 using the resist mask 213 as a mask. Thereby, as shown in FIG. 10B, an opening 215 whose bottom surface is the silicon substrate 201 is formed. After the opening 215 is formed, the resist mask 213 is removed by ashing.

次に、図１０（Ｃ）に示すように、シリコン基板２０１の上方全面にシリコン酸化膜２１７を形成する。このシリコン酸化膜２１７の厚さは、２［μｍ］程度である。次に、図１１（Ａ）に示すように、開口部２１５の底面、即ち、シリコン基板２０１上にあるシリコン酸化膜２１７の一部を露出し、その他を覆うような第３のレジストマスク２１９をシリコン酸化膜２１７上に形成する。   Next, as shown in FIG. 10C, a silicon oxide film 217 is formed on the entire upper surface of the silicon substrate 201. The thickness of the silicon oxide film 217 is about 2 [μm]. Next, as shown in FIG. 11A, a third resist mask 219 that exposes the bottom surface of the opening 215, that is, a part of the silicon oxide film 217 on the silicon substrate 201 and covers the others is formed. It is formed on the silicon oxide film 217.

そして、このレジストマスク２１９をマスクにして、シリコン酸化膜２１７にドライエッチングを施す。これにより、図１１（Ｂ）に示すように、シリコン基板２０１上に開口部を有するハードマスク２１７´を形成する。このハードマスク２１７´の開口部の形状は平面視で略円形であり、その直径は２０〜５０［μｍ］程度である。このハードマスク２１７´を形成した後で、レジストマスク２１９をアッシングして除去する。   Then, dry etching is performed on the silicon oxide film 217 using the resist mask 219 as a mask. Thus, as shown in FIG. 11B, a hard mask 217 ′ having an opening is formed on the silicon substrate 201. The shape of the opening of the hard mask 217 ′ is substantially circular in plan view, and the diameter thereof is about 20 to 50 [μm]. After the hard mask 217 ′ is formed, the resist mask 219 is removed by ashing.

次に、図１１（Ｃ）に示すように、このハードマスク２１７´をマスクにして、シリコン基板２０１にドライエッチングを施して、このシリコン基板２０１に深さが７０〜１５０［μｍ］程度の開口部２２１を形成する。このドライエッチングには、ＳＦ６、ＳＦ６／Ｏ２系等のエッチングガスを用いる。このようなエッチング条件によれば、シリコン酸化膜はほとんどエッチングされず、シリコンだけを異方的にエッチングする。この時、図１１（Ｃ）に示すように、開口部２２１の側壁の上方にハードマスク２１７´のひさし２２３が形成される。 Next, as shown in FIG. 11C, the silicon substrate 201 is dry-etched using the hard mask 217 ′ as a mask, and an opening having a depth of about 70 to 150 [μm] is formed in the silicon substrate 201. A portion 221 is formed. For this dry etching, an etching gas such as SF 6 or SF 6 / O 2 is used. Under such etching conditions, the silicon oxide film is hardly etched, and only silicon is anisotropically etched. At this time, as shown in FIG. 11C, the eaves 223 of the hard mask 217 ′ are formed above the side wall of the opening 221.

ここで、このひさし２２３を除去しておかないと、後述する絶縁膜２２７（図１２（Ｃ）参照）を開口部２２１の側壁に正常に形成することができない。そこで、図１２（Ａ）に示すように、このハードマスク２１７´のひさし２２３と開口部２２１とを露出し、その他を覆うような第４のレジストマスク２２５をハードマスク２１７´上に形成する。この第４のレジストマスク２２５の開口径は５４〜７４［μｍ］程度である。そして、このレジストマスク２２５をマスクにして、ハードマスク２１７´のひさし２２３にドライエッチングを施す。このドライエッチングには、ＣＦ４、ＣＨＦ３、Ｃ２Ｆ６と、Ｏ２、Ｈｅ等などからなる混合ガスを用いる。このようなドライエッチングによって、図１２（Ｂ）に示すように、ハードマスク２１７´のひさしを除去する。その後、レジストマスク２２５をアッシングして除去する。 Here, unless the eaves 223 are removed, an insulating film 227 (see FIG. 12C) described later cannot be normally formed on the sidewall of the opening 221. Therefore, as shown in FIG. 12A, a fourth resist mask 225 is formed on the hard mask 217 ′ so as to expose the eaves 223 and the opening 221 of the hard mask 217 ′ and cover the others. The opening diameter of the fourth resist mask 225 is about 54 to 74 [μm]. Then, dry etching is performed on the eaves 223 of the hard mask 217 ′ using the resist mask 225 as a mask. For this dry etching, a mixed gas composed of CF 4 , CHF 3 , C 2 F 6 , O 2 , He, or the like is used. By such dry etching, the eaves of the hard mask 217 'are removed as shown in FIG. Thereafter, the resist mask 225 is removed by ashing.

次に、図１２（Ｃ）に示すように、シリコン基板２０１の上方全面にシリコン酸化膜からなる絶縁膜２２７を形成する。この絶縁膜２２７の厚さは、１［μｍ］程度である。ここで、ハードマスク２１７´のひさしは上述したドライエッチングによって既に除去されているので、絶縁膜２２７は開口部２２１の側壁に正常に形成される。
次に、図１３（Ａ）に示すように、パッド電極２０５の上方の一部を露出し、その他を覆うような第５のレジストマスク２２９を絶縁膜２２７上に形成する。そして、図１３（Ｂ）に示すように、このレジストマスク２２９をマスクに絶縁膜２２７と、ハードマスク２１７´とにドライエッチングを施して、パッド電極２０５上にプラグ電極との導通をとるための開口部２３１を形成する。開口部２３１の形成後、レジストマスク２２９をアッシングして除去する。 Next, as shown in FIG. 12C, an insulating film 227 made of a silicon oxide film is formed on the entire upper surface of the silicon substrate 201. The thickness of the insulating film 227 is about 1 [μm]. Here, since the eaves of the hard mask 217 ′ have already been removed by the dry etching described above, the insulating film 227 is normally formed on the side wall of the opening 221.
Next, as shown in FIG. 13A, a fifth resist mask 229 is formed on the insulating film 227 so as to expose a part above the pad electrode 205 and cover the other part. Then, as shown in FIG. 13B, dry etching is performed on the insulating film 227 and the hard mask 217 ′ using the resist mask 229 as a mask to make the plug electrode 205 conductive with the plug electrode 205. An opening 231 is formed. After the opening 231 is formed, the resist mask 229 is removed by ashing.

次に、図１３（Ｃ）に示すように、シリコン基板２０１の上方全面にスパッタリング法を用いて、下地メタル膜２３３を形成する。次に、図１４（Ａ）に示すように、パッド電極２０５の上方全面を露出し、その他を覆うような第６のレジストマスク２３５を下地メタル膜２３３上に形成する。そして、図１４（Ｂ）に示すように、電界メッキ及び無電界メッキにより、レジストマスク２３５下から露出した下地メタル膜２３３上に銅等の金属材料からなる電極２３７を形成する。電極２３７を形成した後で、図１４（Ｃ）に示すように、第６のレジストマスクをアッシングして除去する。   Next, as shown in FIG. 13C, a base metal film 233 is formed on the entire upper surface of the silicon substrate 201 by a sputtering method. Next, as shown in FIG. 14A, a sixth resist mask 235 is formed on the base metal film 233 so that the entire upper surface of the pad electrode 205 is exposed and the others are covered. Then, as shown in FIG. 14B, an electrode 237 made of a metal material such as copper is formed on the base metal film 233 exposed from below the resist mask 235 by electroplating and electroless plating. After the electrode 237 is formed, the sixth resist mask is removed by ashing as shown in FIG.

次に、図１５（Ａ）に示すように、電極２３７下から露出した下地メタル膜２３３をドライエッチングして除去する。そして、シリコン基板２０１の裏面側を研削して、このシリコン基板２０１の裏面側から電極２３７の端部を露出させる。さらに、ＣＦ４とＯ２の混合ガスを用いて、シリコン基板２０１の裏面側をドライエッチングする。このようにして、図１５（Ｂ）に示すように、シリコン基板２０１と、このシリコン基板２０１の裏面に露出した絶縁膜２２７とを削り、電極２３７の端部をシリコン基板２０１の裏面からある程度突出させて、ＩＣチップ２００を完成させる。
特開２０００−２７７６８９号公報 Next, as shown in FIG. 15A, the base metal film 233 exposed from under the electrode 237 is removed by dry etching. Then, the back side of the silicon substrate 201 is ground to expose the end of the electrode 237 from the back side of the silicon substrate 201. Further, the back side of the silicon substrate 201 is dry etched using a mixed gas of CF 4 and O 2 . In this way, as shown in FIG. 15B, the silicon substrate 201 and the insulating film 227 exposed on the back surface of the silicon substrate 201 are shaved, and the end portion of the electrode 237 protrudes from the back surface of the silicon substrate 201 to some extent. Thus, the IC chip 200 is completed.
JP 2000-276789 A

ところで、従来例に係るＩＣチップ２００の製造方法によれば、以下に示すような第１、第２の問題点があった。
・第１の問題点
ＩＣチップ２００の製造工程では、パッド電極２０５の中心部に開口部２１１（図９（Ｂ）参照）を形成する前に、このパッド電極２０５の表面にプローブ針を押し当てて、このＩＣチップ２００の電気的特性を検査することが普通である。 Incidentally, the method for manufacturing the IC chip 200 according to the conventional example has the following first and second problems.
First Problem In the manufacturing process of the IC chip 200, the probe needle is pressed against the surface of the pad electrode 205 before the opening 211 (see FIG. 9B) is formed at the center of the pad electrode 205. In general, the electrical characteristics of the IC chip 200 are inspected.

このため、開口部２１１の形成工程では、パッド電極２０５の表面にプローブ痕（針当てによるアルミ膜の盛り上がり）が残されている場合が多い。そして、このプローブ痕の影響で、図１６（Ａ）に示すように、開口部２１１を形成した後にはアルミのエッチング残り２０５ａが発生し易いという問題があった。開口部２１１内にエッチング残り２０５ａが発生してしまうと、層間絶縁膜２０３に開口部を形成する際に、このエッチング残り２０５ａがマスクとなってしまい、図１６（Ｂ）に示すように、開口部２１５内にＳｉＯ２等のエッチング残り２０３ａが発生してしまうおそれがある。 For this reason, in the step of forming the opening 211, probe marks (a bulge of the aluminum film due to the needle contact) are often left on the surface of the pad electrode 205. Due to the influence of the probe marks, as shown in FIG. 16A, there is a problem in that an aluminum etching residue 205a is likely to occur after the opening 211 is formed. If the etching residue 205a occurs in the opening 211, the etching residue 205a becomes a mask when the opening is formed in the interlayer insulating film 203. As shown in FIG. Etching residue 203a such as SiO 2 may be generated in the portion 215.

また、開口部２１５内にエッチング残り２０３ａが発生してしまうと、シリコン基板２０１に開口部を形成する際に、図１６（Ｃ）に示すように、このエッチング残り２０３ａがマスクとなってしまい、開口部２２１を正常な形状に形成できないおそれがあった。例えば、図１６（Ｃ）に示すように、エッチング残り２０３ａがマスクとなって開口部２２１内に凹凸が形成されてしまうと、電極２３７（図４Ｂ参照）を正常な形状に形成することができないので、ＩＣチップ２００の歩留りが低くなってしまう。
・第２の問題点
また、従来例に係るＩＣチップ２００の製造方法では、図９（Ｂ）に示すように、トランジスタ等の素子に接続するパッド電極２０５にドライエッチングを施して、その中央部に開口部２１１を形成していた。 Further, if the etching residue 203a is generated in the opening 215, when the opening is formed in the silicon substrate 201, the etching residue 203a becomes a mask as shown in FIG. There was a possibility that the opening 221 could not be formed into a normal shape. For example, as shown in FIG. 16C, the electrode 237 (see FIG. 4B) cannot be formed in a normal shape if unevenness is formed in the opening 221 using the etching residue 203a as a mask. As a result, the yield of the IC chip 200 is lowered.
Second Problem Also, in the method of manufacturing the IC chip 200 according to the conventional example, as shown in FIG. 9B, the pad electrode 205 connected to the element such as a transistor is dry-etched, and the center portion The opening 211 was formed in the front.

しかしながら、この開口部２１１の形成工程では、パッド電極２０５の表面にプローブ痕が残されている場合が多いので、パッド電極２０５を過剰にオーバーエッチングして、プローブ痕によるアルミのエッチング残りを完全に除去する必要があった。このため、パッド電極２０５は長時間にわたってプラズマ雰囲気に晒されてしまい、このパッド電極２０５につながる素子がプラズマダメージによって破壊されてしまうおそれがあった。例えば、パッド電極２０５に接続する素子がトランジスタの場合には、トランジスタのゲート絶縁膜に多量の電荷が流れ込んで、ゲート絶縁膜が破壊されてしまうおそれがあった。   However, in this step of forming the opening 211, probe marks are often left on the surface of the pad electrode 205. Therefore, the pad electrode 205 is overetched excessively to completely remove the aluminum etching residue from the probe marks. It was necessary to remove. For this reason, the pad electrode 205 is exposed to the plasma atmosphere for a long time, and the element connected to the pad electrode 205 may be destroyed by the plasma damage. For example, when the element connected to the pad electrode 205 is a transistor, a large amount of charge flows into the gate insulating film of the transistor, which may destroy the gate insulating film.

そこで、この発明は、このような問題を解決したものであって、一定形状の貫通孔を半導体基板に安定して形成できるようにした半導体装置の製造方法及び半導体装置の提供を目的とする。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device which can solve such problems and can stably form a through hole having a fixed shape in a semiconductor substrate.

上記した課題を解決するために、本発明に係る第１の半導体装置の製造方法は、半導体基板の一方の面に層間絶縁膜を介して形成されたパッド電極を当該半導体基板の他方の面に引き出すための貫通電極を形成する方法であって、前記半導体基板の前記他方の面から当該半導体基板と前記層間絶縁膜とをエッチングして前記パッド電極を底面とする貫通孔を形成する工程と、前記貫通孔の前記半導体基板からなる側壁と、当該半導体基板の前記他方の面とに絶縁膜を形成する工程と、前記貫通孔を埋め込むように前記絶縁膜上に導電材料を形成し、当該導電材料を所定形状に加工して前記貫通電極を形成する工程と、を含むことを特徴とするものである。   In order to solve the above-described problems, a first method of manufacturing a semiconductor device according to the present invention includes a pad electrode formed on one surface of a semiconductor substrate via an interlayer insulating film on the other surface of the semiconductor substrate. A method of forming a through electrode for drawing out, the step of etching the semiconductor substrate and the interlayer insulating film from the other surface of the semiconductor substrate to form a through hole having the pad electrode as a bottom surface; A step of forming an insulating film on the side wall of the through-hole of the semiconductor substrate and the other surface of the semiconductor substrate, and forming a conductive material on the insulating film so as to fill the through-hole, And processing the material into a predetermined shape to form the through electrode.

ここで、パッド電極は例えばアルミ等からなるものである。半導体装置の製造工程では貫通電極を形成する前に、通常、パッド電極の表面にプローブ針を押し当てて、当該半導体装置の電気的特性を検査するが、アルミ等からなるパッド電極に対してプローブ針は一般に硬く先鋭である。このため、貫通電極を形成するときには、パッド電極の表面にプローブ痕と呼ばれるアルミ膜の盛り上がりが生じている場合が多い。   Here, the pad electrode is made of, for example, aluminum. In the manufacturing process of a semiconductor device, before forming the through electrode, the probe needle is usually pressed against the surface of the pad electrode to inspect the electrical characteristics of the semiconductor device. The needle is generally hard and sharp. For this reason, when the through electrode is formed, the aluminum film called a probe mark is often raised on the surface of the pad electrode.

本発明に係る第２の半導体装置の製造方法は、上述した第１の半導体装置の製造方法において、前記貫通孔を形成する前に、前記パッド電極を含む前記半導体基板の前記一方の面全体に保護膜を形成する工程を含むことを特徴とするものである。
また、本発明に係る第３の半導体装置の製造方法は、上述した第１、第２の半導体装置の製造方法において、前記貫通孔を形成する工程は、前記パッド電極に対応する位置の前記半導体基板をエッチングして前記層間絶縁膜を底面とする開口部を形成し、前記開口部底面の前記層間絶縁膜を選択的にエッチングして前記貫通孔を形成する工程であることを特徴とするものである。 According to the second method for manufacturing a semiconductor device of the present invention, in the first method for manufacturing a semiconductor device described above, the entire one surface of the semiconductor substrate including the pad electrode is formed before the through hole is formed. The method includes a step of forming a protective film.
The third method for manufacturing a semiconductor device according to the present invention is the above-described first and second methods for manufacturing a semiconductor device, wherein the step of forming the through hole includes the semiconductor at a position corresponding to the pad electrode. Etching a substrate to form an opening having the interlayer insulating film as a bottom surface, and selectively etching the interlayer insulating film on the bottom surface of the opening to form the through hole. It is.

本発明に係る第１〜第３の半導体装置の製造方法によれば、パッド電極に貫通孔を形成していないので、パッド電極の表面に生じたプローブ痕の位置や、大きさ、形状に関係なく、一定形状の貫通孔を半導体基板に安定して形成することができる。従って、貫通電極を所定の形状に再現性良く形成することができる。また、パッド電極に貫通孔を形成していないので、従来方式と比べて、このパッド電極がプラズマ雰囲気に晒される機会を少なくすることができる。これにより、パッド電極につながる素子へのプラズマダメージを低減することができる。   According to the first to third methods of manufacturing a semiconductor device according to the present invention, since no through hole is formed in the pad electrode, it is related to the position, size, and shape of the probe mark generated on the surface of the pad electrode. In addition, it is possible to stably form a through hole having a fixed shape in the semiconductor substrate. Therefore, the through electrode can be formed in a predetermined shape with good reproducibility. Further, since no through-hole is formed in the pad electrode, the opportunity for the pad electrode to be exposed to the plasma atmosphere can be reduced as compared with the conventional method. Thereby, plasma damage to the element connected to the pad electrode can be reduced.

本発明に係る第４の半導体装置の製造方法は、上述した第３の半導体装置の製造方法において、前記半導体基板はシリコン基板であり、前記貫通孔を形成する工程では、前記シリコン基板の他方の面にシリコン酸化膜からなるマスクパターンを形成し、当該マスクパターンをマスクに前記シリコン基板の他方の面をエッチングして前記開口部を形成することを特徴とするものである。   According to a fourth method of manufacturing the semiconductor device according to the present invention, in the third method of manufacturing a semiconductor device, the semiconductor substrate is a silicon substrate, and in the step of forming the through hole, the other of the silicon substrates is formed. A mask pattern made of a silicon oxide film is formed on the surface, and the opening is formed by etching the other surface of the silicon substrate using the mask pattern as a mask.

本発明に係る第４の半導体装置の製造方法によれば、シリコン基板に開口部を形成した後で、シリコン酸化膜からなるマスクパターンをレジストマスクなしにエッチングして除去することが可能である。従来方式と比べて、レジストマスクの形成工程の削減に貢献することが可能である。
本発明に係る第５の半導体装置の製造方法は、請求項１〜請求項４の何れか一項に記載の半導体装置のうち、一の前記半導体装置の前記一方の面にある前記パッド電極と、他の前記半導体装置の前記他方の面にある前記貫通電極とを接続するように、少なくとも２個以上の前記半導体装置を積み重ねて集積回路を形成することを特徴とするものである。 According to the fourth method for manufacturing a semiconductor device of the present invention, after the opening is formed in the silicon substrate, the mask pattern made of the silicon oxide film can be etched and removed without the resist mask. Compared with the conventional method, it is possible to contribute to the reduction of the resist mask formation process.
A fifth method for manufacturing a semiconductor device according to the present invention includes: the pad electrode on the one surface of one of the semiconductor devices according to any one of claims 1 to 4; Further, at least two or more of the semiconductor devices are stacked to form an integrated circuit so as to connect with the through electrode on the other surface of the other semiconductor device.

本発明に係る第５の半導体装置の製造方法によれば、上記の第１〜第４の半導体装置の製造方法が応用されるので、パッド電極の表面に生じたプローブ痕の位置や、大きさ、形状に関係なく、一定形状の貫通孔を半導体基板に安定して形成することができる。従って、貫通電極を所定の形状に再現性良く形成することができ、集積回路における配線接続の信頼性向上に貢献することができる。   According to the fifth method for manufacturing a semiconductor device according to the present invention, the above-described first to fourth methods for manufacturing a semiconductor device are applied. Therefore, the position and size of the probe mark generated on the surface of the pad electrode. Regardless of the shape, a constant-shaped through hole can be stably formed in the semiconductor substrate. Therefore, the through electrode can be formed in a predetermined shape with good reproducibility, which can contribute to improving the reliability of wiring connection in the integrated circuit.

本発明に係る半導体装置は、半導体基板と、前記半導体基板の一方の面に設けられた層間絶縁膜と、前記層間絶縁膜上に設けられたパッド電極と、前記パッド電極を底面とするように前記半導体基板と前記層間絶縁膜とに設けられた貫通孔と、前記貫通孔の前記半導体基板からなる側壁と、当該半導体基板の他方の面とに設けられた絶縁膜と、前記貫通孔に埋め込まれ、当該貫通孔から前記半導体基板の前記他方の面の前記絶縁膜上にかけて設けられた貫通電極とを備えたことを特徴とするものである。   A semiconductor device according to the present invention includes a semiconductor substrate, an interlayer insulating film provided on one surface of the semiconductor substrate, a pad electrode provided on the interlayer insulating film, and the pad electrode as a bottom surface. A through hole provided in the semiconductor substrate and the interlayer insulating film, a side wall made of the semiconductor substrate of the through hole, an insulating film provided on the other surface of the semiconductor substrate, and embedded in the through hole And a through electrode provided from the through hole to the insulating film on the other surface of the semiconductor substrate.

本発明に係る半導体装置によれば、従来方式と比べて、パッド電極には貫通孔が設けられていないので、貫通電極の形状均一化に貢献することができる。   According to the semiconductor device of the present invention, compared to the conventional method, the pad electrode is not provided with a through hole, which can contribute to uniform shape of the through electrode.

以下、図面を参照しながら、本発明の実施形態に係る半導体装置の製造方法及び半導体装置について説明する。
図１は、本発明の実施形態に係るＩＣチップ１００の構成例を示す要部断面図である。図１において、１はシリコン基板、３は層間絶縁膜、５はパッド電極、７はパッシベーション膜、９は開口部、２１は絶縁膜、２３は下地メタル膜、３７は電極、Ｈは貫通孔である。 A semiconductor device manufacturing method and a semiconductor device according to embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a cross-sectional view of a principal part showing a configuration example of an IC chip 100 according to an embodiment of the present invention. In FIG. 1, 1 is a silicon substrate, 3 is an interlayer insulating film, 5 is a pad electrode, 7 is a passivation film, 9 is an opening, 21 is an insulating film, 23 is a base metal film, 37 is an electrode, and H is a through hole. is there.

これらの中で、図１に示す層間絶縁膜３は、例えばシリコン酸化膜、またはシリコン窒化膜（Ｓｉ３Ｎ４）等からなるものである。この層間絶縁膜３は、シリコン基板１に設けられたトランジスタ（図示せず）等を覆うように、このシリコン基板１の表（おもて）面に形成されている。
また、パッド電極５は例えばアルミ等からなるものである。このパッド電極５は層間絶縁膜３上に形成されており、シリコン基板１に形成された図示しない素子と電気的に接続している。この素子とは、例えばトランジスタのことであり、パッド電極５はトランジスタのソース、ドレイン、またはゲート電極等と電気的に接続している。 Among these, the interlayer insulating film 3 shown in FIG. 1 is made of, for example, a silicon oxide film or a silicon nitride film (Si 3 N 4 ). The interlayer insulating film 3 is formed on the front surface of the silicon substrate 1 so as to cover a transistor (not shown) provided on the silicon substrate 1.
The pad electrode 5 is made of, for example, aluminum. The pad electrode 5 is formed on the interlayer insulating film 3 and is electrically connected to an element (not shown) formed on the silicon substrate 1. This element is, for example, a transistor, and the pad electrode 5 is electrically connected to the source, drain, or gate electrode of the transistor.

ところで、ＩＣチップ１００の製造工程では、電極３７を形成する前に、このトランジスタや、このトランジスタを含む回路等の電気的特性や、動作を検査して、不良品の選別を行うことが普通である。この検査工程では、このパッド電極２０５の表（おもて）面にプローブ針を押し当てて電気信号の送受を行うが、アルミ等からなるパッド電極５に対して、プローブ針は硬く先鋭である。このため、このパッド電極５の表面には、プローブ痕と呼ばれるアルミの盛り上がりが発生している。以下で、この検査のことをプローブ検査という。   By the way, in the manufacturing process of the IC chip 100, before forming the electrode 37, it is usual to check the electrical characteristics and operation of this transistor and a circuit including the transistor to select defective products. is there. In this inspection process, the probe needle is pressed against the front surface of the pad electrode 205 to transmit and receive electrical signals. The probe needle is hard and sharp with respect to the pad electrode 5 made of aluminum or the like. . For this reason, aluminum swell called probe marks is generated on the surface of the pad electrode 5. Hereinafter, this inspection is referred to as probe inspection.

また、図１に示すパッシベーション膜７は、例えばシリコン酸化膜、またはシリコン窒化膜、或いはシリコン酸窒化膜（ＳｉＯＮ）などからなるものである。このパッシベーション膜７は、ＩＣチップ１００を機械的応力や不純物の侵入から保護するための保護膜である。図１に示すように、このパッシベーション膜７には開口部９が形成されており、この開口部９からパッド電極５の表面が露出している。   The passivation film 7 shown in FIG. 1 is made of, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiON). The passivation film 7 is a protective film for protecting the IC chip 100 from mechanical stress and impurities. As shown in FIG. 1, an opening 9 is formed in the passivation film 7, and the surface of the pad electrode 5 is exposed from the opening 9.

さらに、貫通孔Ｈはパッド電極５を底面とするように当該シリコン基板１と層間絶縁膜３とに形成されている。また、絶縁膜２１は、この貫通孔Ｈのシリコン基板１からなる側壁と、このシリコン基板１の裏面とに形成されている。電極３７は貫通孔Ｈに埋め込まれ、この貫通孔Ｈからシリコン基板１裏面の絶縁膜２１上にかけて形成されている。このような構造によって、電極３７は、下地メタル膜２３を介してパッド電極５と電気的に接続している。   Further, the through hole H is formed in the silicon substrate 1 and the interlayer insulating film 3 so that the pad electrode 5 is the bottom surface. The insulating film 21 is formed on the side wall of the through hole H made of the silicon substrate 1 and the back surface of the silicon substrate 1. The electrode 37 is embedded in the through hole H, and is formed from the through hole H over the insulating film 21 on the back surface of the silicon substrate 1. With such a structure, the electrode 37 is electrically connected to the pad electrode 5 through the base metal film 23.

図３（Ａ）〜図８はＩＣチップ１００の製造方法を示す工程図（その１〜６）である。この工程図は、ＩＣチップ１００の製造工程のうち、シリコン基板１の裏面側にプラグ電極３７を形成して、ＩＣチップ１００を完成させるまでを示している。図３（Ａ）において、パッシベーション膜７に開口部を形成する工程までは、周知の前工程（ｗａｆｅｒ ｐｒｏｃｅｓｓ）によるので、その説明は省略する。なお、説明の便宜上から、図３（Ｂ）〜図８は、図３（Ａ）に対して上下逆さまとなっている。   3A to 8 are process diagrams (Nos. 1 to 6) showing a method of manufacturing the IC chip 100. FIG. This process diagram shows a process from the manufacturing process of the IC chip 100 to the process of forming the plug electrode 37 on the back side of the silicon substrate 1 to complete the IC chip 100. In FIG. 3A, the process up to the step of forming the opening in the passivation film 7 is a known pre-process (wafer process), and the description thereof is omitted. For convenience of explanation, FIGS. 3B to 8 are upside down with respect to FIG.

図３（Ａ）において、パッシベーション膜７に開口部を形成しパッド電極５上を露出させて、プローブ検査を行った後で、シリコン基板１の裏面を研磨して、このシリコン基板１を少なくとも３００［μｍ］程度の厚さまで薄く加工しておく。次に、このパッド電極５及びパッシベーション膜７を覆うようにシリコン基板１の表面上に表面保護膜１１を形成する。この表面保護膜１１は、例えばシリコン酸化膜である。また、シリコン酸化膜に限らず、傷がつきにくく、パーティクルが発生しにくく、しかも後工程で剥離しやすい性質を有する絶縁性の膜を表面保護膜１１として用いても良い。   In FIG. 3A, after an opening is formed in the passivation film 7 to expose the pad electrode 5 and probe inspection is performed, the back surface of the silicon substrate 1 is polished, and this silicon substrate 1 is at least 300 Thinly processed to a thickness of about [μm]. Next, a surface protective film 11 is formed on the surface of the silicon substrate 1 so as to cover the pad electrode 5 and the passivation film 7. This surface protective film 11 is, for example, a silicon oxide film. Further, not only the silicon oxide film, but also an insulating film having the property that it is difficult to be damaged, particles are not easily generated, and is easily peeled off in a later process may be used as the surface protective film 11.

次に、図３（Ｂ）に示すように、この研磨されたシリコン基板１の裏面全体にシリコン酸化膜１３を形成する。このシリコン酸化膜１３は、例えばＣＶＤ法を用いて２［μｍ］程度の厚さに形成する。次に、図３（Ｃ）に示すように、シリコン基板１裏面のパッド電極５に対応する位置に開口部を有する第１のレジストマスク１５を、このシリコン基板１の裏面に形成する。このレジストマスク１５の形成は、例えばフォトリソグラフィリソ技術を用いて行う。   Next, as shown in FIG. 3B, a silicon oxide film 13 is formed on the entire back surface of the polished silicon substrate 1. The silicon oxide film 13 is formed to a thickness of about 2 [μm] using, for example, a CVD method. Next, as shown in FIG. 3C, a first resist mask 15 having an opening at a position corresponding to the pad electrode 5 on the back surface of the silicon substrate 1 is formed on the back surface of the silicon substrate 1. The resist mask 15 is formed using, for example, a photolithography lithography technique.

次に、図４（Ａ）に示すように、このレジストマスク１５をマスクにシリコン酸化膜をエッチングして、シリコン基板１裏面のパッド電極５に対応する位置に開口部１７を有するハードマスク１３´を形成する。この開口部１７からは、シリコン基板１が露出している。このシリコン酸化膜のエッチングは、例えばＣＦ４と、ＣＨＦ３と、Ｃ２Ｆ６と、Ｏ２と、Ｈｅ等とからなる混合ガスを用いたドライエッチングにより行う。ハードマスク１３´を形成した後で、図４（Ｂ）に示すように、第１のレジストマスクをアッシングして除去する。 Next, as shown in FIG. 4A, the silicon oxide film is etched using the resist mask 15 as a mask, and a hard mask 13 ′ having an opening 17 at a position corresponding to the pad electrode 5 on the back surface of the silicon substrate 1. Form. The silicon substrate 1 is exposed from the opening 17. The etching of the silicon oxide film is performed by dry etching using a mixed gas composed of, for example, CF 4 , CHF 3 , C 2 F 6 , O 2 and He. After the hard mask 13 'is formed, the first resist mask is removed by ashing as shown in FIG.

次に、図４（Ｃ）に示すように、このハードマスク１３´をマスクにシリコン基板１をエッチングして、層間絶縁膜３を底面とする開口部１９を形成する。このシリコン基板１のエッチングは、例えばＳＦ６、ＳＦ６／Ｏ２系等のエッチングガスを用いたドライエッチングにより行う。開口部１９を形成した後で、図５（Ａ）に示すように、ハードマスクをエッチングして除去する。 Next, as shown in FIG. 4C, the silicon substrate 1 is etched using the hard mask 13 'as a mask to form an opening 19 having the interlayer insulating film 3 as a bottom surface. This silicon substrate 1 is etched by dry etching using an etching gas such as SF 6 or SF 6 / O 2 . After the opening 19 is formed, the hard mask is removed by etching as shown in FIG.

このハードマスクの除去は、例えばＣＦ４と、ＣＨＦ３と、Ｃ２Ｆ６と、Ｏ２と、Ｈｅ等とからなる混合ガスを用いたドライエッチングにより行う。図５（Ａ）に示すように、このハードマスクの除去によって、開口部１９から露出した層間絶縁膜３は多少エッチングされて膜減りするが、開口部１９以外の領域の層間絶縁膜３はシリコン基板１でマスクされているので、エッチングされずにそのまま残される。 The hard mask is removed by dry etching using a mixed gas composed of CF 4 , CHF 3 , C 2 F 6 , O 2 , He, and the like. As shown in FIG. 5A, by removing the hard mask, the interlayer insulating film 3 exposed from the opening 19 is slightly etched to reduce the film, but the interlayer insulating film 3 in the region other than the opening 19 is made of silicon. Since it is masked by the substrate 1, it remains as it is without being etched.

次に、図５（Ｂ）に示すように、この開口部１９が形成されたシリコン基板１の裏面全体に絶縁膜２１を形成する。この絶縁膜２１は、例えばシリコン酸化膜であり、ＣＶＤ法を用いて１［μｍ］程度の厚さに形成する。次に、図５（Ｃ）に示すように、開口部１９の底面を露出し、開口部１９の側壁と開口部１９以外とを覆う第２のレジストマスク２５をシリコン基板１の裏面に形成する。この第２のレジストマスク２５の形成は、例えばフォトリソグラフィ技術を用いて行う。   Next, as shown in FIG. 5B, an insulating film 21 is formed on the entire back surface of the silicon substrate 1 in which the opening 19 is formed. The insulating film 21 is a silicon oxide film, for example, and is formed to a thickness of about 1 [μm] using a CVD method. Next, as shown in FIG. 5C, a second resist mask 25 that exposes the bottom surface of the opening 19 and covers the side wall of the opening 19 and the portion other than the opening 19 is formed on the back surface of the silicon substrate 1. . The second resist mask 25 is formed by using, for example, a photolithography technique.

そして、図６（Ａ）に示すように、このレジストマスク２５をマスクに層間絶縁膜３をエッチングして、パッド電極５を底面とする開口部２７を形成する。この開口部２７と開口部１９とにより、上述した貫通孔Ｈ（図１参照）は構成される。この層間絶縁膜３のエッチングは、例えばＣＦ４と、ＣＨＦ３と、Ｃ２Ｆ６と、Ｏ２と、Ｈｅ等とからなる混合ガスを用いたドライエッチングにより行う。層間絶縁膜３に開口部２７を形成した後で、図５（Ｂ）に示すように、第２のレジストマスクをアッシングして除去する。 Then, as shown in FIG. 6A, the interlayer insulating film 3 is etched using the resist mask 25 as a mask to form an opening 27 having the pad electrode 5 as a bottom surface. The opening 27 and the opening 19 constitute the above-described through hole H (see FIG. 1). The interlayer insulating film 3 is etched by dry etching using a mixed gas composed of, for example, CF 4 , CHF 3 , C 2 F 6 , O 2 , and He. After the opening 27 is formed in the interlayer insulating film 3, the second resist mask is removed by ashing as shown in FIG.

次に、図６（Ｃ）に示すように、貫通孔Ｈが形成されたシリコン基板１の裏面全体に下地メタル膜２３を形成する。この下地メタル膜２３は、例えばＡｕ、Ｔｉ、Ｎｉ等であり、スパッタ法を用いて形成する。
次に、図７（Ａ）に示すように、貫通孔Ｈを含むプラグ電極の形成領域を露出し、他を覆う第３のレジストマスク２９を下地メタル膜２３上に形成する。このレジストマスク２９の形成は、例えばフォトリソグラフィ技術を用いて行う。そして、図７（Ｂ）に示すように、このレジストマスク２９下から露出した貫通孔Ｈを埋め込むように下地メタル膜２３上に銅等の金属材料を電界メッキ及び無電界メッキで形成し、電極３７を形成する。電極３７を形成した後、図７（Ｃ）に示すように、第３のレジストマスクをアッシングして除去する。 Next, as shown in FIG. 6C, a base metal film 23 is formed on the entire back surface of the silicon substrate 1 in which the through holes H are formed. The base metal film 23 is made of, for example, Au, Ti, Ni or the like, and is formed using a sputtering method.
Next, as shown in FIG. 7A, a third resist mask 29 is formed on the base metal film 23 to expose the plug electrode formation region including the through hole H and cover the other. The resist mask 29 is formed by using, for example, a photolithography technique. Then, as shown in FIG. 7B, a metal material such as copper is formed on the base metal film 23 by electroplating and electroless plating so as to fill the through-holes H exposed from below the resist mask 29. 37 is formed. After the electrode 37 is formed, as shown in FIG. 7C, the third resist mask is removed by ashing.

次に、図８に示すように、電極３７下から露出した下地メタル膜２３をエッチングして除去する。この下地メタル膜２３のエッチングは、例えばＢＣｌ３、Ｃｌ２等とからなる混合ガスを用いたドライエッチングにより行う。その後、シリコン基板１の表面側にある表面保護膜１１をエッチングして除去する。この表面保護膜１１のエッチングは、例えば、ＣＦ４と、ＣＨＦ３と、Ｃ２Ｆ６と、Ｏ２と、Ｈｅ等とからなる混合ガスを用いたドライエッチングにより行う。また、表面保護膜１１のエッチングは、ドライエッチングに限らず、例えば、フッ化アンモン系によるウエットエッチングでも良い。このようにして、図１に示したＩＣチップ１００を完成させる。 Next, as shown in FIG. 8, the underlying metal film 23 exposed from under the electrode 37 is removed by etching. The etching of the base metal film 23 is performed by dry etching using a mixed gas composed of, for example, BCl3, Cl2, or the like. Thereafter, the surface protective film 11 on the surface side of the silicon substrate 1 is removed by etching. The surface protective film 11 is etched by, for example, dry etching using a mixed gas composed of CF 4 , CHF 3 , C 2 F 6 , O 2 , He, and the like. Further, the etching of the surface protective film 11 is not limited to dry etching, but may be wet etching using, for example, ammonium fluoride. In this way, the IC chip 100 shown in FIG. 1 is completed.

また、このＩＣチップ１００を三次元に積層実装する工程では、図２に示すように、一のＩＣチップ１００の裏面側に露出した電極３７と、他のＩＣチップ１００の表面側に露出したパッド電極５とを接続するように、これらのＩＣチップ１００を積み重ねることで、集積回路装置２００を完成させる。
このように、本発明に係るＩＣチップ１００の製造方法によれば、パッド電極５に貫通孔を形成する必要がないので、パッド電極５の表面に生じたプローブ痕の位置や、大きさ、形状に関係なく、一定形状の貫通孔Ｈをシリコン基板１に安定して形成することができる。これにより、電極３７を所定の形状に再現性良く形成することができ、ＩＣチップ１００の歩留りと信頼性の向上に貢献することができる。 Further, in the step of three-dimensionally laminating and mounting the IC chip 100, as shown in FIG. 2, the electrode 37 exposed on the back side of one IC chip 100 and the pad exposed on the front side of another IC chip 100 The integrated circuit device 200 is completed by stacking these IC chips 100 so as to be connected to the electrodes 5.
As described above, according to the method of manufacturing the IC chip 100 according to the present invention, since it is not necessary to form a through hole in the pad electrode 5, the position, size, and shape of the probe marks generated on the surface of the pad electrode 5 Regardless of the case, it is possible to stably form the through hole H having a fixed shape in the silicon substrate 1. Thereby, the electrode 37 can be formed in a predetermined shape with good reproducibility, and can contribute to the improvement of the yield and reliability of the IC chip 100.

また、パッド電極５に貫通孔を形成する必要がないので、従来例と比べて、パッド電極をプラズマ雰囲気に晒す機会を著しく少なくすることができる。従って、シリコン基板１に形成された図示しないトランジスタ等へのプラズマダメージを軽減することができ、ゲート絶縁膜等の破壊を防ぐことができる。
さらに、このＩＣチップ１００の製造方法によれば、従来例と比べて、レジストマスクの形成工程数を削減することができる。具体的には、従来例に係るＩＣチップ２００の製造方法ではレジストマスクの形成工程が６工程必要であるのに対して、本発明に係るＩＣチップ１００の製造方法ではレジストマスクの形成工程が３工程である。従って、ＩＣチップの製造にかかる手間や、時間を大幅に減らすことができ、ＩＣチップの製造コスト低減に貢献することができる。 Further, since it is not necessary to form a through hole in the pad electrode 5, the opportunity to expose the pad electrode to the plasma atmosphere can be remarkably reduced as compared with the conventional example. Therefore, plasma damage to a transistor (not shown) formed on the silicon substrate 1 can be reduced, and breakdown of the gate insulating film or the like can be prevented.
Furthermore, according to the method of manufacturing the IC chip 100, the number of resist mask forming steps can be reduced as compared with the conventional example. Specifically, in the manufacturing method of the IC chip 200 according to the conventional example, the resist mask forming step requires six steps, whereas in the manufacturing method of the IC chip 100 according to the present invention, the resist mask forming step is three. It is a process. Therefore, it is possible to greatly reduce the time and labor involved in the manufacture of the IC chip, which can contribute to reducing the manufacturing cost of the IC chip.

また、従来例に係るＩＣチップ２００の製造方法では、図１７で示すように、例えば第３のレジストマスク２１９をマスクにシリコン酸化膜２１７をエッチングする工程では、レジストマスク２１９表面の段差（矢印部分）は２．０〜４．０［μｍ］程度と大きく、貫通孔の最小加工寸法は２０〜３０［μｍ］程度と小さい。このため、レジストマスク２１９の開口領域にはレジスト残り２１９ａが生じてしまう可能性があった。   Further, in the method of manufacturing the IC chip 200 according to the conventional example, as shown in FIG. 17, for example, in the step of etching the silicon oxide film 217 using the third resist mask 219 as a mask, a step (arrow part on the surface of the resist mask 219). ) Is as large as about 2.0 to 4.0 [μm], and the minimum processing dimension of the through hole is as small as about 20 to 30 [μm]. For this reason, there is a possibility that a resist residue 219a is generated in the opening region of the resist mask 219.

これに対して、本発明にかかるＩＣチップ１００の製造方法では、平坦なシリコン基板１の裏面にレジストマスクを形成するので、従来例と比べて、レジストマスク表面の段差を小さくすることができる。また、プラグ電極には貫通孔を形成しないので、貫通孔の最小加工寸法を例えば６０［μｍ］程度とすることができる。従って、上記のようなレジスト残りの発生を防ぐことができ、工程歩留りを安定化させることができる。   On the other hand, in the method for manufacturing the IC chip 100 according to the present invention, the resist mask is formed on the back surface of the flat silicon substrate 1, so that the level difference on the resist mask surface can be reduced as compared with the conventional example. Further, since no through hole is formed in the plug electrode, the minimum processing dimension of the through hole can be set to about 60 [μm], for example. Therefore, the generation of the resist residue as described above can be prevented, and the process yield can be stabilized.

この実施形態では、シリコン基板１が本発明の半導体基板に対応し、このシリコン基板１の表面が本発明の半導体基板の一方の面に対応している。また、シリコン基板１の裏面が本発明の半導体基板の他方の面に対応し、電極３７が本発明の貫通電極に対応している。さらに、この電極３７を構成する銅等の金属材料が本発明の導電材料に対応している。また、開口部１９が本発明の層間絶縁膜を底面とする開口部に対応し、ハードマスク１３が本発明のシリコン酸化膜からなるマスクパターンに対応している。   In this embodiment, the silicon substrate 1 corresponds to the semiconductor substrate of the present invention, and the surface of the silicon substrate 1 corresponds to one surface of the semiconductor substrate of the present invention. The back surface of the silicon substrate 1 corresponds to the other surface of the semiconductor substrate of the present invention, and the electrode 37 corresponds to the through electrode of the present invention. Furthermore, a metal material such as copper constituting the electrode 37 corresponds to the conductive material of the present invention. The opening 19 corresponds to the opening having the interlayer insulating film of the present invention as a bottom surface, and the hard mask 13 corresponds to the mask pattern made of the silicon oxide film of the present invention.

実施形態に係るＩＣチップ１００の構成例を示す断面図。FIG. 3 is a cross-sectional view illustrating a configuration example of the IC chip 100 according to the embodiment. 実施形態に係る集積回路装置１５０の構成例を示す断面図。FIG. 3 is a cross-sectional view illustrating a configuration example of an integrated circuit device 150 according to the embodiment. ＩＣチップ１００の製造方法（その１）を示す工程図。Process drawing which shows the manufacturing method (the 1) of IC chip 100. FIG. ＩＣチップ１００の製造方法（その２）を示す工程図。Process drawing which shows the manufacturing method (the 2) of IC chip 100. FIG. ＩＣチップ１００の製造方法（その３）を示す工程図。Process drawing which shows the manufacturing method (the 3) of IC chip 100. FIG. ＩＣチップ１００の製造方法（その４）を示す工程図。Process drawing which shows the manufacturing method (the 4) of IC chip 100. FIG. ＩＣチップ１００の製造方法（その５）を示す工程図。Process drawing which shows the manufacturing method (the 5) of IC chip 100. FIG. ＩＣチップ１００の製造方法（その６）を示す工程図。Process drawing which shows the manufacturing method (the 6) of IC chip 100. FIG. 従来例に係るＩＣチップ９０の製造方法（その１）を示す工程図。Process drawing which shows the manufacturing method (the 1) of IC chip 90 which concerns on a prior art example. ＩＣチップ９０の製造方法（その２）を示す工程図。Process drawing which shows the manufacturing method (the 2) of IC chip 90. FIG. ＩＣチップ９０の製造方法（その３）を示す工程図。Process drawing which shows the manufacturing method (the 3) of IC chip 90. FIG. ＩＣチップ９０の製造方法（その４）を示す工程図。Process drawing which shows the manufacturing method (the 4) of IC chip 90. FIG. ＩＣチップ９０の製造方法（その５）を示す工程図。Process drawing which shows the manufacturing method (the 5) of IC chip 90. FIG. ＩＣチップ９０の製造方法（その６）を示す工程図。Process drawing which shows the manufacturing method (the 6) of IC chip 90. FIG. ＩＣチップ９０の製造方法（その７）を示す工程図。Process drawing which shows the manufacturing method (the 7) of IC chip 90. FIG. 従来例の問題点（その１）を示す図。The figure which shows the problem (the 1) of a prior art example. 従来例の問題点（その２）を示す図。The figure which shows the problem (the 2) of a prior art example.

符号の説明Explanation of symbols

１ シリコン基板、３ 層間絶縁膜、５ パッド電極、７ パッシベーション膜、９、１７、１９、２７ 開口部、１１ 表面保護膜、１３ シリコン酸化膜、１３´ ハードマスク、１５、２５、２９ レジストマスク、２１ 絶縁膜、２３ 下地メタル膜、３７ 電極、Ｈ 貫通孔、１００ ＩＣチップ、１５０ 集積回路装置   DESCRIPTION OF SYMBOLS 1 Silicon substrate, 3 interlayer insulation film, 5 pad electrode, 7 passivation film, 9, 17, 19, 27 opening, 11 surface protective film, 13 silicon oxide film, 13 'hard mask, 15, 25, 29 resist mask, 21 insulating film, 23 base metal film, 37 electrode, H through hole, 100 IC chip, 150 integrated circuit device

Claims (6)

半導体基板の一方の面に層間絶縁膜を介して形成されたパッド電極を当該半導体基板の他方の面に引き出すための貫通電極を形成する方法であって、
前記半導体基板の前記他方の面から当該半導体基板と前記層間絶縁膜とをエッチングして前記パッド電極を底面とする貫通孔を形成する工程と、
前記貫通孔の前記半導体基板からなる側壁と、当該半導体基板の前記他方の面とに絶縁膜を形成する工程と、
前記貫通孔を埋め込むように前記絶縁膜上に導電材料を形成し、当該導電材料を所定形状に加工して前記貫通電極を形成する工程と、を含むことを特徴とする半導体装置の製造方法。 A method of forming a through electrode for drawing a pad electrode formed on one surface of a semiconductor substrate via an interlayer insulating film to the other surface of the semiconductor substrate,
Etching the semiconductor substrate and the interlayer insulating film from the other surface of the semiconductor substrate to form a through hole having the pad electrode as a bottom surface;
Forming an insulating film on a side wall of the through hole made of the semiconductor substrate and on the other surface of the semiconductor substrate;
Forming a conductive material on the insulating film so as to fill the through hole, and processing the conductive material into a predetermined shape to form the through electrode. A method for manufacturing a semiconductor device, comprising: 前記貫通孔を形成する前に、前記パッド電極を含む前記半導体基板の前記一方の面全体に保護膜を形成する工程を含むことを特徴とする請求項１に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a protective film on the entire one surface of the semiconductor substrate including the pad electrode before forming the through hole. 前記貫通孔を形成する工程は、
前記パッド電極に対応する位置の前記半導体基板をエッチングして前記層間絶縁膜を底面とする開口部を形成し、前記開口部底面の前記層間絶縁膜を選択的にエッチングして前記貫通孔を形成する工程であることを特徴とする請求項１または請求項２に記載の半導体装置の製造方法。 The step of forming the through hole includes:
The semiconductor substrate at a position corresponding to the pad electrode is etched to form an opening with the interlayer insulating film as a bottom surface, and the interlayer insulating film on the bottom surface of the opening is selectively etched to form the through hole 3. The method of manufacturing a semiconductor device according to claim 1, wherein 前記半導体基板はシリコン基板であり、
前記貫通孔を形成する工程では、
前記シリコン基板の他方の面にシリコン酸化膜からなるマスクパターンを形成し、当該マスクパターンをマスクに前記シリコン基板の他方の面をエッチングして前記開口部を形成することを特徴とする請求項３に記載の半導体装置の製造方法。 The semiconductor substrate is a silicon substrate;
In the step of forming the through hole,
4. A mask pattern made of a silicon oxide film is formed on the other surface of the silicon substrate, and the opening is formed by etching the other surface of the silicon substrate using the mask pattern as a mask. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. 請求項１〜請求項４の何れか一項に記載の半導体装置のうち、一の前記半導体装置の前記一方の面にある前記パッド電極と、他の前記半導体装置の前記他方の面にある前記貫通電極とを接続するように、少なくとも２個以上の前記半導体装置を積み重ねて集積回路を形成することを特徴とする半導体装置の製造方法。   The semiconductor device according to any one of claims 1 to 4, wherein the pad electrode on the one surface of the one semiconductor device and the other surface of the other semiconductor device are on the other surface. A method of manufacturing a semiconductor device, wherein an integrated circuit is formed by stacking at least two of the semiconductor devices so as to be connected to a through electrode. 半導体基板と、
前記半導体基板の一方の面に設けられた層間絶縁膜と、
前記層間絶縁膜上に設けられたパッド電極と、
前記パッド電極を底面とするように前記半導体基板と前記層間絶縁膜とに設けられた貫通孔と、
前記貫通孔の前記半導体基板からなる側壁と、当該半導体基板の他方の面とに設けられた絶縁膜と、
前記貫通孔に埋め込まれ、当該貫通孔から前記半導体基板の前記他方の面の前記絶縁膜上にかけて設けられた貫通電極とを備えたことを特徴とする半導体装置。 A semiconductor substrate;
An interlayer insulating film provided on one surface of the semiconductor substrate;
A pad electrode provided on the interlayer insulating film;
A through hole provided in the semiconductor substrate and the interlayer insulating film so that the pad electrode is a bottom surface;
An insulating film provided on a side wall made of the semiconductor substrate of the through hole and the other surface of the semiconductor substrate;
A semiconductor device comprising: a through electrode embedded in the through hole and provided on the insulating film on the other surface of the semiconductor substrate from the through hole.
JP2003320880A 2003-09-12 2003-09-12 Semiconductor device and its manufacturing method Pending JP2005093486A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003320880A JP2005093486A (en) 2003-09-12 2003-09-12 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003320880A JP2005093486A (en) 2003-09-12 2003-09-12 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2005093486A true JP2005093486A (en) 2005-04-07

Family

ID=34452715

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003320880A Pending JP2005093486A (en) 2003-09-12 2003-09-12 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2005093486A (en)

Cited By (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006237594A (en) * 2005-01-31 2006-09-07 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof
JP2007142309A (en) * 2005-11-22 2007-06-07 Seiko Epson Corp Method for manufacturing semiconductor device
JP2008022528A (en) * 2006-06-12 2008-01-31 Epson Toyocom Corp Probe contacting electrode and electronic device
JP2008034508A (en) * 2006-07-27 2008-02-14 Sanyo Electric Co Ltd Semiconductor device and its manufacturing method
EP1913631A2 (en) * 2005-08-11 2008-04-23 Ziptronix, Inc. 3d ic method and device
JP2008098498A (en) * 2006-10-13 2008-04-24 Seiko Epson Corp Semiconductor device, manufacturing method of the semiconductor device, circuit board and electronic apparatus
JP2008294159A (en) * 2007-05-23 2008-12-04 Denso Corp Manufacturing method of semiconductor device and semiconductor device
JP2008305897A (en) * 2007-06-06 2008-12-18 Renesas Technology Corp Semiconductor device and manufacturing method thereof
JP2009295676A (en) * 2008-06-03 2009-12-17 Oki Semiconductor Co Ltd Semiconductor device and production method thereof
JP2010103433A (en) * 2008-10-27 2010-05-06 Toshiba Corp Semiconductor device, and method of manufacturing the same
EP2183770A2 (en) * 2007-07-31 2010-05-12 Tessera, Inc. Semiconductor packaging process using through silicon vias
JP2010141932A (en) * 2006-06-12 2010-06-24 Epson Toyocom Corp Method of manufacturing probe contacting electrode for electronic device
US8004090B2 (en) 2007-10-29 2011-08-23 Elpida Memory, Inc Semiconductor device and method for manufacturing the same
JP2011171607A (en) * 2010-02-19 2011-09-01 Sony Corp Semiconductor device and method of testing through electrode
JP2012505557A (en) * 2008-10-16 2012-03-01 マイクロン テクノロジー， インク． Semiconductor circuit board having integrated vias and via terminals, and related systems and methods
JP2012134526A (en) * 2012-02-22 2012-07-12 Renesas Electronics Corp Semiconductor device
US8310036B2 (en) 2007-03-05 2012-11-13 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8432045B2 (en) 2010-11-15 2013-04-30 Tessera, Inc. Conductive pads defined by embedded traces
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8653644B2 (en) 2006-11-22 2014-02-18 Tessera, Inc. Packaged semiconductor chips with array
US8704347B2 (en) 2006-11-22 2014-04-22 Tessera, Inc. Packaged semiconductor chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
WO2021208832A1 (en) * 2020-04-16 2021-10-21 长鑫存储技术有限公司 Semiconductor structure and method for forming same
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11728313B2 (en) 2018-06-13 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Offset pads over TSV
US11804377B2 (en) 2018-04-05 2023-10-31 Adeia Semiconductor Bonding Technologies, Inc. Method for preparing a surface for direct-bonding
US11929347B2 (en) 2020-10-20 2024-03-12 Adeia Semiconductor Technologies Llc Mixed exposure for large die
US12125784B2 (en) 2023-08-17 2024-10-22 Adeia Semiconductor Bonding Technologies Inc. Interconnect structures

Cited By (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006237594A (en) * 2005-01-31 2006-09-07 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof
US11515202B2 (en) 2005-08-11 2022-11-29 Adeia Semiconductor Bonding Technologies Inc. 3D IC method and device
US8709938B2 (en) 2005-08-11 2014-04-29 Ziptronix, Inc. 3D IC method and device
US11011418B2 (en) 2005-08-11 2021-05-18 Invensas Bonding Technologies, Inc. 3D IC method and device
EP1913631A2 (en) * 2005-08-11 2008-04-23 Ziptronix, Inc. 3d ic method and device
US8389378B2 (en) 2005-08-11 2013-03-05 Ziptronix, Inc. 3D IC method and device
US9171756B2 (en) 2005-08-11 2015-10-27 Ziptronix, Inc. 3D IC method and device
US10147641B2 (en) 2005-08-11 2018-12-04 Invensas Bonding Technologies, Inc. 3D IC method and device
EP1913631A4 (en) * 2005-08-11 2011-10-05 Ziptronix Inc 3d ic method and device
US9716033B2 (en) 2005-08-11 2017-07-25 Ziptronix, Inc. 3D IC method and device
JP2013058781A (en) * 2005-08-11 2013-03-28 Ziptronix Inc Three dimensional ic method and device
US11289372B2 (en) 2005-08-11 2022-03-29 Invensas Bonding Technologies, Inc. 3D IC method and device
JP2007142309A (en) * 2005-11-22 2007-06-07 Seiko Epson Corp Method for manufacturing semiconductor device
JP2010141932A (en) * 2006-06-12 2010-06-24 Epson Toyocom Corp Method of manufacturing probe contacting electrode for electronic device
JP2008022528A (en) * 2006-06-12 2008-01-31 Epson Toyocom Corp Probe contacting electrode and electronic device
JP2008034508A (en) * 2006-07-27 2008-02-14 Sanyo Electric Co Ltd Semiconductor device and its manufacturing method
JP2008098498A (en) * 2006-10-13 2008-04-24 Seiko Epson Corp Semiconductor device, manufacturing method of the semiconductor device, circuit board and electronic apparatus
US8653644B2 (en) 2006-11-22 2014-02-18 Tessera, Inc. Packaged semiconductor chips with array
US8704347B2 (en) 2006-11-22 2014-04-22 Tessera, Inc. Packaged semiconductor chips
US9548254B2 (en) 2006-11-22 2017-01-17 Tessera, Inc. Packaged semiconductor chips with array
US9070678B2 (en) 2006-11-22 2015-06-30 Tessera, Inc. Packaged semiconductor chips with array
US8310036B2 (en) 2007-03-05 2012-11-13 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8405196B2 (en) 2007-03-05 2013-03-26 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8735205B2 (en) 2007-03-05 2014-05-27 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
JP2008294159A (en) * 2007-05-23 2008-12-04 Denso Corp Manufacturing method of semiconductor device and semiconductor device
JP2008305897A (en) * 2007-06-06 2008-12-18 Renesas Technology Corp Semiconductor device and manufacturing method thereof
US8324736B2 (en) 2007-06-06 2012-12-04 Renesas Electronics Corporation Manufacturing process and structure of through silicon via
US7973415B2 (en) 2007-06-06 2011-07-05 Renesas Electronics Corporation Manufacturing process and structure of through silicon via
EP2183770A2 (en) * 2007-07-31 2010-05-12 Tessera, Inc. Semiconductor packaging process using through silicon vias
US8193615B2 (en) 2007-07-31 2012-06-05 DigitalOptics Corporation Europe Limited Semiconductor packaging process using through silicon vias
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
EP2183770A4 (en) * 2007-07-31 2010-08-04 Tessera Inc Semiconductor packaging process using through silicon vias
US8004090B2 (en) 2007-10-29 2011-08-23 Elpida Memory, Inc Semiconductor device and method for manufacturing the same
JP2009295676A (en) * 2008-06-03 2009-12-17 Oki Semiconductor Co Ltd Semiconductor device and production method thereof
US8629057B2 (en) 2008-10-16 2014-01-14 Micron Technology, Inc. Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
US9935085B2 (en) 2008-10-16 2018-04-03 Micron Technology, Inc. Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
US9508628B2 (en) 2008-10-16 2016-11-29 Micron Technology, Inc. Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
JP2012505557A (en) * 2008-10-16 2012-03-01 マイクロン テクノロジー， インク． Semiconductor circuit board having integrated vias and via terminals, and related systems and methods
JP2010103433A (en) * 2008-10-27 2010-05-06 Toshiba Corp Semiconductor device, and method of manufacturing the same
JP2011171607A (en) * 2010-02-19 2011-09-01 Sony Corp Semiconductor device and method of testing through electrode
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8809190B2 (en) 2010-09-17 2014-08-19 Tessera, Inc. Multi-function and shielded 3D interconnects
US9847277B2 (en) 2010-09-17 2017-12-19 Tessera, Inc. Staged via formation from both sides of chip
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US10354942B2 (en) 2010-09-17 2019-07-16 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US9355948B2 (en) 2010-09-17 2016-05-31 Tessera, Inc. Multi-function and shielded 3D interconnects
US9362203B2 (en) 2010-09-17 2016-06-07 Tessera, Inc. Staged via formation from both sides of chip
US8772908B2 (en) 2010-11-15 2014-07-08 Tessera, Inc. Conductive pads defined by embedded traces
US8432045B2 (en) 2010-11-15 2013-04-30 Tessera, Inc. Conductive pads defined by embedded traces
US9368476B2 (en) 2010-12-02 2016-06-14 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US9620437B2 (en) 2010-12-02 2017-04-11 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US9269692B2 (en) 2010-12-02 2016-02-23 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9099296B2 (en) 2010-12-02 2015-08-04 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages with plural active chips
US8796828B2 (en) 2010-12-08 2014-08-05 Tessera, Inc. Compliant interconnects in wafers
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US9224649B2 (en) 2010-12-08 2015-12-29 Tessera, Inc. Compliant interconnects in wafers
JP2012134526A (en) * 2012-02-22 2012-07-12 Renesas Electronics Corp Semiconductor device
US11830838B2 (en) 2015-08-25 2023-11-28 Adeia Semiconductor Bonding Technologies Inc. Conductive barrier direct hybrid bonding
US11264345B2 (en) 2015-08-25 2022-03-01 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10262963B2 (en) 2015-08-25 2019-04-16 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11552041B2 (en) 2017-09-24 2023-01-10 Adeia Semiconductor Bonding Technologies Inc. Chemical mechanical polishing for hybrid bonding
US11804377B2 (en) 2018-04-05 2023-10-31 Adeia Semiconductor Bonding Technologies, Inc. Method for preparing a surface for direct-bonding
US11955445B2 (en) 2018-06-13 2024-04-09 Adeia Semiconductor Bonding Technologies Inc. Metal pads over TSV
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11728313B2 (en) 2018-06-13 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Offset pads over TSV
US11749645B2 (en) 2018-06-13 2023-09-05 Adeia Semiconductor Bonding Technologies Inc. TSV as pad
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11756880B2 (en) 2018-10-22 2023-09-12 Adeia Semiconductor Bonding Technologies Inc. Interconnect structures
CN113539946A (en) * 2020-04-16 2021-10-22 长鑫存储技术有限公司 Semiconductor structure and forming method thereof
WO2021208832A1 (en) * 2020-04-16 2021-10-21 长鑫存储技术有限公司 Semiconductor structure and method for forming same
US12033920B2 (en) 2020-04-16 2024-07-09 Changxin Memory Technologies, Inc. Semiconductor structure and formation method thereof
US11929347B2 (en) 2020-10-20 2024-03-12 Adeia Semiconductor Technologies Llc Mixed exposure for large die
US12125784B2 (en) 2023-08-17 2024-10-22 Adeia Semiconductor Bonding Technologies Inc. Interconnect structures

Similar Documents

Publication Publication Date Title
JP2005093486A (en) Semiconductor device and its manufacturing method
JP4873517B2 (en) Semiconductor device and manufacturing method thereof
JP3918935B2 (en) Manufacturing method of semiconductor device
US7029937B2 (en) Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US7273804B2 (en) Internally reinforced bond pads
EP1391923B1 (en) Manufacturing method of semiconductor device
US7348671B2 (en) Vias having varying diameters and fills for use with a semiconductor device and methods of forming semiconductor device structures including same
US20090093117A1 (en) Method of manufacturing substrate
JP3690407B2 (en) Manufacturing method of semiconductor device
CN108155155B (en) Semiconductor structure and forming method thereof
US7682957B2 (en) Method of forming pad and fuse in semiconductor device
US7135762B2 (en) Semiconductor device, stacked semiconductor device, methods of manufacturing them, circuit board, and electronic instrument
JP2007294821A (en) Wiring board and manufacturing method thereof
JP4322181B2 (en) Manufacturing method of semiconductor device
JP4803964B2 (en) Electrode structure
JP4248355B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2006049557A (en) Semiconductor device
US20120119371A1 (en) Method of fabricating semiconductor device and semiconductor device
JP4182340B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
JP2000307003A (en) Fabrication of semiconductor device
KR100395907B1 (en) Method for forming the line of semiconductor device
JP2000332017A (en) Semiconductor device and manufacture thereof
KR100905187B1 (en) Method for fabricating contact plug of semiconductor device
KR20060135242A (en) Method of forming a trench in a semiconductor device
JP2007049097A (en) Semiconductor