JP2007049097A - Semiconductor - Google Patents

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JP2007049097A
JP2007049097A JP2005234851A JP2005234851A JP2007049097A JP 2007049097 A JP2007049097 A JP 2007049097A JP 2005234851 A JP2005234851 A JP 2005234851A JP 2005234851 A JP2005234851 A JP 2005234851A JP 2007049097 A JP2007049097 A JP 2007049097A
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insulating film
lower wiring
wiring
semiconductor device
film
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JP2005234851A
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Japanese (ja)
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Hisahiro Shiraishi
尚寛 白石
Yosuke Fujito
陽介 藤戸
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Mitsumi Electric Co Ltd
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Mitsumi Electric Co Ltd
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Priority to JP2005234851A priority Critical patent/JP2007049097A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125—Reinforcing structures
    • H01L2224/02126—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

<P>PROBLEM TO BE SOLVED: To prevent damage of an insulating film provided just under a bonding pad, related to a semiconductor device provided with the bonding pad of a two-layer structure comprising a lower wiring and an upper wiring. <P>SOLUTION: The device comprises an insulating film 12 provided to a semiconductor substrate 11, the bonding pad 13 comprising the lower wiring 21 and the upper wiring 22 provided on the insulating film 12, and an insulating film 15 provided between the upper wiring 22 and the insulating film 12. The insulating film 15 is so provided as not to overlap with an upper surface 21A of the lower wiring 21. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置に係り、特に、下部配線と上部配線とからなる２層構造のボンディングパッドを備えた半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a two-layer bonding pad made up of a lower wiring and an upper wiring.

半導体装置は、外部接続端子としてのボンディングパッドを有しており、ボンディングパッドには、金等のワイヤが接続される。このような半導体装置をインターポーザ等の基板に接続する場合、ボンディングパッドは、ワイヤを介して、基板のパッドと電気的に接続される。このような、ボンディングパッドには、下部配線と上部配線とを有する２層構造のものがある（図１１参照）。   The semiconductor device has a bonding pad as an external connection terminal, and a wire such as gold is connected to the bonding pad. When such a semiconductor device is connected to a substrate such as an interposer, the bonding pad is electrically connected to the pad of the substrate through a wire. Such a bonding pad has a two-layer structure having a lower wiring and an upper wiring (see FIG. 11).

図１１は、ボンディングパッドを備えた従来の半導体装置の断面図である。図１１において、Ａは上部配線１１１のワイヤ１０８が接続される領域（以下、「ワイヤ接続領域Ａ」とする）を示している。   FIG. 11 is a cross-sectional view of a conventional semiconductor device having a bonding pad. In FIG. 11, A indicates a region to which the wire 108 of the upper wiring 111 is connected (hereinafter referred to as “wire connection region A”).

図１１を参照して、従来の半導体装置１００について説明する。   A conventional semiconductor device 100 will be described with reference to FIG.

半導体装置１００は、半導体基板１０１と、絶縁膜１０２，１０５と、ボンディングパッド１０３と、保護膜１０６とを有する。半導体基板１０１の上面１０１Ａ側には、トランジスタ等の半導体素子（図示せず）が形成されている。絶縁膜１０２は、半導体基板１０１の上面１０１Ａを覆うように設けられている。絶縁膜１０５は、絶縁膜１０５の一部が下部配線１１０の上面１１０Ａと重なるように、絶縁膜１０２上に設けられている。絶縁膜１０５は、下部配線１１０の上面１１０Ａの中央部を露出する開口部１０５Ａを有する。   The semiconductor device 100 includes a semiconductor substrate 101, insulating films 102 and 105, a bonding pad 103, and a protective film 106. A semiconductor element (not shown) such as a transistor is formed on the upper surface 101A side of the semiconductor substrate 101. The insulating film 102 is provided so as to cover the upper surface 101 </ b> A of the semiconductor substrate 101. The insulating film 105 is provided on the insulating film 102 so that a part of the insulating film 105 overlaps the upper surface 110 </ b> A of the lower wiring 110. The insulating film 105 has an opening 105 </ b> A that exposes the central portion of the upper surface 110 </ b> A of the lower wiring 110.

ボンディングパッド１０３は、下部配線１１０と、上部配線１１１とから構成されている。下部配線１１０は、絶縁膜１０２上に設けられている。上部配線１１１は、開口部１０５Ａに露出された下部配線１１０上、及び絶縁膜１０５上に設けられている。上部配線１１１は、ワイヤ接続領域Ａを有する。ワイヤ接続領域Ａには、ワイヤ１０８の先端のボール部１０９が接続される。   The bonding pad 103 is composed of a lower wiring 110 and an upper wiring 111. The lower wiring 110 is provided on the insulating film 102. The upper wiring 111 is provided on the lower wiring 110 exposed in the opening 105 </ b> A and the insulating film 105. The upper wiring 111 has a wire connection region A. In the wire connection area A, the ball portion 109 at the tip of the wire 108 is connected.

保護膜１０６は、上部配線１１１及び絶縁膜１０５上に設けられており、上部配線１１１のワイヤ接続領域Ａを露出する開口部１０６Ａを有する（例えば、特許文献１参照。）。
特開平６−５３２７０号公報 The protective film 106 is provided on the upper wiring 111 and the insulating film 105, and has an opening 106A that exposes the wire connection region A of the upper wiring 111 (see, for example, Patent Document 1).
JP-A-6-53270

図１２は、ワイヤ接続領域の中心からずれてワイヤが接続された従来の半導体装置の断面図である。図１２において、図１１に示した半導体装置１００と同一構成部分には同一符号を付す。また、図１２において、Ｂは下部配線１１０上に設けられた絶縁膜１０５により形成される段差（以下、「段差部Ｂ」とする）を示している。   FIG. 12 is a cross-sectional view of a conventional semiconductor device in which wires are connected with a deviation from the center of the wire connection region. 12, the same components as those of the semiconductor device 100 shown in FIG. In FIG. 12, B indicates a step formed by the insulating film 105 provided on the lower wiring 110 (hereinafter referred to as “stepped portion B”).

図１２に示すように、ワイヤボンディング装置の性能によっては、ワイヤ１０８のボール部１０９がワイヤ接続領域Ａの中心からずれて、ボール部１０９がワイヤ接続領域Ａと保護膜１０６との両方に接触する場合がある。このような場合でも、ボール部１０９とワイヤ接続領域Ａとは電気的に接続されているため、ワイヤ１０８と半導体装置１００との間の電気的な接続に関して問題はない。しかし、ボール部１０９が保護膜１０６と接触した際の衝撃が段差部Ｂ（特に、下部配線１１０の端部）に集中するため、ボンディングパッド１０３の下層に位置する絶縁膜１０２が破損してクラックＣが発生してしまうという問題があった。   As shown in FIG. 12, depending on the performance of the wire bonding apparatus, the ball portion 109 of the wire 108 is displaced from the center of the wire connection region A, and the ball portion 109 contacts both the wire connection region A and the protective film 106. There is a case. Even in such a case, since the ball portion 109 and the wire connection region A are electrically connected, there is no problem with respect to the electrical connection between the wire 108 and the semiconductor device 100. However, since the impact when the ball portion 109 comes into contact with the protective film 106 is concentrated on the step portion B (particularly, the end portion of the lower wiring 110), the insulating film 102 located under the bonding pad 103 is damaged and cracked. There was a problem that C was generated.

また、クラックＣが発生した場合には、半導体基板１０１に形成された半導体素子（図示せず）の性能に悪影響を及ぼしてしまうという問題があった。   Moreover, when the crack C generate | occur | produced, there existed a problem of having a bad influence on the performance of the semiconductor element (not shown) formed in the semiconductor substrate 101. FIG.

そこで、本発明は上記の点に鑑みてなされたものであり、ボンディングパッドの下層に設けられた絶縁膜の破損を防止することのできる半導体装置を提供することを目的とする。   Accordingly, the present invention has been made in view of the above points, and an object thereof is to provide a semiconductor device capable of preventing damage to an insulating film provided in a lower layer of a bonding pad.

本発明の一観点によれば、半導体基板（１１）上に設けられた第１の絶縁膜（１２）と、前記第１の絶縁膜（１２）上に設けられた下部配線（２１）と、該下部配線（２１）上に設けられた上部配線（２２）とを有するボンディングパッド（１３）と、前記第１の絶縁膜（１２）上に設けられた第２の絶縁膜（１５）とを備えた半導体装置（１０）において、前記第２の絶縁膜（１５）を前記下部配線（２１）の上面（２１Ａ）と重ならないように配置したことを特徴とする半導体装置が提供される。   According to one aspect of the present invention, a first insulating film (12) provided on a semiconductor substrate (11), a lower wiring (21) provided on the first insulating film (12), A bonding pad (13) having an upper wiring (22) provided on the lower wiring (21) and a second insulating film (15) provided on the first insulating film (12). In the semiconductor device (10) provided, the semiconductor device is provided in which the second insulating film (15) is arranged so as not to overlap the upper surface (21A) of the lower wiring (21).

本発明によれば、第２の絶縁膜（１５）を下部配線（２１）の上面（２１Ａ）と重ならないように配置することにより、下部配線（２１）の端部に第２の絶縁層（１５）による段差が形成されないため、ボンディングパッド（１３）にワイヤ（１８）を接続した際の下部配線（２１）の端部における衝撃が緩和される。これにより下部配線（２１）の直下に設けられた第１の絶縁膜（１２）の破損を防止することができる。   According to the present invention, the second insulating film (15) is disposed so as not to overlap the upper surface (21A) of the lower wiring (21), so that the second insulating layer (15) is formed on the end of the lower wiring (21). 15), the step at the end of the lower wiring (21) when the wire (18) is connected to the bonding pad (13) is mitigated. Thereby, damage to the first insulating film (12) provided immediately below the lower wiring (21) can be prevented.

本発明は、ボンディングパッドの直下に設けられた絶縁膜の破損を防止することができる。   The present invention can prevent damage to an insulating film provided immediately below a bonding pad.

次に、図面に基づいて本発明の実施の形態を説明する。   Next, embodiments of the present invention will be described with reference to the drawings.

図１は、本発明の実施の形態に係る半導体装置の断面図であり、図２は、図１に示した半導体装置の平面図である。図１において、Ｄは上部配線２２のワイヤ１８が接続される領域（以下、「ワイヤ接続領域Ｄ」とする）、Ｅは溝部２３の幅（以下、「幅Ｅ」とする）、をそれぞれ示している。   FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view of the semiconductor device shown in FIG. In FIG. 1, D indicates a region (hereinafter referred to as “wire connection region D”) to which the wire 18 of the upper wiring 22 is connected, and E indicates a width of the groove portion 23 (hereinafter referred to as “width E”). ing.

図１及び図２を参照して、本発明の実施の形態に係る半導体装置１０について説明する。   A semiconductor device 10 according to an embodiment of the present invention will be described with reference to FIGS.

半導体装置１０は、半導体基板１１と、絶縁膜１２，１５と、ボンディングパッド１３と、保護膜１７とを有する。半導体基板１１には、例えば、Ｓｉ基板やＧａＡｓ基板等を用いることができる。半導体基板１１の上面１１Ａ側には、図示していないトランジスタ等の半導体素子が形成されている。   The semiconductor device 10 includes a semiconductor substrate 11, insulating films 12 and 15, a bonding pad 13, and a protective film 17. As the semiconductor substrate 11, for example, a Si substrate or a GaAs substrate can be used. On the upper surface 11A side of the semiconductor substrate 11, a semiconductor element such as a transistor (not shown) is formed.

絶縁膜１２（第１の絶縁膜）は、図示していない半導体素子を覆うように半導体基板１１の上面１１Ａに設けられている。絶縁膜１２としては、ＢＰＳＧ膜を用いることができる。ＢＰＳＧ膜は、例えば、常圧ＣＶＤ法により形成することができる。   The insulating film 12 (first insulating film) is provided on the upper surface 11A of the semiconductor substrate 11 so as to cover a semiconductor element (not shown). As the insulating film 12, a BPSG film can be used. The BPSG film can be formed by, for example, an atmospheric pressure CVD method.

絶縁膜１５（第２の絶縁膜）は、絶縁膜１２上に設けられている。絶縁膜１５は、下部配線２１の上面２１Ａと重ならないよう、下部配線２１の側壁２１Ｂから離間した位置に配置されている。   The insulating film 15 (second insulating film) is provided on the insulating film 12. The insulating film 15 is disposed at a position separated from the side wall 21 </ b> B of the lower wiring 21 so as not to overlap the upper surface 21 </ b> A of the lower wiring 21.

このように、絶縁膜１５を下部配線２１の上面２１Ａと重ならないよう、下部配線２１の側壁２１Ｂから離間した位置に配置することにより、下部配線２１の端部（側壁２１Ｂ付近）に絶縁層１５による段差がなくなるため、ボンディングパッド１３にワイヤ１８を接続した際の下部配線２１の側壁２１Ｂ付近における衝撃が緩和される。これにより下部配線２１の直下に設けられた絶縁膜１２が破損することを防止できる。   In this way, the insulating film 15 is arranged at a position separated from the side wall 21B of the lower wiring 21 so as not to overlap the upper surface 21A of the lower wiring 21, so that the insulating layer 15 is formed at the end of the lower wiring 21 (near the side wall 21B). Therefore, the impact in the vicinity of the side wall 21B of the lower wiring 21 when the wire 18 is connected to the bonding pad 13 is mitigated. As a result, it is possible to prevent the insulating film 12 provided immediately below the lower wiring 21 from being damaged.

絶縁膜１５としては、例えば、ＳｉＯ2膜、ＳＯＧ（Spin On Glass）膜、或いはＳｉＯ2膜とＳＯＧ膜との積層膜を用いることができる。この場合、ＳｉＯ2膜は、例えば、ＣＶＤ法により形成することができる。 As the insulating film 15, for example, a SiO 2 film, a SOG (Spin On Glass) film, or a laminated film of a SiO 2 film and an SOG film can be used. In this case, the SiO 2 film can be formed by, for example, a CVD method.

絶縁膜１５と下部配線２１との間には、絶縁膜１５の側壁１５Ａ、下部配線２１の側壁２１Ｂ、及び絶縁膜１２の上面により溝部２３が形成されている。この溝部２３の幅Ｅは、溝部２３に上部配線２２となる導電金属を埋め込むことが可能な大きさであればよい。   A groove 23 is formed between the insulating film 15 and the lower wiring 21 by the side wall 15 A of the insulating film 15, the side wall 21 B of the lower wiring 21, and the upper surface of the insulating film 12. The width E of the groove 23 may be a size that allows the conductive metal to be embedded in the groove 23 to be the upper wiring 22.

ボンディングパッド１３は、２層構造とされており、下部配線２１と、上部配線２２とを有する。下部配線２１は、絶縁膜１５から離間した絶縁膜１２上に設けられている。上部配線２２は、下部配線２１上から絶縁膜１５上に亘って設けられており、溝部２３を充填している。上部配線２２は、下部配線２１の上面２１Ａを覆っており、上部配線２２の側壁２２Ｂは、下部配線２１の側壁２１Ｂよりも外側に配置されている。上部配線２２は、ワイヤ１８のボール部１９が接続されるワイヤ接続領域Ｄを有する。ワイヤ接続領域Ｄの面積は、下部配線２１の上面２１Ａの面積よりも大きくなるように設定されている。   The bonding pad 13 has a two-layer structure, and has a lower wiring 21 and an upper wiring 22. The lower wiring 21 is provided on the insulating film 12 separated from the insulating film 15. The upper wiring 22 is provided from the lower wiring 21 to the insulating film 15 and fills the groove 23. The upper wiring 22 covers the upper surface 21A of the lower wiring 21, and the side wall 22B of the upper wiring 22 is disposed outside the side wall 21B of the lower wiring 21. The upper wiring 22 has a wire connection region D to which the ball portion 19 of the wire 18 is connected. The area of the wire connection region D is set to be larger than the area of the upper surface 21A of the lower wiring 21.

このように、上部配線２２を下部配線２１の上面２１Ａを覆うように設け、上部配線２２の側壁２２Ｂを下部配線２１の側壁２１Ｂよりも外側に配置して、ワイヤ接続領域Ｄの面積を大きくすることにより、ワイヤ１８のボール部１９全体と上部配線２２とが接触する確率が高くなるため、ワイヤ１８とボンディングパッド１３との間の接続信頼性を向上させることができる。   As described above, the upper wiring 22 is provided so as to cover the upper surface 21A of the lower wiring 21, and the side wall 22B of the upper wiring 22 is disposed outside the side wall 21B of the lower wiring 21, thereby increasing the area of the wire connection region D. As a result, the probability that the entire ball portion 19 of the wire 18 and the upper wiring 22 come into contact with each other increases, so that the connection reliability between the wire 18 and the bonding pad 13 can be improved.

なお、下部配線２１及び上部配線２２の材料としては、導電金属を用いることができ、導電金属としては、例えば、ＡｌやＡｌ合金を用いることができる。   In addition, as a material of the lower wiring 21 and the upper wiring 22, a conductive metal can be used. As the conductive metal, for example, Al or an Al alloy can be used.

保護膜１７は、上部配線２２の端部を覆うよう絶縁膜１５上に設けられている。保護膜１７は、上部配線２２のワイヤ接続領域Ｄを露出する開口部２４を有する。保護膜１７としては、例えば、ＳｉＮ膜を用いることができる。ＳｉＮ膜は、例えば、プラズマＣＶＤ法により形成することができる。   The protective film 17 is provided on the insulating film 15 so as to cover the end of the upper wiring 22. The protective film 17 has an opening 24 that exposes the wire connection region D of the upper wiring 22. As the protective film 17, for example, a SiN film can be used. The SiN film can be formed by, for example, a plasma CVD method.

本実施の形態の半導体装置によれば、絶縁膜１５を下部配線２１の側壁２１Ｂから離間した絶縁膜１２上に配置することにより、下部配線２１の端部（側壁２１Ｂ付近）に絶縁層１５による段差がなくなるため、ボンディングパッド１３にワイヤ１８が接続された際の衝撃が緩和されるので、下部配線２１の直下に設けられた絶縁膜１２が破損することを防止できる。   According to the semiconductor device of the present embodiment, the insulating film 15 is disposed on the insulating film 12 separated from the side wall 21B of the lower wiring 21, so that the end portion (near the side wall 21B) of the lower wiring 21 is formed by the insulating layer 15. Since the step is eliminated, the impact when the wire 18 is connected to the bonding pad 13 is mitigated, so that the insulating film 12 provided immediately below the lower wiring 21 can be prevented from being damaged.

また、上部配線２２を下部配線２１の上面２１Ａを覆うように設け、上部配線２２の側壁２２Ｂを下部配線２１の側壁２１Ｂよりも外側に配置することにより、ワイヤ接続領域Ｄの面積を大きくして、ワイヤ１８とボンディングパッド１３との間の接続信頼性を向上させることができる。   Further, the upper wiring 22 is provided so as to cover the upper surface 21A of the lower wiring 21, and the side wall 22B of the upper wiring 22 is arranged outside the side wall 21B of the lower wiring 21, thereby increasing the area of the wire connection region D. The connection reliability between the wire 18 and the bonding pad 13 can be improved.

図３〜図９は、本発明の実施の形態に係る半導体装置の製造工程を示す図であり、図１０は、図６に示した構造体の平面図である。なお、図３〜図１０において、先に説明した半導体装置１０と同一構成部分には同一符号を付す。   3 to 9 are views showing a manufacturing process of the semiconductor device according to the embodiment of the present invention, and FIG. 10 is a plan view of the structure shown in FIG. 3 to 10, the same components as those of the semiconductor device 10 described above are denoted by the same reference numerals.

次に、図３〜図１０を参照して、本発明の実施の形態に係る半導体装置１０の製造方法について説明する。   Next, a method for manufacturing the semiconductor device 10 according to the embodiment of the present invention will be described with reference to FIGS.

始めに、図３に示すように、半導体素子（図示せず）が形成された半導体基板１１の上面１１Ａに、絶縁層１２と、下部配線２１とを順次形成する。具体的には、例えば、半導体素子（図示せず）が形成されたシリコンからなる半導体基板１１上に、常圧ＣＶＤ法によりＢＰＳＧ膜を成膜して絶縁層１２を形成する。次いで、スパッタ法により、ＢＰＳＧ膜上にＡｌ膜を成膜し、次いで、Ａｌ膜上に下部配線２１の形状にパターニングしたレジスト層を形成し、その後、レジスト層をマスクとするドライエッチング法によりＡｌ膜をエッチングすることで下部配線２１を形成する。レジスト層は、下部配線２１を形成後に除去する。   First, as shown in FIG. 3, the insulating layer 12 and the lower wiring 21 are sequentially formed on the upper surface 11A of the semiconductor substrate 11 on which the semiconductor element (not shown) is formed. Specifically, for example, a BPSG film is formed on the semiconductor substrate 11 made of silicon on which a semiconductor element (not shown) is formed by an atmospheric pressure CVD method to form the insulating layer 12. Next, an Al film is formed on the BPSG film by sputtering, a resist layer patterned in the shape of the lower wiring 21 is formed on the Al film, and then Al is formed by dry etching using the resist layer as a mask. The lower wiring 21 is formed by etching the film. The resist layer is removed after the lower wiring 21 is formed.

次いで、図４に示すように、図３に示した構造体の上面を覆うように絶縁膜１５を形成し、続いて、絶縁膜１５上に開口部３１Ａを有したレジスト層３１を形成する。開口部３１Ａは、下部配線２１が形成された領域と、溝部２３（図１参照）が形成される領域とを露出する開口部である。   Next, as shown in FIG. 4, the insulating film 15 is formed so as to cover the upper surface of the structure shown in FIG. 3, and subsequently, a resist layer 31 having an opening 31 </ b> A is formed on the insulating film 15. The opening 31A is an opening that exposes a region where the lower wiring 21 is formed and a region where the groove 23 (see FIG. 1) is formed.

絶縁膜１５としては、例えば、ＳｉＯ2膜と、ＳＯＧ（Spin On Glass）膜と、ＳｉＯ2膜とが順次積層された積層膜を用いることができる。この場合、絶縁膜１５は、例えば、ＣＶＤ法によりＳｉＯ2膜を成膜し、続いて、塗布法によりＳＯＧ（Spin On Glass）膜を成膜し、その後、ＣＶＤ法によりＳｉＯ2膜を成膜することで形成する。 As the insulating film 15, for example, a laminated film in which an SiO 2 film, an SOG (Spin On Glass) film, and an SiO 2 film are sequentially laminated can be used. In this case, the insulating film 15 is formed, for example, by forming a SiO 2 film by a CVD method, subsequently forming an SOG (Spin On Glass) film by a coating method, and then forming a SiO 2 film by a CVD method. To form.

次いで、図５に示すように、ドライエッチング法により、開口部３１Ａに露出された絶縁膜１５をエッチングする。これにより、下部配線２１を露出すると共に、絶縁膜１５の側壁１５Ａ、下部配線２１の側壁２１Ｂ、及び絶縁膜１２の上面からなる溝部２３を形成する。溝部２３の幅Ｅは、溝部２３に上部配線２２となる導電金属を充填可能な大きさであればよい。   Next, as shown in FIG. 5, the insulating film 15 exposed in the opening 31A is etched by dry etching. Thereby, the lower wiring 21 is exposed, and the side wall 15 A of the insulating film 15, the side wall 21 B of the lower wiring 21, and the groove portion 23 including the upper surface of the insulating film 12 are formed. The width E of the groove 23 may be a size that can fill the groove 23 with a conductive metal that becomes the upper wiring 22.

次いで、図６に示すように、レジスト層３１をレジスト剥離液により除去する。なお、溝部２３は、図１０に示すように、下部配線２１の側壁２１Ｂを囲むように形成する。   Next, as shown in FIG. 6, the resist layer 31 is removed with a resist stripping solution. In addition, the groove part 23 is formed so that the side wall 21B of the lower wiring 21 may be enclosed as shown in FIG.

次いで、図７に示すように、図６に示した構造体上に上部配線２２を形成する。具体的には、例えば、図６に示した構造体上に、スパッタ法によりＡｌ膜を成膜し、次いで、Ａｌ膜上に上部配線２２の形状にパターニングしたレジスト層を形成し、その後、レジスト層をマスクとするドライエッチング法によりＡｌ膜をエッチングすることで上部配線２２を形成する。これにより、下部配線２１と上部配線２２とよりなる２層構造のボンディングパッド１３が形成される。レジスト層は、上部配線２２を形成後に除去する。   Next, as shown in FIG. 7, the upper wiring 22 is formed on the structure shown in FIG. Specifically, for example, an Al film is formed on the structure shown in FIG. 6 by sputtering, and then a resist layer patterned in the shape of the upper wiring 22 is formed on the Al film. The upper wiring 22 is formed by etching the Al film by a dry etching method using the layer as a mask. Thereby, the bonding pad 13 having a two-layer structure including the lower wiring 21 and the upper wiring 22 is formed. The resist layer is removed after the upper wiring 22 is formed.

次いで、図８に示すように、図７に示した構造体上を覆うように保護膜１７を形成し、続いて、保護膜１７上に開口部３３Ａを有したレジスト層３３を形成する。開口部３３Ａは、上部配線２２のワイヤ接続領域Ｄ上に位置する保護膜１７を露出する。   Next, as shown in FIG. 8, a protective film 17 is formed so as to cover the structure shown in FIG. 7, and subsequently, a resist layer 33 having an opening 33 </ b> A is formed on the protective film 17. The opening 33 </ b> A exposes the protective film 17 located on the wire connection region D of the upper wiring 22.

次いで、図９に示すように、レジスト層３３をマスクとするドライエッチング法により、開口部３３Ａに露出された保護膜１７を除去して、保護膜１７に上部配線２２のワイヤ接続領域Ｄを露出する開口部２４を形成する。レジスト層３３は、開口部２４を形成後に除去する。これにより、半導体装置１０が製造される。   Next, as shown in FIG. 9, the protective film 17 exposed in the opening 33 </ b> A is removed by a dry etching method using the resist layer 33 as a mask, and the wire connection region D of the upper wiring 22 is exposed in the protective film 17. The opening 24 to be formed is formed. The resist layer 33 is removed after the opening 24 is formed. Thereby, the semiconductor device 10 is manufactured.

以上、本発明の好ましい実施の形態について詳述したが、本発明はかかる特定の実施の形態に限定されるものではなく、特許請求の範囲内に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。   The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

なお、本実施の形態の半導体装置１０では、ボンディングパッドとして、下部配線２１と上部配線２２とよりなる２層構造のボンディングパッド１３を例に挙げて説明したが、本発明は、２層以上の配線から構成されるボンディングパッドを備えた半導体装置に対しても適用可能である。   In the semiconductor device 10 according to the present embodiment, the bonding pad 13 having the two-layer structure including the lower wiring 21 and the upper wiring 22 has been described as an example of the bonding pad. The present invention can also be applied to a semiconductor device provided with a bonding pad composed of wiring.

本発明は、ボンディングパッドの直下に設けられた絶縁膜の破損を防止することのできる半導体装置に適用できる。   The present invention can be applied to a semiconductor device capable of preventing damage to an insulating film provided immediately below a bonding pad.

本発明の実施の形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on embodiment of this invention. 図１に示した半導体装置の平面図である。FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. 本発明の実施の形態に係る半導体装置の製造工程を示す図（その１）である。It is FIG. (1) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造工程を示す図（その２）である。It is FIG. (2) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造工程を示す図（その３）である。It is FIG. (The 3) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造工程を示す図（その４）である。FIG. 14 is a diagram (part 4) illustrating a manufacturing step of the semiconductor device according to the embodiment of the present invention; 本発明の実施の形態に係る半導体装置の製造工程を示す図（その５）である。It is FIG. (5) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造工程を示す図（その６）である。It is FIG. (6) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造工程を示す図（その７）である。It is FIG. (The 7) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. 図６に示した構造体の平面図である。It is a top view of the structure shown in FIG. ボンディングパッドを備えた従来の半導体装置の断面図である。It is sectional drawing of the conventional semiconductor device provided with the bonding pad. ワイヤ接続領域の中心からずれてワイヤが接続された従来の半導体装置の断面図である。It is sectional drawing of the conventional semiconductor device with which the wire shifted | deviated from the center of the wire connection area | region and was connected.

符号の説明Explanation of symbols

１０ 半導体装置
１１ 半導体基板
１１Ａ，２１Ａ 上面
１２，１５ 絶縁膜
１３ ボンディングパッド
１５Ａ，２１Ｂ，２２Ｂ 側壁
１７ 保護膜
１８ ワイヤ
１９ ボール部
２１ 下部配線
２２ 上部配線
２３ 溝部
２４，３１Ａ，３３Ａ 開口部
３１，３３ レジスト層
Ｄ ワイヤ接続領域
Ｅ 幅 DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor substrate 11A, 21A Upper surface 12,15 Insulating film 13 Bonding pad 15A, 21B, 22B Side wall 17 Protective film 18 Wire 19 Ball part 21 Lower wiring 22 Upper wiring 23 Groove part 24, 31A, 33A Opening part 31, 33 Resist layer D Wire connection area E Width

Claims (3)

半導体基板上に設けられた第１の絶縁膜と、
前記第１の絶縁膜上に設けられた下部配線と、該下部配線上に設けられた上部配線とを有するボンディングパッドと、
前記第１の絶縁膜上に設けられた第２の絶縁膜とを備えた半導体装置において、
前記第２の絶縁膜を前記下部配線の上面と重ならないように配置したことを特徴とする半導体装置。 A first insulating film provided on the semiconductor substrate;
A bonding pad having a lower wiring provided on the first insulating film and an upper wiring provided on the lower wiring;
In a semiconductor device comprising a second insulating film provided on the first insulating film,
A semiconductor device, wherein the second insulating film is disposed so as not to overlap an upper surface of the lower wiring. 前記第２の絶縁膜は、前記下部配線から離間した位置に設けたことを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the second insulating film is provided at a position separated from the lower wiring. 前記上部配線は、前記下部配線の上面を覆うことを特徴とする請求項１または２記載の半導体装置。   The semiconductor device according to claim 1, wherein the upper wiring covers an upper surface of the lower wiring.
JP2005234851A 2005-08-12 2005-08-12 Semiconductor Pending JP2007049097A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009027098A (en) * 2007-07-23 2009-02-05 Renesas Technology Corp Semiconductor device and manufacturing method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009027098A (en) * 2007-07-23 2009-02-05 Renesas Technology Corp Semiconductor device and manufacturing method therefor

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