JP3918935B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP3918935B2
JP3918935B2 JP2002369393A JP2002369393A JP3918935B2 JP 3918935 B2 JP3918935 B2 JP 3918935B2 JP 2002369393 A JP2002369393 A JP 2002369393A JP 2002369393 A JP2002369393 A JP 2002369393A JP 3918935 B2 JP3918935 B2 JP 3918935B2
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semiconductor device
manufacturing
semiconductor
semiconductor substrate
vertical hole
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JP2004200547A (en
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剛秀 松尾
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器に関する。
【０００２】
【従来の技術】
【０００３】
【特許文献１】
特開２００１−４４１９７号公報
【０００４】
【発明の背景】
３次元実装形態の半導体装置が開発されている。また、３次元実装を可能にするため、半導体チップに貫通電極を形成することが知られている。貫通電極は、半導体チップから突出するように形成する。従来知られている貫通電極は、良好な電気的接続を図ることが難しい形状であった。
【０００５】
本発明の目的は、貫通電極を電気的接続に適した形状に形成することにある。
【０００６】
【課題を解決するための手段】
（１）本発明に係る半導体装置の製造方法は、（ａ）集積回路の少なくとも一部が作り込まれてなる半導体基板の第１の面に、開口部よりも幅の広い底部を有する凹部を形成すること、
（ｂ）前記凹部に、前記底部に対応する先端部を有するように、導電部を設けること、及び、
（ｃ）前記半導体基板の第２の面を削って、前記導電部の前記先端部の少なくとも一部を、前記第２の面から露出させること、
を含む。
本発明によれば、導電部が凹部に対応して形成されるので、その先端部の幅が広くなっており、電気的接続に適した形状の貫通電極を形成することができる。
（２）この半導体装置の製造方法において、
前記凹部の底面を、凹曲面を有するように形成し、
前記導電部の前記先端部を、凸曲面を有するように形成し、
前記凸曲面の少なくとも一部を、前記第２の面から露出させてもよい。
（３）この半導体装置の製造方法において、
前記先端部の一部のみが露出するように、前記第２の面を削ってもよい。
（４）この半導体装置の製造方法において、
前記（ａ）工程は、
（ａ１）前記半導体基板に、底面を有する縦穴を形成すること、及び、
（ａ２）前記縦穴の前記底面から、アンダカットが生じるように前記半導体基板をエッチングすること、
を含んでもよい。
（５）この半導体装置の製造方法は、
前記（ａ１）工程の後であって前記（ａ２）工程の前に、
前記（ａ２）工程で行うエッチングに対して前記縦穴の前記底面よりも耐性が高い膜を、前記縦穴の内壁面に形成することをさらに含んでもよい。
（６）この半導体装置の製造方法は、
前記（ａ）工程の後であって前記（ｂ）工程の前に、
前記凹部の内面に、絶縁膜を形成することをさらに含んでもよい。
（７）この半導体装置の製造方法において、
ＴＥＯＳ−Ｏ３系ＣＶＤによって、前記絶縁膜を形成してもよい。
（８）この半導体装置の製造方法において、
複数の前記半導体基板をスタックすることをさらに含み、
前記複数の半導体基板のうち、上下の半導体基板の前記導電部を電気的に接続してもよい。
（９）本発明に係る半導体ウエハは、第１及び第２の面を有する半導体基板と、
前記半導体基板の前記第２の面よりも前記第１の面に近い位置に少なくとも一部が作り込まれてなる複数の集積回路と、
前記半導体基板の前記第１及び第２の面を貫通する複数の貫通電極と、
を有し、
それぞれの前記貫通電極は、前記第２の面から少なくとも一部が露出する先端部と、前記先端部から前記第１の面の方向に延びる延設部と、を有し、前記先端部は、前記延設部よりも幅が広くなるように形成されてなる。
本発明によれば、貫通電極は、幅の広い先端部を有するので、電気的接続に適した形状になっている。
（１０）この半導体ウエハにおいて、
それぞれの前記貫通電極の前記先端部は、凸曲面を有し、
前記凸曲面の少なくとも一部が、前記第２の面から露出していてもよい。
（１１）この半導体ウエハにおいて、
それぞれの前記貫通電極の前記先端部の一部が露出して他の一部が前記半導体基板内に配置されていてもよい。
（１２）この半導体ウエハは、
それぞれの前記貫通電極と前記半導体基板に形成された貫通穴の内面との間に形成された絶縁膜をさらに有してもよい。
（１３）本発明に係る半導体チップは、第１及び第２の面を有する半導体基板と、
前記半導体基板の前記第２の面よりも前記第１の面に近い位置に少なくとも一部が作り込まれてなる集積回路と、
前記半導体基板の前記第１及び第２の面を貫通する貫通電極と、
を有し、
前記貫通電極は、前記第２の面から少なくとも一部が露出する先端部と、前記先端部から前記第１の面の方向に延びる延設部と、を有し、前記先端部は、前記延設部よりも幅が広くなるように形成されてなる。
本発明によれば、貫通電極は、幅の広い先端部を有するので、電気的接続に適した形状になっている。
（１４）この半導体チップにおいて、
前記貫通電極の前記先端部は、凸曲面を有し、
前記凸曲面の少なくとも一部が、前記第２の面から露出していてもよい。
（１５）この半導体チップにおいて、
前記貫通電極の前記先端部の一部が露出して他の一部が前記半導体基板内に配置されていてもよい。
（１６）この半導体チップは、
前記貫通電極と前記半導体基板に形成された貫通穴の内面との間に形成された絶縁膜をさらに有してもよい。
（１７）本発明に係る半導体装置は、スタックされてなる上記複数の半導体チップを有し、
前記複数の半導体チップのうち上下の半導体チップが、前記貫通電極によって電気的に接続されてなる。
本発明によれば、貫通電極は、幅の広い先端部を有するので、電気的接続に適した形状になっている。
（１８）本発明に係る回路基板は、上記半導体チップが実装されてなる。
（１９）本発明に係る回路基板は、上記半導体装置が実装されてなる。
（２０）本発明に係る電子機器は、上記半導体チップを有する。
（２１）本発明に係る電子機器は、上記半導体装置を有する。
【０００７】
【発明の実施の形態】
以下、本発明の実施の形態を、図面を参照して説明する。
【０００８】
図１（Ａ）〜図４（Ｂ）は、本発明を適用した実施の形態に係る半導体装置（又は半導体チップ・半導体ウエハ）の製造方法を説明する図である。本実施の形態では、図１（Ａ）に示すように、半導体基板１０を使用する。半導体基板１０は、第１及び第２の面１２，１４を有する。第２の面１４は、第１の面１２とは反対の面である。
【０００９】
半導体基板１０には、集積回路（例えばトランジスタやメモリを有する回路）１６の少なくとも一部（一部又は全体）が作り込まれている。半導体基板１０には、複数の集積回路１６のそれぞれの少なくとも一部が作り込まれていてもよいし、１つの集積回路１６の少なくとも一部が作り込まれていてもよい。集積回路１６は、第２の面１４よりも第１の面１２に近い位置に形成されている。
【００１０】
半導体基板１０の第１の面１２には、パッシベーション膜１８が形成されている。パッシベーション膜１８は、例えば、ＳｉＯ2、ＳｉＮ、ポリイミド樹脂などで形成することができる。パッシベーション膜１８は、集積回路１６を覆うように形成されている。
【００１１】
半導体基板１０には、複数のパッド２０が形成されている。パッド２０は、集積回路１６に電気的に接続されていてもよい。各パッド２０は、アルミニウムで形成されていてもよい。パッド２０の表面の形状は特に限定されないが矩形であることが多い。パッド２０は、第２の面１４よりも第１の面１２に近い位置（例えば第１の面１２の上方）に形成されている。パッド２０は、パッシベーション膜１８上に形成してもよい。パッシベーション膜１８上に、パッド２０と、集積回路１６とパッド２０を接続する配線（図示せず）とを形成してもよい。また、図示しない別のパッシベーション膜（絶縁膜）をパッド２０の表面の少なくとも一部を避けて形成してもよい。
【００１２】
図１（Ｂ）に示すように、半導体基板１０に、その第１の面１２から縦穴（又は凹部）２２を形成する。縦穴２２は、半導体基板１０を貫通しないように、すなわち底面を有するように形成する。第１の面１２は、パッド２０が形成された側（集積回路１６が形成された側）の面である。縦穴２２は、集積回路１６の素子及び配線を避けて形成する。パッド２０に貫通穴２４を形成してもよい。貫通穴２４の形成には、エッチング（ドライエッチング又はウェットエッチング）を適用してもよい。エッチングは、リソグラフィ工程によってパターニングされたレジスト（図示せず）を形成した後に行ってもよい。パッド２０の下にパッシベーション膜１８が形成されている場合、これにも貫通穴２６を形成する。パッド２０のエッチングがパッシベーション膜１８で止まる場合、貫通穴２６の形成には、パッド２０のエッチングに使用したエッチャントを別のエッチャントに換えてもよい。その場合、再び、リソグラフィ工程によってパターニングされたレジスト（図示せず）を形成してもよい。
【００１３】
貫通穴２４（及び貫通穴２６）と連通するように、半導体基板１０に縦穴２２を形成する。縦穴２２は、第１の面１２に対して垂直に形成されてもよいし、例えば開口から深さ方向に穴径が小さくなるように、テーパが付けられていてもよい。貫通穴２４（及び貫通穴２６）と縦穴２２を合わせて、縦穴（又は凹部）ということもできる。縦穴２２の形成にも、エッチング（ドライエッチング又はウェットエッチング）を適用することができる。エッチングは、リソグラフィ工程によってパターニングされたレジスト（図示せず）を形成した後に行ってもよい。あるいは、縦穴２２の形成に、レーザ（例えばＣＯ2レーザ、ＹＡＧレーザ等）を使用してもよい。レーザは、貫通穴２４，２６の形成に適用してもよい。一種類のエッチャント又はレーザによって、縦穴２２及び貫通穴２４，２６の形成を連続して行ってもよい。縦穴２２の形成には、サンドブラスト加工を適用してもよい。
【００１４】
図１（Ｃ）に示すように、第１の面１２の上方（例えば、パッシベーション膜１８及びパッド２０上）にレジスト２８を形成してもよい。レジスト２８は、後に行う工程から第１の面１２及びその上方に形成された部材（例えば、パッシベーション膜１８及びパッド２０）を保護するために必要であれば形成する。レジスト２８は、例えばエッチングに対する耐性が半導体基板１０よりも高い材料で形成する。レジスト２８は、縦穴２２が開口するように（縦穴２２を避けて）形成する。
【００１５】
縦穴２２内に膜３０を形成する。膜３０は、縦穴２２の内壁面に形成する。膜３０は、縦穴２２の底面に形成されてもよいし、レジスト２８上に形成されてもよい。膜３０は、エッチングに対する耐性が半導体基板１０よりも高い材料で形成してもよい。例えば、Ｃ４Ｆ８ガスを使用して、炭素で又は炭素を含む材料で膜３０を形成してもよい。
【００１６】
図２（Ａ）に示すように、膜３０の一部を除去する。詳しくは、膜３０のうち縦穴２２の底面に形成された部分を除去する。すなわち、縦穴２２の底面において、半導体基板１０の材料を露出させる。その場合、膜３０のうち縦穴２２の内壁面に形成された部分が除去されないように、膜３０の一部を除去する。その場合、異方性の高いエッチング（エッチング速度の方向依存性が高いエッチング）、詳しくは、垂直方向（縦穴２２の深さ方向）のエッチング速度が水平方向（縦穴２２の内壁面に対向する方向）よりも大きいエッチングを適用してもよい。例えば、高真空下でＳＦ６ガスを導入し、高バイアス電圧を印加して、数秒間のエッチングを行ってもよい。膜３０のうちレジスト２８上の部分が除去されてもよい。
【００１７】
図２（Ｂ）に示すように、縦穴２２の底面から、アンダカットが生じるように半導体基板１０をエッチングする。詳しくは、縦穴２２の底面から、下方向及び横方向にエッチングを進める。例えば、低真空下でＳＦ６ガスを導入し、低バイアス電圧を印加してエッチングを行ってもよい。縦穴２２の内壁面に形成された膜３０によって、縦穴２２の内壁面はエッチングされなくてもよい。縦穴２２の底面をエッチングして、縦穴２２の開口（又は内壁面に囲まれたスペース）よりも幅（例えば直径）の広いスペースを形成する。例えば、上記工程によって、半導体基板１０に、開口部よりも幅の広い底部を有する凹部３２を形成する。凹部３２は、その底面が凹曲面を有するように形成してもよい。図２（Ｃ）に示すように、レジスト２８を除去し、膜３０を除去する。
【００１８】
図３（Ａ）に示すように、凹部３２の内面に、絶縁膜（電気的な絶縁膜）３４を形成する。絶縁膜３４は、凹部３２の内側面上で１μｍ以上の厚みを有するように形成する。このように、側面に厚い膜を形成するには、ＴＥＯＳ−Ｏ３系ＣＶＤを適用してもよい。ＴＥＯＳ−Ｏ３系ＣＶＤは、減圧下で行ってもよいし、常圧下で行ってもよい。絶縁膜３４は、４００℃程度の低温下で表面反応によって形成してもよい。絶縁膜３４は、アニール処理によって膜質を改善してもよい。絶縁膜３４は、凹部３２の底面に形成する。絶縁膜３４は、凹部３２の内壁面に形成する。ただし、絶縁膜３４は、凹部３２を埋め込まないように形成する。すなわち、凹部３２が残るように絶縁膜３４を形成する。また、絶縁膜３４は、その形成後も、開口よりも底部が幅いという凹部３２の特徴が残るように形成する。
【００１９】
絶縁膜３４は、パッシベーション膜１８上に形成してもよい。パッド２０上に絶縁膜３４を形成した場合、図３（Ｂ）に示すように、パッド２０の少なくとも一部を絶縁膜３４から露出させる。例えば、絶縁膜３４のうちパッド２０上の部分を除去する。その除去には、エッチング（ドライエッチング又はウェットエッチング）を適用してもよい。エッチングは、リソグラフィ工程によってパターニングされたレジスト（図示せず）を形成した後に行ってもよい。
【００２０】
図３（Ｃ）に示すように、凹部３２に導電部４０を形成する。導電部４０は、凹部３２の内部形状に対応する形状を有する。凹部３２の内部形状に対応する形状は、凹部３２の内壁面に絶縁膜３４が形成されているので、絶縁膜３４の内側の形状である。導電部４０は、凹部３２の底部に対応する先端部４２を有する。先端部４２は、凹部３２の底部に対応する形状を有する。凹部３２の底部に対応する形状は、絶縁膜３４の内側の形状である。導電部４０は、先端部４２から第１の面１２の方向への延設部４４を有する。導電部４０は、第１の面１２の上方（例えばパッド２０上）に至るように形成してもよい。導電部４０は、例えば絶縁膜３４からの露出部を通じて、パッド２０に電気的に接続されるように形成してもよい。複数の凹部３２に設けられる導電部４０は、第１の面１２の上方（例えばパッド２０上）で相互に接続されていてもよいし、相互に電気的に切断されていてもよい。
【００２１】
凹部３２は、絶縁膜３４の形成後も、その開口よりも底部が広いので、導電部４０はこれに対応した形状になる。したがって、先端部４２は、延設部４４よりも幅（例えば直径）が大きくなっている。凹部３２（例えば絶縁膜３４の内側）の底面が凹曲面を有する場合、導電部４０の先端部４２は、凸曲面を有するように形成される。
【００２２】
導電部４０は、Ｃｕ又はＷなどで形成してもよい。導電部４０はバリア層を含んでもよい。バリア層は、絶縁膜３４上に形成される。すなわち、バリア層は、導電部４０の表面層である。バリア層は、他の材料が、半導体基板１０（例えばＳｉ）に拡散することを防止するものである。バリア層は、その上に形成される層とは異なる材料（例えばＴｉＷ、ＴｉＮ）で形成してもよい。導電部４０は、電解メッキで形成する場合、シード層を含んでもよい。シード層は、バリア層を形成した後に形成する。シード層は、その上に形成される層（例えばＣｕ，Ｗ，ドープドポリシリコン（例えば低温ポリシリコン））と同じ材料（例えばＣｕ）で形成する。
【００２３】
図４（Ａ）に示すように、半導体基板１０を薄型化する。詳しくは、半導体基板１０の第２の面（第１の面１２とは反対の面）１４を削る（研削又は研磨する）。例えば、機械研磨・研削及び化学研磨・研削の少なくとも一つの方法によって、半導体基板１０を削ってもよい。またはエッチングを適用してもよい。エッチングは、ドライエッチング装置を使用して行ってもよい。あるいは、エッチャントは、フッ酸及び硝酸の混合液あるいはフッ酸、硝酸及び酢酸の混合液であってもよい。なお、半導体基板１０の第１の面１２の側に、例えば、ガラス板、樹脂層、樹脂テープ等の補強部材を設けて（例えば接着剤又は接着シートによって貼り付けて）もよい。
【００２４】
導電部４０は、第２の面１４から突出させてもよい。例えば、半導体基板（例えばＳｉ）１０に対するエッチング量が絶縁膜（例えばＳｉＯ2）３４に対するエッチング量よりも多くなる性質のエッチャントによって、第２の面１４をエッチングしてもよい。エッチャントは、ＳＦ6又はＣＦ4又はＣｌ2ガスであってもよい。これにより、絶縁膜３４に覆われた状態で導電部４０を第２の面１４から突出させることができる。
【００２５】
導電部４０の一部（詳しくは先端部４２の少なくとも一部）を第２の面１４から露出させる。先端部４２の一部のみを露出させてもよい。すなわち、先端部４２の一部が露出して他の一部が半導体基板１０内に配置されるように、第２の面１４を削ってもよい。
【００２６】
図４（Ｂ）に示すように、導電部４０が絶縁膜３４に覆われている場合、絶縁膜３４を除去する。これにより、導電部４０の先端部４２の少なくとも一部を第２の面１４から露出させることができる。また、先端部４２を第２の面１４から突出させることもできる。絶縁膜３４は、導電部４０と半導体基板１０（詳しくはその貫通穴の内面）との間に介在している。さらに、先端部４２のうち第２の面１４からの突出部の一部（例えば側面）を覆うように絶縁膜３４を残してもよい。その場合、先端部４２の先端面（例えば凸曲面）を絶縁膜３４から露出させる。
【００２７】
例えば、以上の方法によって、図４（Ｂ）に示すように、半導体基板１０に導電部４０からなる（又は導電部４０を含む）貫通電極４６を形成することができる。例えば、以上の工程により、貫通電極４６を有する半導体ウエハ５０（図５参照）が得られる。この場合、半導体基板１０には、複数の集積回路１６が形成され、それぞれの集積回路１６に対応して貫通電極４６が形成されている。その詳しい構造は、上述した製造方法から導くことができる内容である。半導体ウエハ５０を半導体装置ということもできる。あるいは、貫通電極４６を有する半導体チップ６０（図８参照）が得られる。この場合、半導体基板１０には、１つの集積回路１６が形成されている。その詳しい構造は、上述した製造方法から導くことができる内容である。半導体チップ６０を半導体装置ということもできる。
【００２８】
半導体ウエハ５０は、切断（例えばダイシング）してもよい。例えば、図５に示すように、半導体ウエハ５０を切断（例えばダイシング）する。切断には、カッタ（例えばダイサ）５２又はレーザ（例えばＣＯ2レーザ、ＹＡＧレーザ等）を使用してもよい。これにより、貫通電極４６を有する半導体チップ６０（図８参照）が得られる。その構造は、上述した製造方法から導くことができる内容である。
【００２９】
図６に示すように、半導体装置の製造方法は、複数の半導体基板１０をスタックすることを含んでもよい。各半導体基板１０は、貫通電極４６を有し、貫通電極４６は、導電部４０からなる（又は導電部４０を含む）。スタックされた複数の半導体基板１０のうち上下の半導体基板１０の貫通電極４６を電気的に接続する。例えば、貫通電極４６同士をろう接してもよい。あるいは、電気的接続には、金属接合を適用してもよいし、異方性導電材料（異方性導電膜又は異方性導電ペースト等）を使用してもよいし、絶縁性接着剤の収縮力を利用した圧接を適用してもよいし、これらの組み合わせであってもよい。
【００３０】
本実施の形態では、貫通電極４６の先端部４２が延設部４４よりも幅（例えば直径）が大きくなっているので、電気的接続に適している。また、貫通電極４６の先端部４２の第２の面１４からの露出部（例えば先端面）が凸曲面であれば、電気的な接続面積が広くなる。
【００３１】
スタックされた複数の半導体基板１０の具体例として、図７に示すように、貫通電極４６を有する複数の半導体ウエハ５０をスタックしてもよい。その場合、スタックされた複数の半導体ウエハ５０を切断してもよい。あるいは、図８に示すように、貫通電極４６を有する複数の半導体チップ６０をスタックしてもよいし、貫通電極４６を有する半導体チップ６０と貫通電極４６を有する半導体ウエハ５０をスタックしてもよい。半導体チップ６０がスタックされた後に、半導体ウエハ５０を切断してもよい。
【００３２】
図９は、本発明の実施の形態に係る半導体装置（スタック型半導体装置）を示す図である。半導体装置は、上述した貫通電極４６を有する複数の半導体チップ６０を含む。複数の半導体チップ６０はスタックされている。上下の貫通電極４６は、ろう接されていてもよい。ろう接には、硬ろう・軟ろう（例えばハンダペースト）６２を使用する。硬ろう・軟ろう６２を印刷、ディスペンス又は転写によって貫通電極４６に供給してもよい。１つの半導体チップ６０をスタックするごとに、ろう接を行ってもよい。あるいは、硬ろう・軟ろう６２を上下の貫通電極４６間に設けた状態で、全ての半導体チップ６０を仮マウントして、一括リフローによって、ろう接を行ってもよい。
【００３３】
上下の半導体チップ６０間に、絶縁材料（例えば接着剤・樹脂・アンダーフィル材）６４を設けてもよい。絶縁材料６４によって、貫通電極４６の接合状態が維持又は補強される。本実施の形態に係る半導体装置には、本実施の形態に係る半導体装置の製造方法から導くことができる内容を適用することができる。
【００３４】
スタックされた複数の半導体チップ６０は、配線基板７０に実装されてもよい。１つの半導体チップ（スタックされた複数の半導体チップ６０のうち、最も外側の半導体チップ６０）は、配線基板（例えばインターポーザ）７０に実装してもよい。その場合、第２の面１４の方向に最も外側（例えば最も下側）の貫通電極４６を有する半導体チップ６０が、配線基板７０に実装される。例えば、貫通電極４６の先端部４２を配線パターン７２に電気的に接続（例えば接合）してもよい。図示しない例として、貫通電極４６の第１の面１２からの露出部を配線パターン７２に電気的に接続（例えば接合）してもよい。
【００３５】
半導体チップ６０と配線基板７０の間には、絶縁材料（例えば接着剤・樹脂・アンダーフィル材）６４を設けてもよい。配線基板７０には、配線パターン７２に電気的に接続された外部端子（例えばハンダボール）７４が設けられている。あるいは、半導体チップ６０に応力緩和層を形成し、その上にパッド２０から配線パターンを形成し、その上に外部端子を形成してもよい。その他の内容は、上述した製造方法から導くことができる。
【００３６】
図１０には、複数の半導体チップがスタックされてなる半導体装置１が実装された回路基板１０００が示されている。半導体装置１の一部は上述した半導体チップ６０であるから、回路基板１０００には半導体チップ６０が実装されている。上述した半導体装置を有する電子機器として、図１１にはノート型パーソナルコンピュータ２０００が示され、図１２には携帯電話３０００が示されている。これらの電子機器は、半導体チップ６０を有するものでもある。
【００３７】
本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。
【図面の簡単な説明】
【図１】 図１（Ａ）〜図１（Ｃ）は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。
【図２】 図２（Ａ）〜図２（Ｃ）は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。
【図３】 図３（Ａ）〜図３（Ｃ）は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。
【図４】 図４（Ａ）〜図４（Ｂ）は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。
【図５】 図５は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。
【図６】 図６は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。
【図７】 図７は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。
【図８】 図８は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。
【図９】 図９は、本発明の実施の形態に係る半導体装置を示す図である。
【図１０】 図１０は、本発明の実施の形態に係る回路基板を示す図である。
【図１１】 図１１は、本発明の実施の形態に係る電子機器を示す図である。
【図１２】 図１２は、本発明の実施の形態に係る電子機器を示す図である。
【符号の説明】
１０半導体基板、１２第１の面、１４第２の面、１６集積回路、２２縦穴、
３０膜、３２凹部、３４絶縁膜、４０導電部、４２先端部、４４延設部、
４６貫通電極[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor chip, a semiconductor wafer, a semiconductor device and a manufacturing method thereof, a circuit board, and an electronic device.
[0002]
[Prior art]
[0003]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-44197
BACKGROUND OF THE INVENTION
A semiconductor device having a three-dimensional mounting form has been developed. In order to enable three-dimensional mounting, it is known that a through electrode is formed on a semiconductor chip. The through electrode is formed so as to protrude from the semiconductor chip. Conventionally known through electrodes have a shape that makes it difficult to achieve good electrical connection.
[0005]
An object of the present invention is to form a through electrode in a shape suitable for electrical connection.
[0006]
[Means for Solving the Problems]
(1) In the method for manufacturing a semiconductor device according to the present invention, (a) a recess having a bottom wider than an opening is formed on a first surface of a semiconductor substrate formed with at least a part of an integrated circuit. Forming,
(B) providing a conductive portion in the recess so as to have a tip corresponding to the bottom; and
(C) scraping the second surface of the semiconductor substrate to expose at least a part of the tip of the conductive portion from the second surface;
including.
According to the present invention, since the conductive portion is formed corresponding to the concave portion, the width of the tip portion is wide, and a through electrode having a shape suitable for electrical connection can be formed.
(2) In this method of manufacturing a semiconductor device,
Forming the bottom surface of the concave portion to have a concave curved surface;
Forming the tip of the conductive part to have a convex curved surface;
At least a part of the convex curved surface may be exposed from the second surface.
(3) In this method of manufacturing a semiconductor device,
The second surface may be shaved so that only a part of the tip is exposed.
(4) In this method of manufacturing a semiconductor device,
The step (a)
(A 1 ) forming a vertical hole having a bottom surface in the semiconductor substrate; and
(A 2 ) etching the semiconductor substrate so as to cause an undercut from the bottom surface of the vertical hole;
May be included.
(5) A manufacturing method of this semiconductor device is as follows:
After the step (a 1 ) and before the step (a 2 ),
It may further include forming a film having higher resistance to the etching performed in the step (a 2 ) than the bottom surface of the vertical hole on the inner wall surface of the vertical hole.
(6) A manufacturing method of this semiconductor device is as follows:
After the step (a) and before the step (b),
An insulating film may be further formed on the inner surface of the recess.
(7) In this method of manufacturing a semiconductor device,
The insulating film may be formed by TEOS-O 3 system CVD.
(8) In this method of manufacturing a semiconductor device,
Further comprising stacking a plurality of said semiconductor substrates;
Of the plurality of semiconductor substrates, the conductive portions of the upper and lower semiconductor substrates may be electrically connected.
(9) A semiconductor wafer according to the present invention includes a semiconductor substrate having first and second surfaces;
A plurality of integrated circuits formed at least partially at a position closer to the first surface than the second surface of the semiconductor substrate;
A plurality of through electrodes penetrating the first and second surfaces of the semiconductor substrate;
Have
Each of the through electrodes has a tip portion at least partially exposed from the second surface, and an extending portion extending from the tip portion toward the first surface, and the tip portion is It is formed to be wider than the extending portion.
According to the present invention, since the through electrode has a wide tip portion, it has a shape suitable for electrical connection.
(10) In this semiconductor wafer,
The tip of each through electrode has a convex curved surface,
At least a part of the convex curved surface may be exposed from the second surface.
(11) In this semiconductor wafer,
A part of the tip of each through electrode may be exposed and the other part may be disposed in the semiconductor substrate.
(12) This semiconductor wafer is
You may further have the insulating film formed between each said through-electrode and the inner surface of the through-hole formed in the said semiconductor substrate.
(13) A semiconductor chip according to the present invention includes a semiconductor substrate having first and second surfaces;
An integrated circuit formed at least partially at a position closer to the first surface than the second surface of the semiconductor substrate;
A through electrode penetrating the first and second surfaces of the semiconductor substrate;
Have
The penetrating electrode has a tip portion at least partially exposed from the second surface, and an extending portion extending from the tip portion in the direction of the first surface, and the tip portion is extended from the extension surface. It is formed so as to be wider than the installation portion.
According to the present invention, since the through electrode has a wide tip portion, it has a shape suitable for electrical connection.
(14) In this semiconductor chip,
The tip of the through electrode has a convex curved surface,
At least a part of the convex curved surface may be exposed from the second surface.
(15) In this semiconductor chip,
A part of the tip part of the through electrode may be exposed and the other part may be disposed in the semiconductor substrate.
(16) This semiconductor chip is
You may further have the insulating film formed between the said through-electrode and the inner surface of the through-hole formed in the said semiconductor substrate.
(17) A semiconductor device according to the present invention includes the plurality of stacked semiconductor chips,
Upper and lower semiconductor chips among the plurality of semiconductor chips are electrically connected by the through electrodes.
According to the present invention, since the through electrode has a wide tip portion, it has a shape suitable for electrical connection.
(18) A circuit board according to the present invention has the semiconductor chip mounted thereon.
(19) A circuit board according to the present invention has the semiconductor device mounted thereon.
(20) An electronic apparatus according to the present invention includes the semiconductor chip.
(21) An electronic apparatus according to the present invention includes the semiconductor device.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0008]
FIG. 1A to FIG. 4B are diagrams for explaining a method for manufacturing a semiconductor device (or semiconductor chip / semiconductor wafer) according to an embodiment to which the present invention is applied. In this embodiment mode, a semiconductor substrate 10 is used as shown in FIG. The semiconductor substrate 10 has first and second surfaces 12 and 14. The second surface 14 is a surface opposite to the first surface 12.
[0009]
At least a part (a part or the whole) of an integrated circuit (for example, a circuit having a transistor or a memory) 16 is formed in the semiconductor substrate 10. At least a part of each of the plurality of integrated circuits 16 may be formed on the semiconductor substrate 10, or at least a part of one integrated circuit 16 may be formed. The integrated circuit 16 is formed at a position closer to the first surface 12 than to the second surface 14.
[0010]
A passivation film 18 is formed on the first surface 12 of the semiconductor substrate 10. The passivation film 18 can be formed of, for example, SiO 2 , SiN, polyimide resin, or the like. The passivation film 18 is formed so as to cover the integrated circuit 16.
[0011]
A plurality of pads 20 are formed on the semiconductor substrate 10. The pad 20 may be electrically connected to the integrated circuit 16. Each pad 20 may be formed of aluminum. The shape of the surface of the pad 20 is not particularly limited, but is often rectangular. The pad 20 is formed at a position closer to the first surface 12 than the second surface 14 (for example, above the first surface 12). The pad 20 may be formed on the passivation film 18. A pad 20 and a wiring (not shown) for connecting the integrated circuit 16 and the pad 20 may be formed on the passivation film 18. Further, another passivation film (insulating film) (not shown) may be formed while avoiding at least a part of the surface of the pad 20.
[0012]
As shown in FIG. 1B, vertical holes (or recesses) 22 are formed in the semiconductor substrate 10 from the first surface 12 thereof. The vertical hole 22 is formed so as not to penetrate the semiconductor substrate 10, that is, to have a bottom surface. The first surface 12 is a surface on the side where the pad 20 is formed (the side where the integrated circuit 16 is formed). The vertical hole 22 is formed avoiding the elements and wiring of the integrated circuit 16. A through hole 24 may be formed in the pad 20. Etching (dry etching or wet etching) may be applied to the formation of the through hole 24. Etching may be performed after forming a resist (not shown) patterned by a lithography process. When the passivation film 18 is formed under the pad 20, the through hole 26 is also formed there. When the etching of the pad 20 stops at the passivation film 18, the etchant used for the etching of the pad 20 may be replaced with another etchant for forming the through hole 26. In that case, a resist (not shown) patterned by a lithography process may be formed again.
[0013]
A vertical hole 22 is formed in the semiconductor substrate 10 so as to communicate with the through hole 24 (and the through hole 26). The vertical hole 22 may be formed perpendicular to the first surface 12, or may be tapered so that the hole diameter decreases from the opening in the depth direction, for example. The through hole 24 (and the through hole 26) and the vertical hole 22 may be combined to be called a vertical hole (or a recess). Etching (dry etching or wet etching) can also be applied to the formation of the vertical holes 22. Etching may be performed after forming a resist (not shown) patterned by a lithography process. Alternatively, a laser (for example, a CO 2 laser, a YAG laser, etc.) may be used for forming the vertical hole 22. The laser may be applied to form the through holes 24 and 26. The vertical hole 22 and the through holes 24 and 26 may be continuously formed by using one kind of etchant or laser. Sandblasting may be applied to the formation of the vertical holes 22.
[0014]
As shown in FIG. 1C, a resist 28 may be formed above the first surface 12 (for example, on the passivation film 18 and the pad 20). The resist 28 is formed if necessary for protecting the first surface 12 and members (for example, the passivation film 18 and the pad 20) formed thereon from a process performed later. The resist 28 is formed of, for example, a material that has higher resistance to etching than the semiconductor substrate 10. The resist 28 is formed so that the vertical hole 22 is opened (avoids the vertical hole 22).
[0015]
A film 30 is formed in the vertical hole 22. The film 30 is formed on the inner wall surface of the vertical hole 22. The film 30 may be formed on the bottom surface of the vertical hole 22 or may be formed on the resist 28. The film 30 may be formed of a material that has higher resistance to etching than the semiconductor substrate 10. For example, the film 30 may be formed of carbon or a material containing carbon using C 4 F 8 gas.
[0016]
As shown in FIG. 2A, a part of the film 30 is removed. Specifically, the portion of the film 30 formed on the bottom surface of the vertical hole 22 is removed. That is, the material of the semiconductor substrate 10 is exposed at the bottom surface of the vertical hole 22. In that case, a part of the film 30 is removed so that a portion of the film 30 formed on the inner wall surface of the vertical hole 22 is not removed. In that case, etching with high anisotropy (etching with high direction dependency of the etching rate), specifically, the etching rate in the vertical direction (depth direction of the vertical hole 22) is horizontal (the direction facing the inner wall surface of the vertical hole 22). Larger etchings) may be applied. For example, SF 6 gas may be introduced under high vacuum, a high bias voltage may be applied, and etching may be performed for several seconds. A portion of the film 30 on the resist 28 may be removed.
[0017]
As shown in FIG. 2B, the semiconductor substrate 10 is etched from the bottom surface of the vertical hole 22 so as to cause an undercut. Specifically, etching proceeds downward and laterally from the bottom surface of the vertical hole 22. For example, the etching may be performed by introducing SF 6 gas under a low vacuum and applying a low bias voltage. The inner wall surface of the vertical hole 22 may not be etched by the film 30 formed on the inner wall surface of the vertical hole 22. The bottom surface of the vertical hole 22 is etched to form a space having a width (for example, a diameter) wider than the opening of the vertical hole 22 (or the space surrounded by the inner wall surface). For example, the recess 32 having a bottom wider than the opening is formed in the semiconductor substrate 10 by the above process. The recess 32 may be formed such that the bottom surface has a concave curved surface. As shown in FIG. 2C, the resist 28 is removed and the film 30 is removed.
[0018]
As shown in FIG. 3A, an insulating film (electrical insulating film) 34 is formed on the inner surface of the recess 32. The insulating film 34 is formed to have a thickness of 1 μm or more on the inner surface of the recess 32. Thus, TEOS-O 3 -based CVD may be applied to form a thick film on the side surface. TEOS-O 3 system CVD may be performed under reduced pressure or under normal pressure. The insulating film 34 may be formed by a surface reaction at a low temperature of about 400 ° C. The quality of the insulating film 34 may be improved by annealing. The insulating film 34 is formed on the bottom surface of the recess 32. The insulating film 34 is formed on the inner wall surface of the recess 32. However, the insulating film 34 is formed so as not to fill the recess 32. That is, the insulating film 34 is formed so that the recess 32 remains. In addition, the insulating film 34 is formed so that the feature of the concave portion 32 that the bottom is wider than the opening remains after the formation.
[0019]
The insulating film 34 may be formed on the passivation film 18. When the insulating film 34 is formed on the pad 20, at least a part of the pad 20 is exposed from the insulating film 34 as shown in FIG. For example, a portion of the insulating film 34 on the pad 20 is removed. Etching (dry etching or wet etching) may be applied to the removal. Etching may be performed after forming a resist (not shown) patterned by a lithography process.
[0020]
As shown in FIG. 3C, the conductive portion 40 is formed in the concave portion 32. The conductive portion 40 has a shape corresponding to the internal shape of the recess 32. The shape corresponding to the internal shape of the recess 32 is the shape inside the insulating film 34 because the insulating film 34 is formed on the inner wall surface of the recess 32. The conductive portion 40 has a tip portion 42 corresponding to the bottom portion of the recess 32. The distal end portion 42 has a shape corresponding to the bottom portion of the recess 32. The shape corresponding to the bottom of the recess 32 is the shape inside the insulating film 34. The conductive portion 40 has an extending portion 44 extending from the distal end portion 42 toward the first surface 12. The conductive portion 40 may be formed so as to reach above the first surface 12 (for example, on the pad 20). The conductive portion 40 may be formed so as to be electrically connected to the pad 20 through, for example, an exposed portion from the insulating film 34. The conductive portions 40 provided in the plurality of recesses 32 may be connected to each other above the first surface 12 (for example, on the pad 20), or may be electrically disconnected from each other.
[0021]
Even after the formation of the insulating film 34, the recess 32 has a wider bottom than the opening thereof, so that the conductive portion 40 has a shape corresponding thereto. Therefore, the tip portion 42 has a width (for example, a diameter) larger than that of the extended portion 44. When the bottom surface of the recess 32 (for example, the inner side of the insulating film 34) has a concave curved surface, the distal end portion 42 of the conductive portion 40 is formed to have a convex curved surface.
[0022]
The conductive portion 40 may be formed of Cu or W. The conductive part 40 may include a barrier layer. The barrier layer is formed on the insulating film 34. That is, the barrier layer is a surface layer of the conductive portion 40. The barrier layer prevents other materials from diffusing into the semiconductor substrate 10 (for example, Si). The barrier layer may be formed of a material (for example, TiW or TiN) different from the layer formed thereon. The conductive portion 40 may include a seed layer when formed by electrolytic plating. The seed layer is formed after the barrier layer is formed. The seed layer is formed of the same material (for example, Cu) as the layer (for example, Cu, W, doped polysilicon (for example, low temperature polysilicon)) formed thereon.
[0023]
As shown in FIG. 4A, the semiconductor substrate 10 is thinned. Specifically, the second surface (the surface opposite to the first surface 12) 14 of the semiconductor substrate 10 is cut (ground or polished). For example, the semiconductor substrate 10 may be shaved by at least one of mechanical polishing / grinding and chemical polishing / grinding. Alternatively, etching may be applied. Etching may be performed using a dry etching apparatus. Alternatively, the etchant may be a mixed solution of hydrofluoric acid and nitric acid or a mixed solution of hydrofluoric acid, nitric acid and acetic acid. For example, a reinforcing member such as a glass plate, a resin layer, or a resin tape may be provided on the first surface 12 side of the semiconductor substrate 10 (for example, pasted with an adhesive or an adhesive sheet).
[0024]
The conductive portion 40 may protrude from the second surface 14. For example, the second surface 14 may be etched by an etchant having a property that the etching amount for the semiconductor substrate (for example, Si) 10 is larger than the etching amount for the insulating film (for example, SiO 2 ) 34. The etchant may be SF 6 or CF 4 or Cl 2 gas. Thereby, the conductive portion 40 can be protruded from the second surface 14 while being covered with the insulating film 34.
[0025]
A part of the conductive part 40 (specifically, at least a part of the tip part 42) is exposed from the second surface. Only a part of the tip portion 42 may be exposed. That is, the second surface 14 may be shaved so that a part of the tip portion 42 is exposed and the other part is disposed in the semiconductor substrate 10.
[0026]
As shown in FIG. 4B, when the conductive portion 40 is covered with the insulating film 34, the insulating film 34 is removed. Thereby, at least a part of the tip portion 42 of the conductive portion 40 can be exposed from the second surface 14. Further, the tip end portion 42 can be protruded from the second surface 14. The insulating film 34 is interposed between the conductive portion 40 and the semiconductor substrate 10 (specifically, the inner surface of the through hole). Further, the insulating film 34 may be left so as to cover a part (for example, a side surface) of the protruding portion from the second surface 14 in the tip portion 42. In that case, the distal end surface (for example, a convex curved surface) of the distal end portion 42 is exposed from the insulating film 34.
[0027]
For example, as shown in FIG. 4B, the through electrode 46 including the conductive portion 40 (or including the conductive portion 40) can be formed in the semiconductor substrate 10 by the above method. For example, the semiconductor wafer 50 (see FIG. 5) having the through electrode 46 is obtained by the above process. In this case, a plurality of integrated circuits 16 are formed on the semiconductor substrate 10, and through electrodes 46 are formed corresponding to the integrated circuits 16. The detailed structure is the content which can be derived from the manufacturing method described above. The semiconductor wafer 50 can also be called a semiconductor device. Or the semiconductor chip 60 (refer FIG. 8) which has the penetration electrode 46 is obtained. In this case, one integrated circuit 16 is formed on the semiconductor substrate 10. The detailed structure is the content which can be derived from the manufacturing method described above. The semiconductor chip 60 can also be called a semiconductor device.
[0028]
The semiconductor wafer 50 may be cut (for example, dicing). For example, as shown in FIG. 5, the semiconductor wafer 50 is cut (for example, dicing). For cutting, a cutter (for example, dicer) 52 or a laser (for example, CO 2 laser, YAG laser, etc.) may be used. Thereby, the semiconductor chip 60 (refer FIG. 8) which has the penetration electrode 46 is obtained. The structure is a content that can be derived from the manufacturing method described above.
[0029]
As shown in FIG. 6, the method for manufacturing a semiconductor device may include stacking a plurality of semiconductor substrates 10. Each semiconductor substrate 10 includes a through electrode 46, and the through electrode 46 includes the conductive portion 40 (or includes the conductive portion 40). The through electrodes 46 of the upper and lower semiconductor substrates 10 among the stacked semiconductor substrates 10 are electrically connected. For example, the through electrodes 46 may be brazed. Alternatively, metal connection may be applied for electrical connection, an anisotropic conductive material (an anisotropic conductive film or anisotropic conductive paste, etc.) may be used, or an insulating adhesive may be used. A pressure contact using a contraction force may be applied, or a combination of these may be used.
[0030]
In the present embodiment, the distal end portion 42 of the through electrode 46 has a width (for example, a diameter) larger than that of the extending portion 44, which is suitable for electrical connection. Moreover, if the exposed part (for example, front end surface) from the 2nd surface 14 of the front-end | tip part 42 of the penetration electrode 46 is a convex curve, an electrical connection area will become large.
[0031]
As a specific example of the stacked semiconductor substrates 10, a plurality of semiconductor wafers 50 having through electrodes 46 may be stacked as shown in FIG. 7. In that case, a plurality of stacked semiconductor wafers 50 may be cut. Alternatively, as shown in FIG. 8, a plurality of semiconductor chips 60 having through electrodes 46 may be stacked, or a semiconductor chip 60 having through electrodes 46 and a semiconductor wafer 50 having through electrodes 46 may be stacked. . The semiconductor wafer 50 may be cut after the semiconductor chips 60 are stacked.
[0032]
FIG. 9 is a diagram showing a semiconductor device (stacked semiconductor device) according to an embodiment of the present invention. The semiconductor device includes a plurality of semiconductor chips 60 having the through electrodes 46 described above. A plurality of semiconductor chips 60 are stacked. The upper and lower through electrodes 46 may be brazed. For brazing, a hard solder / soft solder (for example, solder paste) 62 is used. The hard solder / soft solder 62 may be supplied to the through electrode 46 by printing, dispensing, or transferring. The soldering may be performed every time one semiconductor chip 60 is stacked. Alternatively, all the semiconductor chips 60 may be temporarily mounted in a state where the hard solder / soft solder 62 is provided between the upper and lower through electrodes 46, and soldering may be performed by batch reflow.
[0033]
An insulating material (for example, an adhesive, a resin, or an underfill material) 64 may be provided between the upper and lower semiconductor chips 60. The insulating material 64 maintains or reinforces the bonding state of the through electrode 46. The contents derived from the method for manufacturing a semiconductor device according to the present embodiment can be applied to the semiconductor device according to the present embodiment.
[0034]
The plurality of stacked semiconductor chips 60 may be mounted on the wiring board 70. One semiconductor chip (the outermost semiconductor chip 60 among the stacked semiconductor chips 60) may be mounted on a wiring board (for example, an interposer) 70. In that case, the semiconductor chip 60 having the outermost through electrode 46 in the direction of the second surface 14 (for example, the lowermost side) is mounted on the wiring board 70. For example, the tip portion 42 of the through electrode 46 may be electrically connected (for example, joined) to the wiring pattern 72. As an example (not shown), the exposed portion of the through electrode 46 from the first surface 12 may be electrically connected (for example, joined) to the wiring pattern 72.
[0035]
An insulating material (for example, adhesive, resin, underfill material) 64 may be provided between the semiconductor chip 60 and the wiring board 70. The wiring board 70 is provided with external terminals (for example, solder balls) 74 that are electrically connected to the wiring pattern 72. Alternatively, a stress relaxation layer may be formed on the semiconductor chip 60, a wiring pattern may be formed from the pad 20 thereon, and an external terminal may be formed thereon. Other contents can be derived from the manufacturing method described above.
[0036]
FIG. 10 shows a circuit board 1000 on which a semiconductor device 1 in which a plurality of semiconductor chips are stacked is mounted. Since a part of the semiconductor device 1 is the semiconductor chip 60 described above, the semiconductor chip 60 is mounted on the circuit board 1000. As an electronic device having the above-described semiconductor device, a notebook personal computer 2000 is shown in FIG. 11, and a mobile phone 3000 is shown in FIG. These electronic devices also have a semiconductor chip 60.
[0037]
The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.
[Brief description of the drawings]
FIG. 1A to FIG. 1C are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 3A to 3C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
4A to 4B are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 6 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 7 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 8 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 9 is a diagram illustrating a semiconductor device according to an embodiment of the present invention.
FIG. 10 is a diagram showing a circuit board according to an embodiment of the present invention.
FIG. 11 is a diagram showing an electronic apparatus according to an embodiment of the present invention.
FIG. 12 is a diagram showing an electronic apparatus according to an embodiment of the present invention.
[Explanation of symbols]
10 semiconductor substrates, 12 first surface, 14 second surface, 16 integrated circuits, 22 vertical holes,
30 films, 32 recesses, 34 insulating films, 40 conductive parts, 42 tip parts, 44 extending parts,
46 through electrode

Claims (8)

（ａ）集積回路の少なくとも一部が作り込まれてなる半導体基板の第１の面に、開口部よりも幅の広い底部を有する凹部を形成すること、
（ｂ）前記凹部に、前記底部に対応する先端部を有するように、導電部を設けること、及び、
（ｃ）前記半導体基板の第２の面を削って、前記導電部の前記先端部の少なくとも一部を、前記第２の面から露出させること、
を含む半導体装置の製造方法。(A) forming a recess having a bottom wider than the opening on the first surface of the semiconductor substrate formed with at least a part of the integrated circuit;
(B) providing a conductive portion in the recess so as to have a tip corresponding to the bottom; and
(C) scraping the second surface of the semiconductor substrate to expose at least a part of the tip of the conductive portion from the second surface;
A method of manufacturing a semiconductor device including: 請求項１記載の半導体装置の製造方法において、
前記凹部の底面を、凹曲面を有するように形成し、
前記導電部の前記先端部を、凸曲面を有するように形成し、
前記凸曲面の少なくとも一部を、前記第２の面から露出させる半導体装置の製造方法。In the manufacturing method of the semiconductor device according to claim 1,
Forming the bottom surface of the concave portion to have a concave curved surface;
Forming the tip of the conductive part to have a convex curved surface;
A method of manufacturing a semiconductor device, wherein at least a part of the convex curved surface is exposed from the second surface. 請求項１又は請求項２記載の半導体装置の製造方法において、
前記先端部の一部のみが露出するように、前記第２の面を削る半導体装置の製造方法。In the manufacturing method of the semiconductor device of Claim 1 or Claim 2,
A method of manufacturing a semiconductor device, wherein the second surface is cut so that only a part of the tip is exposed. 請求項１から請求項３のいずれかに記載の半導体装置の製造方法において、
前記（ａ）工程は、
（ａ１）前記半導体基板に、底面を有する縦穴を形成すること、及び、
（ａ２）前記縦穴の前記底面から、アンダカットが生じるように前記半導体基板をエッチングすること、
を含む半導体装置の製造方法。In the manufacturing method of the semiconductor device in any one of Claims 1-3,
The step (a)
(A 1 ) forming a vertical hole having a bottom surface in the semiconductor substrate; and
(A 2 ) etching the semiconductor substrate so that undercut occurs from the bottom surface of the vertical hole;
A method of manufacturing a semiconductor device including: 請求項４記載の半導体装置の製造方法において、
前記（ａ１）工程の後であって前記（ａ２）工程の前に、
前記（ａ２）工程で行うエッチングに対して前記縦穴の前記底面よりも耐性が高い膜を、前記縦穴の内壁面に形成することをさらに含む半導体装置の製造方法。In the manufacturing method of the semiconductor device according to claim 4,
After the step (a 1 ) and before the step (a 2 ),
Wherein (a 2) the vertical hole said bottom surface is highly resistant film than against etching performed in step, further comprises a method of manufacturing a semiconductor device to be formed on the inner wall surface of the vertical hole. 請求項１から請求項５のいずれかに記載の半導体装置の製造方法において、
前記（ａ）工程の後であって前記（ｂ）工程の前に、
前記凹部の内面に、絶縁膜を形成することをさらに含む半導体装置の製造方法。In the manufacturing method of the semiconductor device in any one of Claims 1-5,
After the step (a) and before the step (b),
A method of manufacturing a semiconductor device, further comprising forming an insulating film on an inner surface of the recess. 請求項６記載の半導体装置の製造方法において、
ＴＥＯＳ−Ｏ３系ＣＶＤによって、前記絶縁膜を形成する半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 6.
A method for manufacturing a semiconductor device, wherein the insulating film is formed by TEOS-O 3 -based CVD. 請求項１から請求項７のいずれかに記載の半導体装置の製造方法において、
複数の前記半導体基板をスタックすることをさらに含み、
前記複数の半導体基板のうち、上下の半導体基板の前記導電部を電気的に接続する半導体装置の製造方法。In the manufacturing method of the semiconductor device in any one of Claims 1-7,
Further comprising stacking a plurality of said semiconductor substrates;
A manufacturing method of a semiconductor device for electrically connecting the conductive portions of upper and lower semiconductor substrates among the plurality of semiconductor substrates.
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