JP2005033105A - Semiconductor device, its manufacturing method, circuit board and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To protect an active element region from an external environment (e.g., a light or an electric noise) by a conductive layer, and to enhance reliability. <P>SOLUTION: A method for manufacturing a semiconductor device contains forming a plurality of through electrodes 54 which penetrate through first and second planes 20, 21 of a semiconductor substrate having an active element region 12, and a conductive layer 38 electrically connected to at least one of the plurality of through electrodes 54. The conductive layer 38 is formed so as to overlap the whole active element region in the semiconductor substrate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, a circuit board, and an electronic device.

  A semiconductor device having a three-dimensional mounting form has been developed. It is also known to form through electrodes on a semiconductor chip, stack the semiconductor chips, and join the upper and lower through electrodes. According to this, since a plurality of semiconductor chips are stacked at a short distance and are easily affected by electrical noise, reliability higher than that of a conventional semiconductor device is required.

An object of the present invention is to improve the reliability of a semiconductor device, a manufacturing method thereof, a circuit board, and an electronic device.
JP 2001-127242 A

(1) In the method for manufacturing a semiconductor device according to the present invention, a plurality of through electrodes penetrating the first and second surfaces of a semiconductor substrate having an active element region and at least one of the plurality of through electrodes are electrically connected. Forming electrically connected conductive layers, and
The conductive layer is formed to overlap the entire active element region in the semiconductor substrate. According to the present invention, the active element region can be protected from the external environment (for example, light and electrical noise) by the conductive layer, and the reliability can be improved.
(2) In the method for manufacturing a semiconductor device according to the present invention, a plurality of through electrodes penetrating the first and second surfaces of a semiconductor substrate having a plurality of pads, and at least one of the plurality of through electrodes are electrically connected. Forming electrically connected conductive layers, and
The conductive layer is formed in a central region surrounded by the plurality of pads in the semiconductor substrate. According to the present invention, the semiconductor device can be protected from the external environment (for example, light or electrical noise) by the conductive layer, and the reliability can be improved.
(3) In this method of manufacturing a semiconductor device,
The conductive layer may be formed to overlap with at least one of the first and second surfaces of the semiconductor substrate. According to this, for example, the active element region can be reliably protected from the external environment (for example, light and electrical noise).
(4) In this method of manufacturing a semiconductor device,
The conductive layer may be divided into a plurality of regions. By doing so, the area of the conductive layer can be reduced, so that stress based on expansion or contraction of the conductive layer can be dispersed.
(5) In this method of manufacturing a semiconductor device,
The conductive layer may be electrically connected to two or more through electrodes having a common potential among the plurality of through electrodes.
(6) In this method of manufacturing a semiconductor device,
The method may further include covering the conductive layer with an insulating material.
(7) In this method of manufacturing a semiconductor device,
The through electrode forming step includes:
(A) forming a recess in the semiconductor substrate from the first surface;
(B) forming an insulating layer on the inner surface of the recess;
(C) forming a conductive portion inside the insulating layer;
(D) exposing the conductive portion from the second surface of the semiconductor substrate;
May be included.
(8) In this method of manufacturing a semiconductor device,
In the step (c), a base electrode is formed on the semiconductor substrate, and the conductive portion is formed by performing a plating process.
The conductive layer may be formed leaving the base electrode. According to this, since a part of the base electrode used for the plating process is used, the conductive layer can be formed by a simple process.
(9) In this method of manufacturing a semiconductor device,
In the step (c), by forming a base electrode on the semiconductor substrate and performing a plating process, an outer surface layer is formed on the conductive portion and its periphery,
The conductive layer may be formed leaving the base electrode and the outer surface layer thereon. According to this, since a part of the base electrode used for the plating process is used, the conductive layer can be formed by a simple process.
(10) In this method of manufacturing a semiconductor device,
After the step (d), the conductive layer may be formed on the second surface of the semiconductor substrate.
(11) In this method of manufacturing a semiconductor device,
The method may further include cutting the semiconductor substrate to obtain a plurality of pieces.
(12) The method for manufacturing a semiconductor device according to the present invention further includes stacking a plurality of semiconductor devices manufactured by the above method and electrically connecting the upper and lower semiconductor devices through the through electrode. According to the present invention, a conductive layer that is electrically connected to at least one through electrode is formed in each semiconductor device, so that mutual interference between the conductor portion and the semiconductor portion of each semiconductor device can be prevented. The influence of static noise can be reduced. Therefore, it is possible to manufacture a semiconductor device that is extremely excellent in high-frequency characteristics.
(13) A semiconductor device according to the present invention includes a semiconductor substrate having an active element region,
A plurality of through electrodes penetrating the first and second surfaces of the semiconductor substrate;
A conductive layer electrically connected to at least one of the plurality of through electrodes and overlapping the entire active element region of the semiconductor substrate;
including. According to the present invention, the active element region can be protected from the external environment (for example, light and electrical noise) by the conductive layer, and the reliability can be improved.
(14) A semiconductor device according to the present invention includes a semiconductor substrate having a plurality of pads;
A plurality of through electrodes penetrating the first and second surfaces of the semiconductor substrate;
A conductive layer electrically connected to at least one of the plurality of through electrodes and formed in a central region surrounded by the plurality of pads in the semiconductor substrate;
including. According to the present invention, the semiconductor device can be protected from the external environment (for example, light or electrical noise) by the conductive layer, and the reliability can be improved.
(15) In this semiconductor device,
The conductive layer may overlap the entire at least one of the first and second surfaces of the semiconductor substrate. According to this, for example, the active element region can be reliably protected from the external environment (for example, light and electrical noise).
(16) In this semiconductor device,
The conductive layer may be divided into a plurality of regions. By doing so, the area of the conductive layer can be reduced, so that stress based on expansion or contraction of the conductive layer can be dispersed.
(17) In this semiconductor device,
The conductive layer may be electrically connected to two or more through electrodes having a common potential among the plurality of through electrodes.
(18) In this semiconductor device,
The conductive layer may be covered with an insulating material.
(19) The semiconductor device according to the present invention includes a plurality of semiconductor devices according to any one of claims 13 to 18, which are stacked.
Of the plurality of semiconductor devices, upper and lower semiconductor devices are electrically connected by the through electrode. According to the present invention, each semiconductor device is provided with a conductive layer electrically connected to at least one through electrode, thereby preventing mutual interference between the conductor portion and the semiconductor portion of each semiconductor device. Thus, the influence of electrical noise can be reduced. Therefore, it is possible to provide a semiconductor device that is extremely excellent in high-frequency characteristics.
(20) A circuit board according to the present invention has the semiconductor device mounted thereon.
(21) An electronic apparatus according to the present invention includes the semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1A to FIG. 12 are diagrams for explaining a semiconductor device and a manufacturing method thereof according to a first embodiment to which the present invention is applied. In the present embodiment, a semiconductor substrate 10 (for example, a semiconductor chip or a semiconductor wafer) is used.

  An integrated circuit is formed on the semiconductor substrate 10. The semiconductor substrate 10 has an active element region 12. The active element region 12 is a partial region of the integrated circuit. In the active element region 12, a plurality of active elements (eg, diodes and transistors) are densely packed. One or a plurality of active element regions 12 (for example, a plurality of different functions) may be provided in each semiconductor chip. The semiconductor substrate 10 has a plurality of pads (electrodes) 14 composed of at least one group. In many cases, a group of pads 14 are arranged in units of semiconductor chips. The pad 14 is electrically connected to the integrated circuit. The pad 14 is often formed of an aluminum-based or copper-based metal. The plurality of pads 14 in each group may be arranged along an outer peripheral end (for example, two or four sides facing each other) of a semiconductor chip (or a portion corresponding to the semiconductor chip). The plurality of pads 14 may be arranged in a region outside the active element region 12. In other words, the active element region 12 may be formed in a central region surrounded by the plurality of pads 14. The integrated circuit is electrically connected to the pad 14 by wiring (not shown) formed in the peripheral region of the active element region 12.

One or more layers of passivation films 16 and 18 are formed on the semiconductor substrate 10. The passivation films 16 and 18 can be formed of, for example, SiO ₂ , SiN, polyimide resin, or the like. Further, the passivation film 18 is formed so as to avoid at least a part of the surface of the pad 14. The passivation film 18 may be formed so as to cover the surface of the pad 14, and then a part of the passivation film 18 may be etched to expose a part of the pad 14. Either dry etching or wet etching may be applied to the etching. When the passivation film 18 is etched, the surface of the pad 14 may be etched.

  In the present embodiment, a recess 22 (see FIG. 1C) is formed in the semiconductor substrate 10 from the first surface 20 thereof. The first surface 20 is a surface on the side where the pad 14 is formed (the side where the active element region 12 is formed). The recess 22 is formed avoiding the elements and wirings in the active element region 12. As shown in FIG. 1B, a through hole 24 may be formed in the pad 14. Etching (dry etching or wet etching) may be applied to the formation of the through hole 24. Etching may be performed after forming a resist (not shown) patterned by a lithography process. When the passivation film 16 is formed under the pad 14, a through hole 26 (see FIG. 1C) is also formed there. When the etching of the pad 14 stops at the passivation film 16, the etchant used for the etching of the pad 14 may be replaced with another etchant for forming the through hole 26. In that case, a resist (not shown) patterned by a lithography process may be formed again.

As shown in FIG. 1C, a recess 22 is formed in the semiconductor substrate 10 so as to communicate with the through hole 24 (and the through hole 26). The through-hole 24 (and the through-hole 26) and the recess 22 can be combined to be called a recess. Etching (dry etching or wet etching) can also be applied to the formation of the recess 22. Etching may be performed after forming a resist (not shown) patterned by a lithography process. Alternatively, a laser (for example, a CO ₂ laser, a YAG laser, etc.) may be used for forming the recess 22. The laser may be applied to form the through holes 24 and 26. The recess 22 and the through holes 24 and 26 may be continuously formed by one kind of etchant or laser. Sand blasting may be applied to the formation of the recess 22.

As shown in FIG. 1D, an insulating layer 28 may be formed inside the recess 22. The insulating layer 28 may be an oxide film. For example, when the semiconductor substrate 10 is made of Si, the insulating layer 28 may be SiO ₂ or SiN. The insulating layer 28 is formed on the bottom surface of the recess 22. The insulating layer 28 is formed on the inner wall surface of the recess 22. However, the insulating layer 28 is formed so as not to fill the recess 22. That is, the recess is formed by the insulating layer 28. The insulating layer 28 may be formed on the inner wall surface of the through hole 26 of the passivation film 16. The insulating layer 28 may be formed on the passivation film 18.

  The insulating layer 28 may be formed on the inner wall surface of the through hole 24 of the pad 14. The insulating layer 28 is formed so as to avoid a part of the pad 14 (for example, the upper surface thereof). The insulating layer 28 may be formed so as to cover the entire surface of the pad 14, and a part of the insulating layer 28 may be etched (dry etching or wet etching) to expose a part of the pad 14. Etching may be performed after forming a resist (not shown) patterned by a lithography process.

  Next, a conductive portion 36 (see FIG. 3A) is provided in the recess 22 (for example, inside the insulating layer 28). The conductive portion 36 may be formed by filling the concave portion 22, or may be formed so as to further have a concave portion inside the concave portion 22. In the present embodiment, the conductive portion 36 is formed by forming the base electrode 30 and performing a plating process (electroplating).

  First, as illustrated in FIG. 2A, the base electrode 30 is formed on the first surface 20 (specifically, the insulating layer 28) including the inside of the recess 22. The base electrode 30 is integrally formed so as to include the insides of the plurality of recesses 22. The base electrode 30 may be formed so as to cover the entire surface of the first surface 20 or may be patterned. When at least a part of the base electrode 30 forms a conductive layer 38 to be described later, the base electrode 30 overlaps the entire active element region 12 (a central region surrounded by a group of pads 14). Form. The base electrode 30 may be formed by a sputtering method, an electroless plating method, or an ink jet method.

  As shown in FIG. 2B, the central portion 32 is formed. For example, the resist 40 may be patterned so as to have the opening 42 to form the central portion 32 in the opening 42. The central portion 32 is formed on the base electrode 30. The central portion 32 may be formed of the same material as that of the base electrode 30, and can be formed of, for example, any one of Cu, W, and doped polysilicon (for example, low temperature polysilicon).

  As shown in FIG. 2C, the resist 40 is removed. Thereafter, a part of the base electrode 30 is removed. For example, as shown in FIG. 2D, the resist 44 may be patterned so as to have an opening 46, and a part of the base electrode 30 exposed in the opening 46 may be etched. Thereafter, the resist 44 is removed.

  In this way, as shown in FIG. 3A, the outer layer portion 34 (a part of the base electrode 30) of the conductive portion 36 and the conductive layer 38 (the other part of the base electrode 30) can be formed. . The conductive portion 36 includes a center portion 32 and an outer layer portion 34 outside thereof. As shown in FIG. 3A, the outer layer part 34 may extend outward from the center part 32, or may extend to the same width as the center part 32. A part of the conductive portion 36 is located in the recess 22 of the semiconductor substrate 10. Since the insulating layer 28 is interposed between the inner wall surface of the recess 22 and the conductive portion 36, the electrical connection between them is interrupted. The conductive portion 36 is electrically connected to the pad 14. For example, the conductive portion 36 may be in contact with the exposed portion of the pad 14 from the insulating layer 28. A part of the conductive portion 36 may be located on the passivation film 18. The conductive portion 36 may be provided only in the region of the pad 14. The conductive portion 36 may protrude at least above the recess 22. For example, the conductive portion 36 may protrude from the passivation films 16 and 18 (and the insulating layer 28). In addition to the above, the conductive portion 36 (at least the central portion 32) may be formed by electroless plating or an inkjet method.

  FIG. 4 is a plan view of the semiconductor substrate corresponding to FIG. FIG. 4 shows a portion corresponding to a semiconductor chip of the semiconductor substrate 10 (the same applies to FIGS. 5 to 7). The conductive layer 38 is the remaining part of the base electrode 30. According to this, since a part of the base electrode 30 used for the plating process (electroplating) is used, the conductive layer 38 can be formed by a simple process. The conductive layer 38 is electrically connected to at least one (a plurality in FIG. 4) of the plurality of conductive portions 36. When electrically connected to the plurality of conductive portions 36, the conductive portions 36 have a common potential. That is, the conductive layer 38 may be electrically connected to a plurality of common electrodes. The conductive layer 38 may be electrically connected to a ground electrode (or power supply electrode). According to this, the impedance of wiring can be reduced and the influence of electrical noise can be reduced. The conductive layer 38 may be electrically connected to two or more (all or a part thereof) of the plurality of conductive portions 36 to be ground electrodes (or power supply electrodes). As shown in FIG. 4, the conductive layer 38 may be formed so as to overlap the entire surface (for example, the first surface 20) of any one of the semiconductor substrates 10. By doing so, the active element region 12 can be reliably protected from the external environment (for example, light and electrical noise), and reliability can be improved. The conductive layer 38 may have the same outer shape as the surface of the semiconductor substrate 10 (for example, the first surface 20), or from the surface of the semiconductor substrate 10 (for example, the first surface 20) as shown in FIG. May have a slightly smaller outer shape. The conductive layer 38 may extend so as to reach the outside of the region surrounded by the plurality of conductive portions 36. However, the conductive layer 38 is formed to avoid the periphery of at least one conductive portion 36 (for example, an input or output signal). That is, the conductive layer 38 is electrically connected to a part of the conductive parts 36 and is not electrically connected to the other part of the conductive parts 36. The conductive layer 38 is preferably formed of a highly conductive material (for example, an aluminum-based metal). The material of the conductive layer 38 may have higher conductivity than at least a part of the material of the conductive portion 36. In addition, when the shielding effect is acquired by the conductive layer 38, the conductive layer 38 is a shield layer.

  As shown in the modification of FIG. 5, the conductive layer 60 may be formed so as to overlap the whole (only) of the active element region 12 in the semiconductor substrate 10. For example, the conductive layer 60 includes a main body portion 62 having an outer shape including the active element region 12 and a connection portion 63 that electrically connects the main body portion 62 and the conductive portion 36. The main body 62 may have an outer shape (or substantially the same outer shape) slightly larger than that of the active element region 12. Alternatively, the conductive layer 60 (specifically, the main body portion 62 of the conductive layer 60) may be formed so as to overlap a central region (only) surrounded by a group of pads 14. For example, as shown in FIG. 5, when the plurality of pads 14 are arranged along two opposing sides of the semiconductor chip, the conductive layer 60 is formed in the central region (only) sandwiched between the rows. May be. The other configurations correspond to the contents described in the form shown in FIG.

  As shown in the modified example of FIG. 6, the conductive layer 64 may be divided into a plurality of regions (for example, four regions). By doing so, the area of the conductive layer 64 can be reduced, which is preferable because stress based on expansion or contraction of the conductive layer 64 is dispersed. The plurality of conductive layers 64 may be electrically independent from each other. The other configurations correspond to the contents described in the form shown in FIG.

  As shown in the modified example of FIG. 7, the content described in the form shown in FIG. 5 may be applied, and the conductive layer 66 may be divided into a plurality of regions (for example, four regions). For example, the conductive layer 66 includes a main body portion 68 having an outer shape including the active element region 12 and a connection portion 69 that electrically connects the main body portion 68 and the conductive portion 36. The main body 68 is divided into a plurality of regions. The other configurations correspond to the contents described in the forms shown in FIGS.

As shown in FIG. 3B, the conductive layer 38 may be covered with an insulating material 50. The insulating material 50 may be provided on the entire surface of the semiconductor substrate 10 on the first surface 20 side, avoiding the through electrode 54. The insulating material 50 may be a resin, an oxide film (for example, SiO ₂ ), a nitride film (for example, SiN), or the like. The insulating material 50 may be formed by applying a CVD (Chemical Vapor Deposition) method, a spin coating method, or the like.

  As shown in FIG. 3C, a brazing material 52 may be provided on the conductive portion 36. Specifically, the brazing material 52 is provided on the tip surface of the portion of the conductive portion 36 that protrudes from the first surface 20. The brazing material 52 is formed of, for example, solder, and may be formed of either soft solder or hard solder. The brazing material 52 may be formed by covering a region other than the conductive portion 36 with a resist.

  As shown in FIG. 3D, the conductive portion 36 is exposed from the second surface 21 of the semiconductor substrate 10 (the surface opposite to the first surface 20). A part of the semiconductor substrate 10 may be removed and thinned. For example, a part of the semiconductor substrate 10 may be removed by at least one of a mechanical method and a chemical method. In that case, the surface may be ground and polished with a grindstone or the like, or may be subjected to etching. The removal process of the semiconductor substrate 10 may be divided into a plurality of times. For example, grinding and polishing may be performed before the insulating layer 28 formed in the recess 22 is exposed in the first removal step, and the conductive portion 36 may be exposed in the second and subsequent removal steps. After the insulating layer 28 is exposed, the conductive portion 36 may be exposed in a separate process. This step may be performed in a state where a reinforcing member (not shown) (for example, a tape or a plate) is provided on the semiconductor substrate 10.

  Thus, a plurality of through electrodes 54 penetrating the first and second surfaces 20 and 21 of the semiconductor substrate 10 can be formed. The through electrode 54 includes a conductive portion 36. The through electrode 54 protrudes to at least one side (both sides in FIG. 3D) of the first and second surfaces 20 and 21.

As shown in FIG. 8, when the semiconductor substrate 10 is a semiconductor wafer 70, the conductive layer 38 and the through electrode 54 are formed in a portion corresponding to each semiconductor chip. Thereafter, the semiconductor substrate 10 is cut to obtain a plurality of pieces (semiconductor chip 80 (see FIG. 11)). For cutting, a cutter (for example, dicer) 72 or a laser (for example, CO ₂ laser, YAG laser, etc.) may be used.

  The method for manufacturing a semiconductor device may include stacking a plurality of semiconductor substrates 10. For example, a plurality of semiconductor wafers 70 may be stacked as shown in FIG. 9, or a plurality of semiconductor chips 80 may be stacked as shown in FIG. Alternatively, the semiconductor wafer 70 and the semiconductor chip 80 may be stacked. As shown in FIG. 9, after stacking a plurality of semiconductor wafers 70, they may be cut.

  Of the stacked semiconductor substrates 10, the upper and lower semiconductor substrates 10 are electrically connected through the through electrode 54. For electrical connection, solder bonding or metal bonding may be applied, an anisotropic conductive material (such as an anisotropic conductive film or anisotropic conductive paste) may be used, or an insulating adhesive. The press-contact using the contraction force may be applied, or a combination of these may be used.

  FIG. 11 is a diagram illustrating a semiconductor device according to an embodiment of the present invention. The semiconductor device includes a semiconductor chip 80 having the active element region 12, the through electrode 54, and the conductive layer 38 described above. According to this, since the conductive layer 38 electrically connected to at least one through electrode 54 is formed in the semiconductor device, mutual interference between the conductor portion and the semiconductor portion of the semiconductor device is prevented. Thus, the influence of electrical noise can be reduced. Further, the thin semiconductor chip 80 can be reinforced by the conductive layer 38. As a modification, the semiconductor device includes a semiconductor wafer 80 (see FIG. 8) having the active element region 12, the through electrode 54, and the conductive layer 38 described above. Other configurations are the contents obtained by the above-described manufacturing method.

  FIG. 12 is a diagram showing a semiconductor device (stacked semiconductor device) according to the present embodiment. In this semiconductor device, a plurality of semiconductor devices (including the semiconductor chip 80) of the form shown in FIG. 11 are stacked. The upper and lower semiconductor devices are electrically connected by the through electrode 54. According to this, each semiconductor device is provided with the conductive layer 38 electrically connected to any one of the through electrodes 54, so that the mutual interference between the conductor portion and the semiconductor portion of each semiconductor device is prevented. Therefore, the influence of electrical noise can be reduced. Therefore, it is possible to provide a semiconductor device that is extremely excellent in high-frequency characteristics.

  The through electrodes 54 may be joined to each other by the brazing material 52. A resin 82 (for example, an epoxy resin) may be filled between the stacked upper and lower semiconductor chips 80. The resin 82 is an underfill material, and can maintain and reinforce the bonding state of the upper and lower semiconductor substrates 10. The resin 82 may be filled between the upper and lower semiconductor chips 80 and provided to cover the side surfaces of the plurality of semiconductor chips 80. The resin 82 may be provided on the outer surface (for example, the second surface 21) of the uppermost semiconductor chip 80. In that case, the through electrode 54 may be covered with the resin 82.

  The plurality of stacked semiconductor chips 80 may be mounted on a wiring board (interposer) 84. The outermost (lowermost) semiconductor chip 80 may be mounted on the wiring board 84. For the mounting, face-down bonding may be applied. The resin 82 may also be filled between the semiconductor chip 80 and the wiring board 84. As a modification, a plurality of stacked semiconductor chips 80 may be face-up bonded. Alternatively, some of the plurality of semiconductor chips 80 may be mounted in the face-down bonding direction, and the other part may be mounted in the face-up bonding direction. A wiring pattern 86 is formed on the wiring substrate 84, and a plurality of semiconductor chips 80 are electrically connected to the wiring pattern 86 through the through electrode 54. The wiring pattern 86 is provided with external terminals (for example, solder balls) 88. As a modification, a stress relaxation layer is formed on the semiconductor chip 80 (first or second surface 20, 21), a wiring pattern is formed from the through electrode 54 thereon, and an external terminal is formed thereon. Also good. Other configurations are the contents obtained by the above-described manufacturing method.

(Second Embodiment)
FIGS. 13A to 13C are views for explaining a method of manufacturing a semiconductor device according to the second embodiment to which the present invention is applied. As shown in FIG. 13A, the base electrode 30 is formed on the first surface 20 (specifically, the insulating layer 28) including the inside of the recess 22. The details of the base electrode 30 are as already described. Then, by performing a plating process (electroplating), the outer surface layer 102 is formed on the conductive portion 36 (specifically, the central portion 32) and its periphery. The central portion 32 and the outer surface layer 102 are formed on the base electrode 30. As shown in FIG. 13A, the resist 100 is patterned, and as shown in FIG. 13B, the central portion 32 of the conductive portion 36 and the outer surface layer 102 are formed in the portion exposed from the resist 100. May be. Thereafter, the resist 100 is removed. Then, as shown in FIG. 13C, a part of the base electrode 30 is removed, and the conductive portion 36 and the conductive layer 106 are formed. For example, the whole of the semiconductor substrate 10 on the first surface 20 side may be etched to remove a part of the base electrode 30 that is relatively thin. The conductive layer 106 includes a part 104 of the base electrode 30 and an outer surface layer 102 formed thereon. Since the conductive layer 106 is formed by leaving the base electrode 30 and the outer surface layer 102 thereon, the manufacturing process is simple. The outer surface layer 102 may be formed of the same material as the base electrode 30 or may be formed of a different material. The contents described in the first embodiment can be applied to other configurations. Note that the configuration of the semiconductor device according to this embodiment can be derived from the above-described manufacturing method and the contents described in the first embodiment.

(Third embodiment)
14A to 15B are views for explaining a method for manufacturing a semiconductor device according to the third embodiment to which the present invention is applied. In the present embodiment, the conductive layer 112 is formed on the second surface 21 of the semiconductor substrate 10.

  As shown in FIG. 14A, after the base electrode 30 is formed, the central portion 32 of the conductive portion 36 is formed. Thereafter, as shown in FIG. 14B, unnecessary portions of the base electrode 30 are removed, and a conductive portion 36 having a center portion 32 and an outer layer portion 34 is formed. A brazing material 52 may be formed on the conductive portion 36. As shown in FIG. 14C, the conductive portion 36 is exposed from the second surface 21 of the semiconductor substrate 10, and a through electrode 54 that penetrates the first and second surfaces 20, 21 is formed. Details of these steps are as described in the first embodiment.

As shown in FIG. 14D, the insulating layer 110 is formed on the second surface 21 of the semiconductor substrate 10. The insulating layer 110 may be provided on the entire second surface 21. However, the insulating layer 110 is formed avoiding the through electrode 54. The insulating layer 110 may be a resin, an oxide film (for example, SiO ₂ ), a nitride film (for example, SiN), or the like. The insulating layer 110 may be formed by applying a CVD (Chemical Vapor Deposition) method, a spin coating method, or the like.

  As shown in FIG. 15A, a conductive layer 112 is formed on the second surface 21 side of the semiconductor substrate 10. The conductive layer 112 is formed over the insulating layer 110. The conductive layer 112 is formed so as to be electrically connected to some of the through electrodes 54 and not to be electrically connected to other part of the through electrodes 54. The conductive layer 112 and the through electrode 54 may be electrically connected by forming the through electrode 54 so as to cover it. The conductive layer 112 may be formed by applying a sputtering method, an electroless plating method, a CVD (Chemical Vapor Deposition) method, or the like. After that, the conductive layer 112 may be covered with an insulating material 114 as illustrated in FIG. The insulating material 114 may be provided on the entire surface of the semiconductor substrate 10 on the second surface 21 side, avoiding the through electrode 54. The contents described in the first embodiment can be applied to other configurations. Note that the configuration of the semiconductor device according to this embodiment can be derived from the above-described manufacturing method and the contents described in the first embodiment.

  As a modification, the above-described conductive layer may be formed on both the first and second surfaces 20 and 21 of the semiconductor substrate 10.

  FIG. 16 shows a circuit board 1000 on which a semiconductor device 1 in which a plurality of semiconductor chips are stacked is mounted. The plurality of semiconductor chips are electrically connected by the through electrode 54 described above. As an electronic apparatus having the above-described semiconductor device, a notebook personal computer 2000 is shown in FIG. 17, and a mobile phone 3000 is shown in FIG.

  The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

1A to 1D are views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention. 2A to 2D are views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 3A to FIG. 3D are views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 4 is a diagram showing the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention. FIG. 5 is a diagram showing a modification of the first embodiment of the present invention. FIG. 6 is a diagram showing a modification of the first embodiment of the present invention. FIG. 7 is a diagram showing a modification of the first embodiment of the present invention. FIG. 8 shows a method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 9 is a diagram showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 10 shows a method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 11 is a diagram showing a semiconductor device according to the first embodiment of the present invention. FIG. 12 is a diagram showing the semiconductor device according to the first embodiment of the present invention. FIG. 13A to FIG. 13C are views showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 14A to FIG. 14D are views showing a method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIGS. 15A and 15B are views showing a method for manufacturing a semiconductor device according to the third embodiment of the invention. FIG. 16 is a diagram showing a circuit board according to the embodiment of the present invention. FIG. 17 is a diagram showing an electronic apparatus according to an embodiment of the present invention. FIG. 18 is a diagram illustrating an electronic apparatus according to an embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 12 ... Active element area | region, 14 ... Pad, 22 ... Recessed part,
28 ... Insulating layer, 30 ... Base electrode, 32 ... Center part, 34 ... Outer layer part,
36 ... conductive portion, 38 ... conductive layer, 50 ... insulating material, 54 ... through electrode,
60, 64, 66 ... conductive layer, 70 ... semiconductor wafer, 80 ... semiconductor chip,
106, 112 ... conductive layer, 114 ... insulating material

Claims (21)

Forming a plurality of through electrodes penetrating the first and second surfaces of the semiconductor substrate having an active element region, and a conductive layer electrically connected to at least one of the plurality of through electrodes. Including
A method of manufacturing a semiconductor device, wherein the conductive layer is formed so as to overlap the entire active element region of the semiconductor substrate. Forming a plurality of through electrodes penetrating the first and second surfaces of a semiconductor substrate having a plurality of pads, and a conductive layer electrically connected to at least one of the plurality of through electrodes. Including
A method of manufacturing a semiconductor device, wherein the conductive layer is formed in a central region surrounded by the plurality of pads in the semiconductor substrate. In the manufacturing method of the semiconductor device of Claim 1 or Claim 2,
A method of manufacturing a semiconductor device, wherein the conductive layer is formed so as to overlap at least one of the first and second surfaces of the semiconductor substrate. In the manufacturing method of the semiconductor device in any one of Claims 1-3,
A method for manufacturing a semiconductor device, wherein the conductive layer is divided into a plurality of regions. In the manufacturing method of the semiconductor device in any one of Claims 1-4,
A method of manufacturing a semiconductor device, wherein the conductive layer is electrically connected to two or more through electrodes having a common potential among the plurality of through electrodes. In the manufacturing method of the semiconductor device in any one of Claims 1-5,
A method for manufacturing a semiconductor device, further comprising covering the conductive layer with an insulating material. In the manufacturing method of the semiconductor device in any one of Claims 1-6,
The through electrode forming step includes:
(A) forming a recess in the semiconductor substrate from the first surface;
(B) forming an insulating layer on the inner surface of the recess;
(C) forming a conductive portion inside the insulating layer;
(D) exposing the conductive portion from the second surface of the semiconductor substrate;
A method of manufacturing a semiconductor device including: The method of manufacturing a semiconductor device according to claim 7.
In the step (c), a base electrode is formed on the semiconductor substrate, and the conductive portion is formed by performing a plating process.
A method for manufacturing a semiconductor device, wherein the conductive layer is formed while leaving the base electrode. The method of manufacturing a semiconductor device according to claim 7.
In the step (c), by forming a base electrode on the semiconductor substrate and performing a plating process, an outer surface layer is formed on the conductive portion and its periphery,
A method of manufacturing a semiconductor device, wherein the conductive layer is formed while leaving the base electrode and the outer surface layer thereon. In the manufacturing method of the semiconductor device in any one of Claims 7-9,
A method of manufacturing a semiconductor device, wherein the conductive layer is formed on the second surface of the semiconductor substrate after the step (d). In the manufacturing method of the semiconductor device in any one of Claims 1-10,
A method of manufacturing a semiconductor device, further comprising cutting a semiconductor substrate to obtain a plurality of pieces.   A semiconductor device manufacturing method further comprising stacking a plurality of semiconductor devices manufactured by the method according to claim 1 and electrically connecting upper and lower semiconductor devices through the through-electrodes. Method. A semiconductor substrate having an active device region;
A plurality of through electrodes penetrating the first and second surfaces of the semiconductor substrate;
A conductive layer electrically connected to at least one of the plurality of through electrodes and overlapping the entire active element region of the semiconductor substrate;
A semiconductor device including: A semiconductor substrate having a plurality of pads;
A plurality of through electrodes penetrating the first and second surfaces of the semiconductor substrate;
A conductive layer electrically connected to at least one of the plurality of through-electrodes and formed in a central region surrounded by the plurality of pads in the semiconductor substrate;
A semiconductor device including: The semiconductor device according to claim 13 or 14,
The conductive device is a semiconductor device formed by overlapping at least one of the first and second surfaces of the semiconductor substrate. The semiconductor device according to any one of claims 13 to 15,
The semiconductor device is formed by dividing the conductive layer into a plurality of regions. The semiconductor device according to any one of claims 13 to 16,
The conductive layer is a semiconductor device that is electrically connected to two or more through electrodes having a common potential among the plurality of through electrodes. The semiconductor device according to any one of claims 13 to 17,
The semiconductor device, wherein the conductive layer is covered with an insulating material. A plurality of semiconductor devices according to any one of claims 13 to 18, which are stacked,
A semiconductor device in which upper and lower semiconductor devices among the plurality of semiconductor devices are electrically connected by the through electrode.   20. A circuit board on which the semiconductor device according to claim 13 is mounted.   An electronic apparatus comprising the semiconductor device according to any one of claims 13 to 19.

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