14 4 twf . do c/0 0 6 A7 B7 經濟部中央樣率局員工消費合作社印製 五、發明説明(/ ) 本發明是有關於一種製造半導體元件之方法,且特別 是有關於一種形成位元線與終端接觸(Node Contact)接著 塾(Landing Pad)的方法。 增進半導體元件效能之目標以透過微小化的方法所提 出’使半導體的製造已進入次微米的階段,同時也降低了 元件的製造成本。微小化已經經由在特定半導體製程方法 上部分的實現,例如是微影或乾鈾刻製程。使用更精密的 曝光設備與更精密的光阻材料已經是在次微米光阻成像上 —種例行的成就。 此外,使用在半導體元件製程上更先進蝕刻設備與方 法的發展,更使得在光阻層上次微米的影像能更成功的轉 移到下層之材質上。然而,就先進半導體元件的角度來看, 仍然必須致力於元件微小化。 以一個結構上的構件爲例,在微小化的元件中必須致 力在一導電結構連接上層的位元線結構或終端與下層電晶 體中源極汲極區相連接。許多有關的技術已經付諸使用, 例如是使用一狹窄的複晶砂插塞置於位兀線結構與下方的 源極汲極區之間作爲接著墊。然而在源極汲極區上形成一 狹窄的複晶矽插塞,並在複晶矽插塞上形成一位元線結 構,但這必須使各層之間緊密的結合與使用微影的覆蓋, 但有時候在次微米的線寬下是很難達成的。 第1A圖至第1E圖繪示爲習知的一種接著墊結構之剖 面圖。首先,請參照第1A圖,提供基底100 ;在基底1〇〇 上至少已形成具有包括閘極102、絕緣層104與間隙壁106 3 (讀先聞讀背面之注意事項再填寫本頁) 0^.------IT------@14 4 twf. Do c / 0 0 6 A7 B7 Printed by the Consumer Cooperative of the Central Sample Rate Bureau of the Ministry of Economic Affairs 5. Description of the Invention (/) The present invention relates to a method for manufacturing semiconductor components, and in particular to a method for forming bits The method of contacting the element line with the terminal (Node Contact) and then (Landing Pad). The goal of improving the efficiency of semiconductor devices is proposed by miniaturization, which allows semiconductor manufacturing to enter the sub-micron stage, and also reduces the manufacturing cost of devices. Miniaturization has been achieved in part through specific semiconductor process methods, such as lithography or dry uranium etching. The use of more sophisticated exposure equipment and more sophisticated photoresist materials has been a routine achievement in submicron photoresist imaging. In addition, the development of more advanced etching equipment and methods used in the fabrication of semiconductor devices has enabled the last micron image of the photoresist layer to be more successfully transferred to the underlying material. However, from the perspective of advanced semiconductor components, it is still necessary to work on miniaturization of the components. Taking a structural component as an example, in a miniaturized component, a conductive structure must be dedicated to connect the upper bit line structure or terminal with the source drain region in the lower-level electrical crystal. Many related techniques have been used, such as using a narrow polycrystalline sand plug as a bonding pad between the bit line structure and the underlying source / drain region. However, a narrow polycrystalline silicon plug is formed on the source-drain region, and a bit line structure is formed on the polycrystalline silicon plug. However, this must make the layers tightly combined and covered with lithography. But sometimes it is difficult to achieve under the sub-micron line width. 1A to 1E are cross-sectional views of a conventional bonding pad structure. First, please refer to FIG. 1A to provide a substrate 100; at least a gate electrode 102, an insulating layer 104, and a barrier wall 106 3 have been formed on the substrate 100 (read the precautions on the back and then fill out this page) 0 ^ .------ IT ------ @
本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 144twf.doc/006 A7 B7 經濟部中央標率局員工消費合作社印裝 五、發明説明(i) 的電晶體108。形成一層材質比如爲二氧化矽的第一介電 層110,覆蓋在包括電晶體1〇8的基底1〇〇上。 接;著,請參照第1B圖’進行微影製程,在第一介電層 110上定義並鈾刻接觸窗開口(未顯示),暴露出基底100 ; 然後再形成一層第一導電層112,覆棻在具有接觸窗開口 的第一介電層110上並塡入接觸窗開口中。 之後,請參照第1C圖,去除部分的第一導電層112, 至暴露出第一介電層110的表面爲止,以在接觸窗開口中 形成頂部略低於第一介電層110之上表面的接著墊113, 使用方法比如爲回蝕法(Etch Back)。 接著,請參照第ID圖,形成一層材質比如爲二氧化系 的第二介電層114,覆蓋在第一介電層uo與接著墊U3 的表面上。 之後,請參照第1E圖,進行微影製程,定義並去除部 分的第二介電層114,以在第二介電層中形成介層洞116, 暴露出部分的接著墊113。於形成介層洞116的第二介電 層114上,形成並定義一層第二導電層,以形成透過介層 洞116,稱接至接著墊U3的位元線118。 由於,接著墊的光阻圖案是互相分離的,當元件尺寸 曰益縮小時,受讎影製程删解析度(phQtQHthQgraphy = 1Utl°n)_制’接著墊_距離無法太接近(距離至 土勺尺寸限制造成微影製程的窗口 加製程的困難度。 ndow)很小更i曰 本纸張尺度適用) A4a^ (請先聞讀背面之注意事項再填寫本頁)This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X297 mm) 144twf.doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Transistor 108 of invention description (i). A first dielectric layer 110 made of a material such as silicon dioxide is formed on a substrate 100 including a transistor 108. Then, please refer to FIG. 1B to perform a lithography process, define a uranium-etched contact window opening (not shown) on the first dielectric layer 110, and expose the substrate 100; and then form a first conductive layer 112, Covered on the first dielectric layer 110 with the contact window opening and into the contact window opening. After that, referring to FIG. 1C, a part of the first conductive layer 112 is removed until the surface of the first dielectric layer 110 is exposed, so that the top of the contact window opening is slightly lower than the upper surface of the first dielectric layer 110. The bonding pad 113 is used, for example, Etch Back. Next, referring to FIG. ID, a layer of a second dielectric layer 114 made of, for example, a dioxide system is formed on the surface of the first dielectric layer uo and the bonding pad U3. After that, referring to FIG. 1E, a lithography process is performed to define and remove a portion of the second dielectric layer 114 to form a via 116 in the second dielectric layer and expose a portion of the bonding pad 113. On the second dielectric layer 114 forming the via 116, a second conductive layer is formed and defined so as to form the via 116, which is called a bit line 118 connected to the pad U3. Because the photoresist patterns of the bonding pads are separated from each other, when the component size is reduced, the resolution of the shadowing process (phQtQHthQgraphy = 1Utl ° n) cannot be made too close (the distance to the soil spoon The size limitation caused the difficulty of window adding process of lithography process. Ndow) is very small and more suitable for paper size) A4a ^ (Please read the precautions on the back before filling this page)
、1T -# 3 14 4 t w f .doc/006 A7 3 14 4 t w f .doc/006 A7 經濟部中央標準扃員工消費合作社印$1 _____B7 __ 五、發明説明(3) 另外,連接基底100的接著墊113除了部分作爲位元 線以外,亦有部分在後續製程中與導體相接,用以作爲終 端。其做法比如在形成位元線118的結構上,覆蓋一層第 三介電層,再利用微影製程,透過第二介電層與第三介電 層,形成介層洞耦接至接著墊以形成終端。 但是,此種方法形成之結構具有較高的高度,而且在 形成作爲終端的介層洞時,介層洞開口的位置必須避開第 一導電層與第二導電層所對應的位置,因此會提高製程的 困難度。換句話說,進行微影製程形成介層洞時,罩幕必 須要有較高的對準性,也就是說製程對於對準誤差的容忍 力會變得較差。而且多層介電層的結構亦會直接影響到元 件的尺寸。 因此,本發明的主要目的就是在,提供一種同時形成 位元線與終端接觸接著墊的方法。位元線與終端接觸係透 過定義並蝕刻導電層同時形成,故僅需形成一層介電層’ 對於縮小元件尺寸有相當大的助益;並且在形成接觸窗開 口後,於開口之側壁形成間隙壁,以增加對準誤差的容忍 力。 根據本發明的上述及其他目的’提出一種同時形成位 元線與終端接觸接著墊的方法,此方法包括下列步驟:首 先在形成有電晶體結構的基底上形成一層第一介電層’對 此第一介電層進彳了罩幂定義,利用自動封準的方式形成接 觸窗開口暴露出基底。在第一介電層上形成第二介電層, 利用回蝕法去除部分的第二導電層’以在接觸窗開口的側 5 (#先聞讀背面之法意事項再填寫本頁)、 1T-# 3 14 4 twf .doc / 006 A7 3 14 4 twf .doc / 006 A7 Central Standard of the Ministry of Economy 扃 Printed by the Consumer Consumption Cooperatives $ 1 _____B7 __ 5. Description of the invention (3) In addition, the bonding pad 113 connected to the substrate 100 In addition to being part of the bit line, there are also parts that are connected to the conductor in subsequent processes and used as terminations. For example, on the structure forming the bit line 118, a third dielectric layer is covered, and then a lithography process is used to form a via hole coupled to the bonding pad through the second dielectric layer and the third dielectric layer. Form the terminal. However, the structure formed by this method has a high height, and when forming a via hole as a terminal, the position of the via hole opening must avoid the corresponding position of the first conductive layer and the second conductive layer, so it will Increase the difficulty of the process. In other words, when the lithography process is used to form the vias, the mask must have high alignment, which means that the tolerance of the process to alignment errors will be poor. And the structure of the multilayer dielectric layer will directly affect the size of the device. Therefore, the main object of the present invention is to provide a method for simultaneously forming a bit line and a terminal contact pad. The bit line and terminal contacts are formed simultaneously by defining and etching the conductive layer, so only one dielectric layer is needed. It is of considerable help to reduce the size of the component; and after the contact window opening is formed, a gap is formed on the side wall of the opening. Wall to increase tolerance for misalignment. According to the above and other objects of the present invention, a method for simultaneously forming a bit line and a terminal contact pad is proposed. The method includes the following steps. First, a first dielectric layer is formed on a substrate having a transistor structure. The first dielectric layer is defined by the mask power, and the contact window opening is formed by an automatic sealing method to expose the substrate. A second dielectric layer is formed on the first dielectric layer, and a part of the second conductive layer is removed by an etch-back method so as to be on the side of the opening of the contact window.
、1T 參 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) 3144twf . doc/006 A7 經濟部中央標準局貝工消費合作社印製 B7 五、發明説明(¥ ) 壁形成間隙壁;然後形成一層導電層於第一介電層之表面 並塡入接觸窗開口中。在導電層上形成一層光阻罩幕,透 過光阻罩幕去除部分的導電層,以形成位元線;其中塡充 在接觸窗開口中,且未被光阻罩幕覆蓋的導電層並未被完 全去除,而有部分保留在接觸窗開口中以形成接著墊。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂, 下文特舉一較佳實施例,並配合所附圖式,作詳細說明如 下: 圖式之簡單說明: 第1A圖至第1E圖繪示爲習知的一種接著墊結構之剖 面圖; 第2A圖至第2E圖繪示依照本發明一較佳實施例的一 種形成位元線與終端接觸接著墊的製造流程圖;以及 第2F圖繪示爲沒有形成第二間隙壁時,光阻罩幕偏差 造成位元線與終端接著墊接觸的剖面示意圖。 圖示標記說明: 100.200 基底 102.202 閘極 104.204 絕緣層 106.206.216 間隙壁 108.208 電晶體 110.114.210 介電層 112.218 導電層 113.224.224’ 接著墊 6 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) --------II (請先閱讀背面之注意事項再填寫本頁) 訂 ^wl.、 1T paper size of this paper applies Chinese National Standard (CNS) A4 specification (210 × 297 mm) 3144twf.doc / 006 A7 Printed by B7 Consumers Cooperative of Central Standards Bureau of the Ministry of Economic Affairs 5. Description of invention (¥) The wall forms a gap; A conductive layer is then formed on the surface of the first dielectric layer and penetrates into the opening of the contact window. A photoresist mask is formed on the conductive layer, and a part of the conductive layer is removed through the photoresist mask to form bit lines. The conductive layer is filled in the opening of the contact window and is not covered by the photoresist mask. It is completely removed, while a portion remains in the contact window opening to form a bonding pad. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1A to FIG. FIG. 1E is a cross-sectional view of a conventional bonding pad structure; FIGS. 2A to 2E illustrate a manufacturing flow chart of forming a bit line and a terminal contact bonding pad according to a preferred embodiment of the present invention; and FIG. 2F is a schematic cross-sectional view showing that the bit line and the terminal pad contact with each other due to the deviation of the photoresist mask when the second gap wall is not formed. Description of pictograms: 100.200 substrate 102.202 gate 104.204 insulating layer 106.206.216 spacer 108.208 transistor 110.114.210 dielectric layer 112.218 conductive layer 113.224.224 'and then pad 6 This paper size applies Chinese National Standard (CNS) A4 specification ( 210X 297mm) -------- II (Please read the precautions on the back before filling this page) Order ^ wl.
II 一一讀 經濟部中央標隼局員工消費合作社印製 3144twf . doc/ 006 A7 B7 五、發明説明(多) 116 介層洞 118.222.222’ 位元線 2V2.214 接觸窗開口 220 光阻罩幕 實施例 第2A圖至第2E圖繪示依照本發明一較佳實施例的一 種形成位元線與終端接觸接著墊的製造流程圖。 首先,請參照第2A圖,提供基底200 ;在基底200上 至少已形成具有包括閘極202、絕緣層204與第一間隙壁 206的電晶體208。形成一層材質比如爲二氧化矽的介電 層210,覆蓋在包括電晶體208的基底200上,對此介電 層210進行微影製程,去除部分的介電層210暴露出基底 200,以形成終端接觸窗開口 212與位元線接觸窗開口 214。其中,形成第2A圖中所示的結構之製程爲熟悉此技 藝者可輕易達成,且非本發明之重點,故在此不詳細敘述 其製造方法。 接著,請參照第2B圖,在終端接觸窗開口 212與位元 線接觸窗開口 214之側壁形成第二間隙壁216,其材質比 如爲二氧化矽。第二間隙壁216的形成方法比如在第2A _所示的結構上,形成一層薄的二氧化矽層(未顯示),利 用回蝕法去除二氧化矽層,至暴露出介電層210與接觸窗 開口 212與214,殘留之二氧化矽層即會在接觸窗開口 212 與214之側壁形成第二間隙壁216。 之後,請參照第2C圖,形成一層導電層218於介電層 Ί 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) (請先閱讀背面之注意事項再填寫本頁)II One by one printed by the Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs, printed 3144twf.doc / 006 A7 B7 V. Description of the invention (multiple) 116 Via hole 118.222.222 'bit line 2V2.214 Contact window opening 220 Photoresist cover FIG. 2A to FIG. 2E of the curtain embodiment show a manufacturing flow chart of forming a bit line and a terminal contact bonding pad according to a preferred embodiment of the present invention. First, referring to FIG. 2A, a substrate 200 is provided; at least a transistor 208 including a gate electrode 202, an insulating layer 204, and a first spacer 206 has been formed on the substrate 200. A dielectric layer 210 made of a material such as silicon dioxide is formed on the substrate 200 including the transistor 208, and a lithography process is performed on the dielectric layer 210. A portion of the dielectric layer 210 is removed to expose the substrate 200 to form The terminal contact window opening 212 and the bit line contact window opening 214. Among them, the process of forming the structure shown in FIG. 2A is easily achieved by those skilled in the art and is not the focus of the present invention, so the manufacturing method is not described in detail here. Next, referring to FIG. 2B, a second gap 216 is formed on the side wall of the terminal contact window opening 212 and the bit line contact window opening 214, and the material is, for example, silicon dioxide. A method for forming the second spacer 216 is, for example, forming a thin silicon dioxide layer (not shown) on the structure shown in 2A_, and removing the silicon dioxide layer by an etch-back method to expose the dielectric layer 210 and The contact window openings 212 and 214, the remaining silicon dioxide layer will form a second gap wall 216 on the side walls of the contact window openings 212 and 214. After that, please refer to Figure 2C to form a conductive layer 218 on the dielectric layer. Ί This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the precautions on the back before filling this page)
、1T !44 twf - doc /〇 〇 6 Α7 !44 twf - doc /〇 〇 6 Α7 經濟部中央標隼局員工消費合作社印榮 Β7 -----—— '一 : 一 五、發明说明(ό) 210上,並塡充在終端接觸窗開口 212與位元線接觸窗開 口 214內。其中,導電層218之材質比如多晶矽或具有導 電性質的金屬。 接著,請參照第2D圖,在導電層218上形成一層光阻 罩幕220,其中光姐罩幕220之開口對應終端接觸窗開口 212。 之後,請參照第2E圖,透過光阻罩幕220對導電層218 進行蝕刻,至暴露出部分的介電層210爲止,使在終端接 觸窗開口 212外的導電層218被去除,僅留下塡充在其中 的接著墊224,在蝕刻步驟進行完後將光阻罩幕220移除。 其中,塡充在位兀線接觸窗開口 214中,被光阻罩幕220 覆蓋,而未被蝕刻的導電層係用以作爲位元線222。 在透過光阻罩幂進行微影触刻的步驟時,通常會有對 準上的誤差產生,元件的尺寸越小,對對準誤差的容忍力 越小,意即在對準上需要越尚的準確度,若產生對準誤差, 如果在接觸窗開口側壁沒有第二間隙壁,則會形成如第2F 圖所示的結構。如圖所示,光阻罩幕220開口在對準上有 偏差,透過此光阻罩幕220對導電層218進行蝕刻,則定 義的位元線212’會與終端接觸的接著墊224,相連接,而造 成短路。 因此,本發明在形成終端接觸窗開口與位元線接觸窗 開口後,在開口的側壁形成間隙壁,利用此間隙壁增加對 準誤差的容忍力。另外’在本發明中,終端接觸的接著墊 與位元線係在同一微影鈾刻步驟中形成,步驟簡單,且不 8 (讀先閱讀背面之注意事項再填寫本頁) 衣.1T! 44 twf-doc / 〇〇6 Α7! 44 twf-doc / 〇〇6 Α7 Yin Rong B7, Employee Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs (210), and is filled in the terminal contact window opening 212 and the bit line contact window opening 214. The material of the conductive layer 218 is, for example, polycrystalline silicon or a metal having conductive properties. Next, referring to FIG. 2D, a photoresist mask 220 is formed on the conductive layer 218, wherein the opening of the photomask 220 corresponds to the terminal contact window opening 212. After that, referring to FIG. 2E, the conductive layer 218 is etched through the photoresist mask 220 until the part of the dielectric layer 210 is exposed, so that the conductive layer 218 outside the terminal contact window opening 212 is removed, leaving only The bonding pad 224 filled therein is used to remove the photoresist mask 220 after the etching step is completed. Wherein, the conductive lines are filled in the openings 214 of the bit line contact windows, covered by the photoresist mask 220, and the unetched conductive layer is used as the bit lines 222. During the photolithography step through the photoresist mask, alignment errors usually occur. The smaller the component size, the smaller the tolerance for alignment errors, which means that the more alignment is required. If there is an alignment error, if there is no second gap wall on the side wall of the opening of the contact window, a structure as shown in Figure 2F will be formed. As shown in the figure, the opening of the photoresist mask 220 is misaligned. The conductive layer 218 is etched through the photoresist mask 220, and the defined bit line 212 'will contact the terminal with the bonding pad 224. Connection and cause a short circuit. Therefore, in the present invention, after forming the terminal contact window opening and the bit line contact window opening, a gap wall is formed on the side wall of the opening, and this gap wall is used to increase the tolerance of the alignment error. In addition, in the present invention, the contact pad of the terminal contact and the bit line are formed in the same lithography step, and the steps are simple and not 8 (read the precautions on the back before filling in this page).
、1T f ·φι. 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 3144twf . doc/ 006 A7 B7 五、發明説明(T) 需要形成多層的介電層,可有效的縮小元件的尺寸,進一 步降低製作的成本。 雖灘本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍內,當可作各種之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 9 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐), 1T f · φι. This paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) 3144twf .doc / 006 A7 B7 V. Description of the invention (T) Multi-layer dielectric layer needs to be formed, which can effectively reduce components Size, further reducing the cost of production. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 9 This paper size applies to Chinese National Standard (CNS) A4 (210X 297 mm)