經濟部中央標準局負工消費合作社印製 2. ^(9i^.d〇c/nos A7 _B7__ 五、發明説明（i ) 本發明是有關於一種金屬內連線的製造方法’且特別 是有關於一種多重金屬內連線（Interconnects)中’使用 未接著型介層窗（Unlanded Via)製程的自行對準介層窗的 製造方法。 當積體電路的積集度增加，使得晶片的表面無法提供 足夠的面積來製作所需的內連線時’爲了配合金屬氧化半 導體（Metal Oxide Semiconductor; MOS)電晶體縮小後 所增加的內連線需求，兩層以上的金屬層設計，便逐漸的 成爲許多積體電路所必需採用的方式°在金屬層之間常以 內金屬介電層（Inter-Metal Dielectric)加以隔離’並在其 中蝕刻一介層窗開口（Via Hole) ’接著在介層窗開口中塡 入導電材料，用來連接上下兩層金屬層，在半導體工業上， 稱之爲插塞（Plug)，而介層窗開口與插塞統稱爲介層窗。 在習知的金屬內連線設計時，爲了避免介層窗對不準 導線，以確保介層窗完全與導線互相接觸’於欲形成介層 窗位置的導線必須有較大的線寬，此種介層窗稱爲接著型 介層窗（Landed Via)。由於接著型介層窗需使用較大的晶 片面積，將造成製作成本上的的浪費^並且使元件的積集 度不易增加。因此，在積集度要求越來越高.的條件下，爲 了減少導線所使用的面積，須將介層窗的寬度與導線線寬 趨於一致，而不特別增加導線線寬，以達到增加元件積集 度的目的。然而，由於介層窗跟導線線寬相同’在形成介 層窗時，易使所形成之介層窗無法完全落在金屬線上’而 形成所謂的未接著型介層窗(Unlaruled Via)。 3 (請先聞讀背面之注意事項再填寫本頁) 丁 *ye 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2IOX297公釐） A 2. 69452^i doc/008 A7 B7 五、發明説明（2) 習知未接著型介層窗的製造方法常先於基底形成導 線*再於基底與導線上形成一層介電層，然後定義介電層 以形成介層窗開口，開口暴露出導線，於開口塡入導電材 質以形成插塞。但由於此種製程可能因爲介層窗開口無法 完全對準導線，使所形成的插塞與導線間的介電層相互接 觸，如果導線間的介電層具有吸水性，則會導致插塞的毒 化（Poison)。如導線間的介電層具有空氣間隙，則插塞可 能會破壞空氣間隙，造成介電層結構的損壞。 爲避免上述未接著型介層窗的缺點，習知亦使用一種 自行對準介層窗製程，其爲基底上形成一層導體層，在導 體層上形成一層介電層，於介電層中形成介層窗開口，再 於介層窗開口塡入導電材質以形成插塞，然後去除介電 層，使導體層上僅保留有插塞。然後上光阻，進行微影蝕 刻製程，使導體層具有導線的圖案，再形成一層介電層以 完成內連線的製造。 經濟部中央標準局貝工消費合作社印裝 (請先閱讀背面之注意事項再填寫本頁) 但進行此種製程時，導體層上形成插塞並去除導體層 上的介電層後，插塞沒有介電層的依附，因此易於倒場。 且隨後進行光阻塗佈時，由於基底表面高度落差極大，光 阻曝光不易，並且光阻不易塗佈於插塞與導體層上，使得 無法有效形成導線的圖案。 本發明提出一種內連線的製造方法。首先提供一基 底，基底已完成半導體元件之製作，於基底上形成一層導 體層，再於導體層上形成一罩幕層，圖案化罩幕層，於導 體層與罩幕層上形成一層第一介電層，然後定義介電層與 4 本紙張尺度適用中國國家標率（CNS ) A4規招1 2丨0X29?公^ 一— 4269 b ^ 4202tn J'.doc/ΟΟδ A7 B7 經濟部中央標隼局員工消費合作杜印製 五、發明说明（巧） 罩幕層以形成暴露出導體層的開口，於開口中塡入導電材 料，以於開口內形成插塞，於去除第一介電層後，以插塞 與罩幕層爲罩幕，定義導體層以形成導線，其後於基底表 面形成一第二介電層。 於本發明中，導線的定義係使用導體層上的插塞與具 有導線圖案的罩幕層當罩幕，鈾刻導體層，排除了習知自 行對準介層窗製程中，導體層上的插塞易倒塌、光阻不易 塗佈於基底與金屬上、光阻曝光不易…等缺點。且導線與 插塞之間爲自行對準，且插塞比介電層先完成，因此避免 插塞的毒化或破壞介電層結構的缺點。導線上方多了一層 罩幕層，使得導線間凹槽的高寬比增加，有利於空氣間隙 的形成。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A圖〜第1G圖，其繪示依照本發明較佳實施例的 一種內連線的製造流程圖。 圖式之標記說明： 300 :基底 302a :導線 306、322、324 :介電層 310 :插塞 302 :導體層 5 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） Λ2 694522 42〇2twf.d〇c/〇〇8 A7 B7 經濟部中央標举局員工消費合作社印裝 五、發明説明（α ) 304、304a :罩幕層 308 :開口 32〇 :氫化矽倍半氧化物 321 :二氧化矽 32ό :空氣間隙 實施例 請參照第1Α圖〜第1G圖，其繪示依照本發明較佳實 施例的一種內連線的製造流程圖。 請參照第1Α圖，首先提供一基底300，此基底300 已完成半導體元件之製作，比如基底300上已形成金氧半 電晶體元件（未繪示）’在基底300上，形成—層導體層3〇2， 例如使用化學氣相沈積法，而導體層；302例如爲一層金屬 層。然後，於導體層302上形成一層罩幕層3〇4，例如使 用化學氣相沈積法，而此罩幕層3〇4例如爲厚度約3〇〇〜5〇〇 埃的氮化砂、厚度約5〇〇〜1〇〇()埃的氮氧化矽、或厚度約 300〜500埃的氮化鈦。 請參照第1Β圖，定義罩幕層304(第1Α圖），以形成 圖案化：罩幕層304a ’例如使用傳統的微影蝕刻步驟。而罩 幕層3〇4a所具有之圖案與後續導體層302預定形成的導 線圖案相同。再於導體層3〇2與罩幕層3〇4a上形成一介 電層3 06。 §靑麥照第1C圖，定義介電層306與罩幕層304a，例 如使用傳統微影蝕刻法，形成開口 308 ·= 由於罩幕層304a所具有之圖案與後續導體層302預 _ 6 (請先閲讀背面之注意事項再填寫本頁) A' •-•aPrinted by the Central Standards Bureau of the Ministry of Economic Affairs, Consumer Cooperatives 2. ^ (9i ^ .d〇c / nos A7 _B7__ V. Description of the Invention (i) The present invention relates to a method for manufacturing a metal interconnection line ', and in particular has A method for manufacturing a self-aligned interlayer window using an Unlanded Via process in a multi-metal interconnect (Interconnects). When the integration degree of the integrated circuit increases, the surface of the chip cannot be used. When providing enough area to make the required interconnects, 'in order to meet the increased interconnect requirements after the reduction of Metal Oxide Semiconductor (MOS) transistors, the design of two or more metal layers has gradually become The way necessary for many integrated circuits ° Inter-Metal Dielectric is often used to isolate between metal layers 'and a via hole is etched in it' and then in the interlayer window opening The conductive material is used to connect the two upper and lower metal layers. In the semiconductor industry, it is called a plug, and the vias and plugs are collectively called vias. In the design of the interconnect, in order to avoid the misalignment of the wires in the interlayer window, to ensure that the interlayer window is completely in contact with the wires, the wires at the position where the interlayer window is to be formed must have a larger line width. It is a landed via. Because it requires a large chip area, it will waste production costs ^ and make it difficult to increase the degree of component accumulation. Therefore, The requirements are getting higher and higher. In order to reduce the area used by the wires, the width of the interlayer window must be consistent with the wire line width without increasing the wire line width in order to increase the component accumulation. However, because the via window has the same width as the wire, 'the formed via window cannot easily fall on the metal line when the via window is formed', so that a so-called unconnected via window (Unlaruled Via) is formed. 3 (Please read the notes on the back before filling in this page) Ding * ye This paper size is applicable to Chinese National Standard (CNS) Λ4 specification (2IOX297 mm) A 2. 69452 ^ i doc / 008 A7 B7 V. Description of the invention (2) Learning is not followed by type introduction The manufacturing method of the window usually forms a conductive line before the substrate, and then forms a dielectric layer on the substrate and the conductive line, and then defines a dielectric layer to form a dielectric window opening, the opening exposes the conductive line, and a conductive material is inserted into the opening to form a plug. However, due to this process, the opening of the dielectric window cannot be completely aligned with the wires, so that the formed plugs and the dielectric layer between the wires contact each other. If the dielectric layer between the wires has water absorption, it will cause plugs. Poison. If the dielectric layer between the wires has an air gap, the plug may damage the air gap and cause damage to the structure of the dielectric layer. In order to avoid the disadvantages of the aforementioned unattached dielectric window, it is also known to use a self-aligned dielectric window process, which forms a conductor layer on the substrate, a dielectric layer on the conductor layer, and a dielectric layer. The interlayer window is opened, and a conductive material is poured into the interlayer window to form a plug, and then the dielectric layer is removed, so that only the plug remains on the conductor layer. Then, a photoresist is applied, and a lithography etching process is performed so that the conductor layer has a pattern of a conductive line, and then a dielectric layer is formed to complete the manufacture of the interconnects. Printed by the Central Laboratories of the Ministry of Economic Affairs of the Bayer Consumer Cooperative (please read the precautions on the back before filling out this page). However, during this process, plugs are formed on the conductor layer and the dielectric layer on the conductor layer is removed. No dielectric layer is attached, so it is easy to fall. In the subsequent photoresist coating, the photoresist is not easy to be exposed due to the great difference in the height of the substrate surface, and the photoresist is not easy to be coated on the plug and the conductor layer, making it impossible to effectively form the pattern of the conductive wire. The invention provides a method for manufacturing an interconnect. First, a substrate is provided. The substrate has completed the fabrication of semiconductor elements. A conductor layer is formed on the substrate. Then, a cover layer is formed on the conductor layer, the cover layer is patterned, and a first layer is formed on the conductor layer and the cover layer. Dielectric layer, then define the dielectric layer and 4 paper standards applicable to China National Standards (CNS) A4 regulations 1 2 丨 0X29? Public ^ One — 4269 b ^ 4202tn J'.doc / ΟΟδ A7 B7 Central Standard of the Ministry of Economic Affairs Printed by the Consumer Affairs Department of the Municipal Bureau of Du Du. V. Description of the Invention (Clever) Cover the curtain layer to form an opening that exposes the conductive layer. Insert a conductive material into the opening to form a plug in the opening and remove the first dielectric layer. Then, using the plug and the mask layer as a mask, a conductor layer is defined to form a wire, and then a second dielectric layer is formed on the surface of the substrate. In the present invention, the definition of the wire uses the plug on the conductor layer and the mask layer with a wire pattern as the mask, and the conductor layer is etched by uranium. This eliminates the conventional self-aligned interposer window process. The plug is easy to collapse, the photoresist is not easy to be coated on the substrate and the metal, the photoresist is not easy to expose, etc. And the wires and the plug are self-aligned, and the plug is completed before the dielectric layer, so the poisoning of the plug or the disadvantage of destroying the structure of the dielectric layer is avoided. A layer of cover is added above the wires to increase the height-to-width ratio of the grooves between the wires, which is conducive to the formation of air gaps. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: Brief description of the drawings: Figure 1A ~ FIG. 1G is a manufacturing flowchart of an interconnect according to a preferred embodiment of the present invention. Description of drawing marks: 300: substrate 302a: wires 306, 322, 324: dielectric layer 310: plug 302: conductor layer 5 (Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards (CNS) A4 specifications (210X297 mm) Λ2 694522 42〇2twf.d〇c / 〇〇8 A7 B7 Printed by the Consumer Cooperatives of the Central Bureau of the Ministry of Economic Affairs 5. Description of the invention (α) 304, 304a: Cover layer 308: Opening 32: Silicon hydride sesquioxide 321: Silicon dioxide 32; Example of air gap Please refer to FIG. 1A to FIG. 1G, which shows the manufacture of an interconnect according to a preferred embodiment of the present invention flow chart. Please refer to FIG. 1A. First, a substrate 300 is provided. This substrate 300 has completed the fabrication of semiconductor devices. For example, a metal-oxide semiconductor device (not shown) has been formed on the substrate 300. On the substrate 300, a conductive layer is formed. 302, for example, using a chemical vapor deposition method, and the conductor layer; 302, for example, a metal layer. Then, a cover layer 304 is formed on the conductor layer 302, for example, using a chemical vapor deposition method, and the cover layer 304 is, for example, a nitrided sand with a thickness of about 300˜500 angstroms. Silicon nitride oxide with a thickness of about 500 to 100 angstroms, or titanium nitride with a thickness of about 300 to 500 angstroms. Referring to FIG. 1B, the mask layer 304 (FIG. 1A) is defined to form a pattern: the mask layer 304a ', for example, uses a conventional lithographic etching step. The pattern of the mask layer 304a is the same as the pattern of the conductors that are planned to be formed by the subsequent conductor layer 302. Then, a dielectric layer 306 is formed on the conductive layer 300 and the cover layer 304a. § According to Figure 1C, the dielectric layer 306 and the mask layer 304a are defined. For example, the opening 308 is formed using a conventional lithographic etching method. == Because the pattern of the mask layer 304a and the subsequent conductor layer 302 are in advance_ 6 ( Please read the notes on the back before filling out this page) A '•-• a
立、發明説明（t^ 定形成的導線圖案相同’因此將開口 308對準罩幕声 3〇4a ’以於不增加導線線寬之情況下，達到增加^件積^ 度的目的。 請參照第1D圖，於開口 308塡入導電材料，以形成 插塞310，例如使用濺鍍法於介電層3〇6上形成—層導電 材料’再去除介電層3〇6上之導電材料，使導電材料僅存 在於開口 308中。 請參照第1E圖，去除介電層306(第1D圖），例如進 行蝕刻步驟。然後以插塞310與罩幕餍3(Ma爲幕罩，定 我導體層3〇2(第1D圖）’以形成導線3〇2a’定義導體層302 之方法例如進行乾蝕刻步驟。 由於形成導線302a時，係使用插塞310與罩幕層304a 爲幕罩，因此完成導線302a之製作時，雖然插塞31〇無 法很精準地對準罩幕層304a’但其必定位於導線302a之 上方，得到自行對準之目的。避免了習知未接著型介層窗 中導線與插塞因爲沒有對準，而造成插塞的毒化或破壞介 電層結構。 請同時參照第1F圖與第1G圖，於基底300表面形成 介電層材料。例如第1F圖所示，於導線302之間形成有 低介電係數之氫化矽倍半氧化物32〇 ( Hydrogen Silses Quioxane ; HSQ)，隨後再於基底300表面形成一層二氧 化矽321，由二氧化矽321與氫化矽倍半氧化物320共同 形成介電層322 :或如第1G圖所示，於基底300表面形 成一層介電層324，同時控制階梯覆蓋程度，使介電層324 7 本紙浪尺度通用中國阐家樣车（CNS ) A4規格（2Ι〇χ 297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消费合作社印裝 4269 5 2 4202Uvt\doc/008 A7 B7 經濟部中央樣隼局員工消费合作社印聚 五、發明説明（& ) 於導線302a之間的凹槽330中形成空氣間隙326，藉由空 氣的低介電係數特性，使得介電層3M具有低介電係數。 由於本發明與習知相比，導線302a上方多了一層罩幕層 3(Ma’使得凹槽330的闻寬比（Aspect Ration)增加，有利 於空氣間隙326的形成。 由上述本發明較佳實施例可知，應用本發明具有下列 優點。 1) 由於本發明中’導線的定義係使用導體層上的插 塞與具有導線圖案的罩幕層當罩幕，蝕刻導體層， 使導體層具有導線圖案，排除了習知自行對準介層 窗製程中，導體層上的插塞易倒塌' 光阻不易塗佈 於基底與金屬上、光阻曝光不易…等缺點。 2) 導線與插塞之間爲自_行對準’且插塞比介電層先 完成，因此避免了習知未接著型介層窗中導線與插 塞沒有對準而使插塞與導線間的介電層相接觸，而 造成插塞的毒化或破壞介電層結構的缺點^ 3) 本發明與習知相比，導線上方多了一層罩幕層， 使得導線間之凹槽的高寬比增加，有利於空氣間隙 的形成，有效降低介電層的介電係數。 本發明已以較佳實施例揭露如上，然其並非用以限定 本發明，任何熟習此技藝者，在不脫離本發明之精神和範 圍內，當可作各種之更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者爲準。 8 本紙張尺度適用中國國家標率（CNS ) A4規格（210X297公釐） —Γ--^-------, '>衣-- (請先閲讀背面之注意事項再填窝本頁) 訂The invention and the description of the invention (t ^ must be formed with the same pattern of the wire 'so the opening 308 is aligned with the cover sound 304a' so as to increase the volume of the wire without increasing the wire width. Please refer to In FIG. 1D, a conductive material is inserted into the opening 308 to form a plug 310. For example, a sputtering method is used to form a layer of conductive material on the dielectric layer 306. Then, the conductive material on the dielectric layer 306 is removed. The conductive material exists only in the opening 308. Referring to FIG. 1E, the dielectric layer 306 (FIG. 1D) is removed, for example, an etching step is performed. Then, the plug 310 and the cover 餍 3 (Ma is the cover, and fixes The conductor layer 302 (Fig. 1D) 'forms the conductive wire 302a' to define the conductive layer 302, for example, a dry etching step. Since the conductive wire 302a is formed, the plug 310 and the cover curtain layer 304a are used as a curtain cover. Therefore, when the production of the wire 302a is completed, although the plug 31 cannot be accurately aligned with the cover layer 304a ', it must be positioned above the wire 302a for the purpose of self-alignment. Avoiding the conventional unattached interlayer window The middle wire and the plug are misaligned, causing the poison of the plug Or damage the dielectric layer structure. Please refer to FIG. 1F and FIG. 1G at the same time to form a dielectric layer material on the surface of the substrate 300. For example, as shown in FIG. 1F, a low dielectric constant silicon hydride is formed between the wires 302. 32Q (Hydrogen Silses Quioxane; HSQ), and then a layer of silicon dioxide 321 is formed on the surface of the substrate 300, and the dielectric layer 322 is formed by the silicon dioxide 321 and the silicon hydride sesquioxide 320: or as in Section 1G As shown in the figure, a dielectric layer 324 is formed on the surface of the substrate 300, and at the same time, the degree of step coverage is controlled so that the dielectric layer 324 is in the same size as the Chinese car model (CNS) A4 (2Ιχχ 297 mm). Please read the precautions on the back before filling this page) Order printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4269 5 2 4202 Uvt \ doc / 008 A7 B7 Printed by the Consumer Standards Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs ;) An air gap 326 is formed in the groove 330 between the wires 302a, and the low dielectric constant of the air causes the dielectric layer 3M to have a low dielectric coefficient. Since the present invention is compared with the conventional one, the wires 302a are above One more layer The mask layer 3 (Ma 'increases the aspect ratio of the groove 330, which is beneficial to the formation of the air gap 326. As can be seen from the foregoing preferred embodiments of the present invention, the application of the present invention has the following advantages. 1) Because of the present In the invention, the definition of a wire is to use a plug on a conductor layer and a mask layer with a wire pattern as a mask. The conductor layer is etched so that the conductor layer has a wire pattern, which eliminates the conventional self-aligned via window process. The plug on the conductor layer is easy to collapse. The photoresist is not easy to be coated on the substrate and metal, and the photoresist is not easy to expose. 2) The wires and plugs are self-aligned and the plugs are completed before the dielectric layer, so it is avoided that the wires and plugs are not aligned in the conventional non-adhesive type interlayer window and the plugs and wires are not aligned. Disadvantages of poisoning of the plug or damage to the structure of the dielectric layer due to the contact between the dielectric layers ^ 3) Compared with the prior art, the present invention adds a layer of cover layer over the wires, so that the height of the grooves between the wires is high. Increasing the aspect ratio is conducive to the formation of the air gap and effectively reduces the dielectric constant of the dielectric layer. The present invention has been disclosed as above with preferred embodiments, but it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. 8 This paper size applies to China's National Standards (CNS) A4 specification (210X297 mm) —Γ-^ -------, '> clothing-(Please read the precautions on the back before filling the book Page) order