經濟部中央標準局員工消費合作社印製 1 588TWF.D〇c/Frank/0G2 A7 .. ___B7 五、發明説明（丨） 本發明是有關於一種介層窗的製造方法，且特別是有 關於一種利用氮化矽自我對準蝕刻（Self-Align Etching)形 成介層窗的方法。 在目前積體電路積集度增加，使得晶片表面無法提供 足夠的面積來製作所需的內連線（Interconnect)，因此必須 進行多重金屬化製程，而爲了連接上下不同之金屬層，則 必須製作介層窗。當設計法則（Design Rules)愈趨細密之 後，介層窗的偏差也要求愈嚴格。 習知的介層窗製作如第1A-1D圖所示，首先請參照第 1A圖’提供一已形成至少一個金氧半元件之平面丨〇，在 平面10表面形成一電導體層12，例如是複晶矽層或金屬 層’接著定義電導體層12的圖案，形成複數條電導線12a， 如第1B圖所示。 之後，請參照第1C圖，在電導線12a與平面10表面 形成一介電層14，例如是以化學氣相沈積法形成一二氧化 矽層，再以化學機械硏磨法對介電層14進行平坦化製程。 接著，定義介電層14的圖案，形成複數個介層窗16。 最後，請參照第1D圖，在介層窗16中形成鎢插塞17， 以及在介電層14與鎢插塞17表面形成一金屬層18，並定 義金屬層18，完成金屬內連線的製作。 上述習知的介層窗製造方法中，在定義介電層14的圖 案時易產生偏移而對不準，且當電導線12a寬度小於0.6μιη 時，必須增加一對準區（B〇ne Area)以避免過大的誤差。此 外，也可能會造成過度蝕刻至下層的電導線12a。 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1^-I一------C-------tT------基 (讀先閱讀背面之注意事項再填寫本頁) I 5 88TWF.DOC/Frank/〇〇2 A7 B7 經濟部中央標準局員工消費合作社印裂 五、發明説明（X) 因此本發明的主要目的就是在提供一種介層窗的製 造方法’利用對氮化矽選擇性的蝕刻，可在所要的位置準 確的形成介層窗，不致產生偏移；且由於對氮化矽有選擇 性，不會過度蝕刻至下層之電導線。 本發明的另一目的就是在提供一種介層窗的製造方 .法，在電導線寬度小於〇.6μιη時，也不需增加對準區的製 作。 本發明一種介層窗的製造方法，包括 (a) 提供一已形成至少一金氧半元件之平面，在該平面 表面依序形成一電導體層與一氮化矽層； (b) 同時定義該氮化矽層與該電導體層之圖案，形成複 數條電導線； (c) 在該平面與該氮化矽層表面形成一介電層，使介電 層塡滿該些電導線之間，並覆蓋該氮化矽層； (d) 以化學機械硏磨法磨除該介電層，並以該氮化矽層 爲終止層；以及 (e) 塗佈一光阻層，並定義該光阻層之圖案，露出部份 該氮化矽層，以選擇性鈾刻去除露出之該氮化矽層，形成 複數個介層窗，之後去除該光阻層。 本發明另一種介層窗的製造方法，包括： (a) 提供一已形成至少一金氧半元件之平面，在該平面 表面依序形成一電導體層與一氮化矽層； (b) 同時定義該氮化矽層與該電導體層之圖案，形成複 數條電導線； 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X2.97公釐） ^ c1T0Φ (諳先閣讀背面之注意事項再填寫本頁) 1 588TWF,DOC/Frank/002 - A7 _____B7 五、發明説明（B ) (C)塗佈一光阻層，並定義該光阻層之圖案，保留部份 該氮化矽層； (d) 以蝕刻將露出之該氮化矽層去除，以露出該些電導 線，之後去除該光阻層； (e) 在該平面與該些電導線表面形成一介電層，使該介 電層塡滿該些電導線之間，並覆蓋該氮化矽層； (f) 以化學機械硏磨法對該介電層進行平坦化製程，並 以該氮化矽層爲終止層；以及 (g) 對留存之該氮化矽層進行自我對準蝕刻，形成複數 個介層窗。. 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A-1D圖是習知一種介層窗的製造流程圖； 第2A-2F圖是依照本發明第一較佳實施例，一種介層 窗的製造流程圖；以及 經濟部中央標準局員工消費合作社印製 (請先閔讀背面之注意事項再填寫本頁) 第3A-3G圖是依照本發明第二較佳實施例，一種介層 窗的製造流程圖。 實施例 第2A-2F圖是依照本發明第一較佳實施例一種介層窗 的製造方法。首先請參照第2A圖，由於介層窗在半導體 製程中隨處可見，因此在此僅介層窗的製作部份做說明， 以一平面代替基底與基底上所形成之金氧半元件，提供一 5 ϋ張尺度適用中國^&準（CNS ) A4規格(210X297公釐〉 ~ " 經濟部中央標準局貝工消費合作社印製 1 588TWF.DOC/Frank/0^2 ^ _ --------- B7 _ -_. 五、發明説明（) 已形成至少一個金氧半元件之平面2〇，在平面2〇表面依 序形成一電導體層21與一氮化矽層22，電導體層21例如 是複晶矽層或是金屬靥。接著同時定義電導體層21與氮化 矽層22的圖案’形成複數條電導線21a與氮化矽層22a， 如第2B圖所示之結構。 之後，請參照第2e圖，在平面20與氮化矽層22a表 面形成一介電層23 ’例如是以化學氣相沈積法形成之二氧 化砂層’使介電層23塡滿電導線21a之間並將整個氮化矽 層22a覆蓋住。接著利用化學機械硏磨法磨除介電層23 ’ 並以氮化砂層22a爲終止層，得到如第2D圖所示之結構。 接著，請參照第圖，塗佈一光阻層24，並定義光 阻層24的圖案’在欲形成介層窗的位置露出氮化矽層 22a。再以自我對準蝕刻氮化矽層22a而不蝕刻介電層23， 形成介層窗25 ’露出電導線21a，之後去除光阻層24。 由於是以自我對準蝕刻去除氮化矽層22a，因此在定義光 阻層24.圖案時’即使將圖案定義大一些，也不會產生偏差 現象。 最後請參照第2F圖，在介層窗25中形成鎢插塞26， 然後在表面形成一金屬層27，並定義金屬層27形成內連 線，完成金屬內連線製作。 第3A-3G圖是依照本發明第一較佳實施例一種介層窗 的製造方法。首先請參照第3A圖，提供一已形成至少一 個金氧半元件之平面30，在平面30表面依序形成一電導 體層31與一氮化矽層32，電導體層31例如是複晶矽層或 6 ~ .· -------- . _ — ' - - - . · 本紙張尺度適用中國國家標準{ C.NS ) A4規格（210X297公釐.） (請先聞讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 1 588TWF.D0c / Frank / 0G2 A7 .. ___B7 V. Description of the Invention (丨) The present invention relates to a method for manufacturing an interlayer window, and in particular to a Method for forming interlayer window by using self-aligned etching of silicon nitride (Self-Align Etching). At present, the degree of accumulation of integrated circuits has increased, so that the surface of the chip cannot provide enough area to make the required interconnects. Therefore, multiple metallization processes must be performed. In order to connect different metal layers above and below, it is necessary to make Through window. As the design rules become more and more detailed, the deviation of the via window is also required to be stricter. The conventional fabrication of the interlayer window is shown in Figures 1A-1D. First, please refer to Figure 1A 'to provide a plane on which at least one metal-oxygen half element has been formed. An electrical conductor layer 12 is formed on the surface of the plane 10, such as It is a polycrystalline silicon layer or a metal layer 'and then defines the pattern of the electrical conductor layer 12 to form a plurality of electrical wires 12a, as shown in FIG. 1B. Then, referring to FIG. 1C, a dielectric layer 14 is formed on the surface of the electrical wires 12a and the plane 10. For example, a silicon dioxide layer is formed by a chemical vapor deposition method, and then the dielectric layer 14 is subjected to a chemical mechanical honing method. Perform a planarization process. Next, a pattern of the dielectric layer 14 is defined to form a plurality of interlayer windows 16. Finally, referring to FIG. 1D, a tungsten plug 17 is formed in the dielectric window 16, and a metal layer 18 is formed on the surface of the dielectric layer 14 and the tungsten plug 17, and the metal layer 18 is defined to complete the metal interconnection. Production. In the above-mentioned conventional method for manufacturing a dielectric window, an offset is easily generated when the pattern of the dielectric layer 14 is defined, and when the width of the electrical wire 12a is less than 0.6 μm, an alignment region (Bone) must be added. Area) to avoid excessive errors. In addition, it may cause over-etching to the underlying electrical wires 12a. 3 This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 1 ^ -I 一 ------ C ------- tT ------ based (read first read the back Please note this page before filling in this page) I 5 88TWF.DOC / Frank / 〇〇2 A7 B7 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of the Invention (X) Therefore, the main purpose of the present invention is to provide an interlayer. The manufacturing method of the window 'utilizes selective etching of silicon nitride, so that an interlayer window can be accurately formed at a desired position without offset; and because it is selective to silicon nitride, it does not over-etch to the lower layer of electricity. wire. Another object of the present invention is to provide a method for manufacturing an interlayer window. When the width of the electrical wire is less than 0.6 μm, it is not necessary to increase the production of the alignment area. A method for manufacturing an interlayer window according to the present invention includes (a) providing a plane on which at least one metal-oxygen half element has been formed, and sequentially forming an electrical conductor layer and a silicon nitride layer on the plane surface; (b) simultaneously defining Patterning the silicon nitride layer and the electrical conductor layer to form a plurality of electrical wires; (c) forming a dielectric layer on the plane and the surface of the silicon nitride layer, so that the dielectric layer fills between the electrical wires And covering the silicon nitride layer; (d) removing the dielectric layer by chemical mechanical honing, and using the silicon nitride layer as a termination layer; and (e) coating a photoresist layer and defining the In the pattern of the photoresist layer, a part of the silicon nitride layer is exposed, and the exposed silicon nitride layer is removed by selective uranium etching to form a plurality of interlayer windows, and then the photoresist layer is removed. Another method for manufacturing an interlayer window according to the present invention includes: (a) providing a plane on which at least one metal-oxygen half element has been formed, and sequentially forming an electrical conductor layer and a silicon nitride layer on the plane surface; (b) At the same time, the pattern of the silicon nitride layer and the electrical conductor layer is defined to form a plurality of electrical wires; 4 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X2.97 mm) ^ c1T0Φ (谙 xiange read the back of the Please fill in this page again for attention) 1 588TWF, DOC / Frank / 002-A7 _____B7 V. Description of the Invention (B) (C) Apply a photoresist layer and define the pattern of the photoresist layer, leaving a part of the nitride A silicon layer; (d) removing the exposed silicon nitride layer by etching to expose the electrical leads, and then removing the photoresist layer; (e) forming a dielectric layer on the plane and the surfaces of the electrical leads, Filling the dielectric layer between the electrical wires and covering the silicon nitride layer; (f) performing a planarization process on the dielectric layer by a chemical mechanical honing method, and ending with the silicon nitride layer Layer; and (g) performing self-aligned etching on the remaining silicon nitride layer to form a plurality of vias. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings, as follows: Brief description of the drawings: Section 1A Figure -1D is a conventional manufacturing flow chart of interstitial windows; Figures 2A-2F are manufacturing flowcharts of a interstitial window in accordance with the first preferred embodiment of the present invention; (Please read the notes on the back before filling out this page) Figures 3A-3G are flowcharts of the fabrication of an interlayer window according to the second preferred embodiment of the present invention. Embodiments Figs. 2A-2F show a method for manufacturing an interlayer window according to a first preferred embodiment of the present invention. First, please refer to FIG. 2A. Since the via window can be seen everywhere in the semiconductor manufacturing process, only the fabrication part of the via window will be described here. A plane is used instead of the substrate and the metal-oxide half-elements formed on the substrate. 5 Dimensions for China ^ & quasi (CNS) A4 (210X297 mm) ~ " Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 1 588TWF.DOC / Frank / 0 ^ 2 ^ _ ---- ----- B7 _ -_. V. Description of the invention () A plane 20 having at least one metal-oxygen half element has been formed, and an electrical conductor layer 21 and a silicon nitride layer 22 have been sequentially formed on the surface of the plane 20, The electric conductor layer 21 is, for example, a polycrystalline silicon layer or a metal hafnium. Next, the pattern of the electric conductor layer 21 and the silicon nitride layer 22 is defined simultaneously to form a plurality of electric wires 21a and the silicon nitride layer 22a, as shown in FIG. 2B. Then, referring to FIG. 2e, a dielectric layer 23 is formed on the surface of the plane 20 and the silicon nitride layer 22a, for example, a sand dioxide layer formed by a chemical vapor deposition method, so that the dielectric layer 23 is fully charged. Between the wires 21a and covering the entire silicon nitride layer 22a. Then the dielectric layer is removed by chemical mechanical honing 23 'and using the nitrided sand layer 22a as the termination layer to obtain the structure shown in Figure 2D. Next, please refer to the figure, apply a photoresist layer 24, and define the pattern of the photoresist layer 24' The silicon nitride layer 22a is exposed at the position of the layer window. The silicon nitride layer 22a is etched by self-alignment without etching the dielectric layer 23 to form a dielectric window 25 'to expose the electrical leads 21a, and then the photoresist layer 24 is removed. The silicon nitride layer 22a is removed by self-aligned etching, so when defining the pattern of the photoresist layer 24. 'Even if the pattern is defined larger, no deviation will occur. Finally, please refer to FIG. 2F in the interlayer window 25. A tungsten plug 26 is formed, and then a metal layer 27 is formed on the surface, and the metal layer 27 is defined to form an interconnector, and the fabrication of the metal interconnector is completed. Figures 3A-3G show a via layer according to the first preferred embodiment of the present invention. A method for manufacturing a window. First, referring to FIG. 3A, a plane 30 having at least one metal-oxygen half element formed is provided, and an electric conductor layer 31 and a silicon nitride layer 32 are sequentially formed on the surface of the plane 30. The electric conductor layer 31 For example, a polycrystalline silicon layer or 6 ~ .. --------. _ — '---. · This paper size applies the Chinese National Standard {C.NS) A4 specification (210X297 mm.) (Please read the precautions on the back before filling this page)
! 588TWF.DOC/Frank/002 -A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（f) 是金屬層。接著同時定義電導體層31與氮化矽層32的圖 案，形成複數條電導線31a與氮化矽層32a，如第3B.圖所 示之結構。 接著，請參照第3C圖，在平面30與氮化矽層32a表 .面塗佈一光阻層33，並定義光阻層33的圖案，保留欲形 成介層窗位置之氮化矽層32a，之後將露出之氮化矽層32a 去除，再將光阻層33去除，得到如第3D圖所示之結構。 之後，請參照第3E圖，在上述各層表面形成一介電層 34，例如是以化學氣相沈積法形成之二氧化矽層，並使介 電層34厚度至少高於氮化矽層32a。再以化學機械硏磨法 對介層34進行平坦化製程，以氮化砂層32a爲終止層。 然後，請參照第3F圖，對留存之氮化矽層32a進行選 擇性蝕刻，僅蝕刻氮化矽層32a而保留二氧化矽材質之介 電層34，形成介層窗35，露出下方之電導線31a。 最後請參照第3G圖，在介層窗35中形成鎢插塞36， 然後在表面形成一金屬層37，並定義金屬層37形成內連 線，完成金屬內連線製作。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先鬩讀背面之注意事項再填寫本頁) -訂- 線-588TWF.DOC / Frank / 002 -A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of Invention (f) is a metal layer. Next, the patterns of the electrical conductor layer 31 and the silicon nitride layer 32 are defined simultaneously to form a plurality of electrical wires 31a and the silicon nitride layer 32a, as shown in the structure shown in FIG. 3B. Next, referring to FIG. 3C, a photoresist layer 33 is coated on the surface 30 and the silicon nitride layer 32a, and the pattern of the photoresist layer 33 is defined, and the silicon nitride layer 32a where the interposer window is to be formed is reserved. Then, the exposed silicon nitride layer 32a is removed, and then the photoresist layer 33 is removed to obtain the structure shown in FIG. 3D. Then, referring to FIG. 3E, a dielectric layer 34, such as a silicon dioxide layer formed by a chemical vapor deposition method, is formed on the surface of each layer, and the thickness of the dielectric layer 34 is at least higher than that of the silicon nitride layer 32a. Then, a planarization process is performed on the interlayer 34 by a chemical mechanical honing method, and the nitrided sand layer 32a is used as a termination layer. Then, referring to FIG. 3F, the remaining silicon nitride layer 32a is selectively etched, and only the silicon nitride layer 32a is etched while the dielectric layer 34 made of silicon dioxide is retained, and a dielectric window 35 is formed to expose the underlying electrical Lead 31a. Finally, referring to FIG. 3G, a tungsten plug 36 is formed in the interlayer window 35, and then a metal layer 37 is formed on the surface, and the metal layer 37 is defined to form an interconnect, and the metal interconnect is completed. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 7 This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page) -Order-Line-