JP2000223492A - Manufacture of semiconductor device having multilayer wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacture of a semiconductor device having multilayer wiring which provides the wiring structure having removed the discrepancy of dimensions and film thickness between a groove wiring congested section and an isolated section and also solves the problem of the erosion in chemical mechanical polishing(CMP) of metallic material at the same time. SOLUTION: Resist patterns are made at specified wiring intervals on an interlayer film, and with the pattern as a mask, a groove to serve as a wiring layer, and a discontinuous groove or a hole not to serve as a wiring layer are made, and then groove to serve as that wiring layer and the discontinuous groove or hole which do not serve as the wiring layer are filled with metal, and the surface is flattened by chemical-mechanical polishing, whereby dummy groove wiring 13 is arranged at the same pitch as the wiring congested section 12a, at the space section around the wiring isolated section.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring, and more particularly, to a method of providing a wiring structure in which the dimensions and thicknesses of a densely packed portion and an isolated portion of a trench wiring are eliminated. .

[0002]

2. Description of the Related Art Conventionally, as a method of forming a multilayer wiring,
A method of forming a metal film directly on a wiring pattern by photolithography has been adopted. At this time, when the pattern includes a sparse part and a dense part, there is a problem that the wiring width is different in each part because the etching rate is different due to the sparseness of the wiring.

In order to solve this problem, it has been proposed to provide a dummy pattern to eliminate the variation in the shape of the wiring pattern due to the density of the pattern. For example, in Japanese Unexamined Patent Publication No. Hei 3-180041, dummy wiring layers not connected to other wiring layers are arranged at the minimum pitch of the design rule in order to suppress variation in dimensions due to the loading effect of etching. It is stated that the loading is suppressed. Also, JP-A-6-333928
In Japanese Patent Application Laid-Open Publication No. H11-157, a dummy wiring layer is provided so that the pattern density of the wiring layer occupying the semiconductor substrate is about 30% or more, thereby causing variations in the shape and processing dimensions of the wiring layer due to the density of the pattern, It is said that the decrease in flatness due to the sparseness of the density is eliminated.

However, such a dummy wiring has a problem that the capacitance of the adjacent wiring is greatly increased.
In particular, a problem has arisen that when the wiring is miniaturized, the dummy wiring layer collapses and causes a wiring short circuit.

Japanese Patent Application Laid-Open Nos. 10-209390 and 10-189770 disclose the formation of a dummy wiring layer for the purpose of improving the flatness of a film formed on a wiring pattern.

On the other hand, even in the photolithography process for forming the trench wiring, when the wiring pitch is 0.8 μm or less, there is a problem that the dimensions of the pattern, particularly the wiring formed, depend on the density of the wirings. FIG. 6 (a) shows a pattern processed so that an isolated wiring portion can be patterned according to a mask dimension, and FIG. 6 (b) shows a pattern obtained when a densely-connected wiring section conforms to a mask size. Due to the density of the pattern due to irregular reflection of light and the like, the wiring size of the dense portion becomes large in (a), and the size of the isolated portion becomes small in (b).
If the processing dimension is 0.35 μm or less, the dense part and the isolated part cannot be simultaneously and accurately processed by the photolithography technique generally used at present.

In the case of forming a trench wiring, as shown in FIG. 7A, after a barrier film 14 is formed in a groove formed in an insulating film as required, a metal material 15 is buried and polished. A method of flattening the surface has been adopted, and currently, a method of polishing mainly by a chemical mechanical polishing (CMP) method has been adopted. However, as shown in FIG. 7B, there has been a problem that the wiring height after polishing is different between the densely interconnected portion and the isolated portion in CMP of a metal material such as tungsten (erosion).

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring structure in which the dimensions and thicknesses of a densely packed portion and an isolated portion of a grooved wiring are eliminated, and the problem of erosion in CMP of a metal material is eliminated. Another object of the present invention is to provide a method of manufacturing a semiconductor device having a multilayer wiring, which can be solved at the same time.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention comprises forming an interlayer film on a substrate of a semiconductor device on which a first-layer wiring or contact is formed, and communicating with the first-layer wiring or contact in the interlayer film. A semiconductor having a multilayer wiring in which a groove for forming a wiring layer to be formed and a wiring layer which is not communicated is formed by photolithography, a metal material is buried in the groove, and the surface is flattened by a chemical mechanical polishing method to form a buried wiring. In the method of manufacturing a device, a resist pattern is formed at a predetermined wiring interval on the interlayer film, and a groove serving as a wiring layer and a discontinuous groove or hole not serving as a wiring layer are formed using the pattern as a mask. A step of embedding metal in a groove serving as a layer and a discontinuous groove or hole not serving as a wiring layer, and performing a surface planarization by a chemical mechanical polishing method, or a semiconductor. Forming a first interlayer film, an etching stopper film, and a second interlayer film on the substrate on which the elements are formed; forming a resist pattern on the second interlayer film at predetermined wiring intervals; Forming a groove to be a wiring layer and a discontinuous groove or hole not to be a wiring layer, and applying a material having an antireflection effect to the groove to be a wiring layer and the discontinuous groove and / or hole not to be a wiring layer. Embedding, flattening the surface, forming a resist pattern corresponding to the groove serving as the wiring layer on a material having an antireflection effect, and using the pattern as a mask to form a material having an antireflection effect and a first interlayer film. A step of forming a contact hole by etching, after removing the resist pattern and the material having an antireflection effect, a groove serving as a wiring layer and a discontinuous groove or hole which does not serve as a wiring layer; Embedding a metal in a method for manufacturing a semiconductor device having a multilayer interconnection comprising the step of carrying out surface planarization by chemical mechanical polishing.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, dummy groove wirings are arranged at the same pitch as a densely arranged wiring in a space around an isolated wiring. As a result, there is no difference in the density of the wiring, and the groove wiring having the same dimensions as the mask can be formed uniformly.
In addition, when polishing the wiring metal, it is possible to eliminate the difference in wiring height caused by the difference in wiring density.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to embodiments.

Embodiment 1 FIGS. 1 and 2 are process cross-sectional views showing a manufacturing process of a semiconductor device having a multilayer wiring according to an embodiment of the present invention.

First, a trench 2 is formed on a P-type silicon substrate 1.
Is used to form an element isolation region. Thereafter, a MOS transistor 4 is formed by introducing impurities such as boron and arsenic by ion implantation and using a gate electrode using polysilicon 3. In order to reduce the connection resistance with a contact plug or the like in a later step, a metal such as titanium is formed on the source / drain region and the gate electrode of the MOS transistor 4 and silicidized to form a silicide layer 5. deep. Next, a silicon oxide film (BPSG film) 6 containing phosphorus and boron is formed as an interlayer insulating film to a thickness of 800 nm to 1 μm. After a contact hole is opened in the silicon oxide film 6 by a commonly used photolithography step and dry etching step, the contact hole is filled with a metal such as tungsten to form a contact plug 7 (FIG. 1A).

Subsequently, in order to form a first layer wiring, a silicon oxide film is formed as an interlayer insulating film 8 to a thickness of 400 to 600 nm by a plasma CVD method. Next, the photoresist 9 is patterned by photolithography.
The dummy pattern 11 is arranged around 0b (FIG. 2).
(B)). The dummy pattern 11 is, as shown in FIG.
The wiring pattern is formed in a rectangular pattern, and the wiring interval is an interval from the minimum pitch to 1.5 times the minimum pitch, and the wiring length direction is formed to be two to three times the minimum wiring width. For example,
Assuming that the minimum wiring pitch is 0.5 μm, the minimum dummy pattern is about 0.25 μm × 0.5 μm.

Next, as shown in FIG. 1C, C ₄ F ₈ ,
The wiring grooves 12a and 12b and the dummy wiring grooves 13 are formed in the interlayer insulating film 8 by a technique such as reactive ion etching (RIE) using a gas such as CHF ₃ .

Next, a metal material is buried in the trenches 12 and 13. At this time, titanium nitride is formed to a thickness of about 50 nm as a barrier film 14 by a sputtering method for the purpose of improving the adhesion to the interlayer insulating film 8. . Thereafter, tungsten is deposited as a metal material 15 on the entire surface by CVD (FIG. 2).
(D)).

Finally, unnecessary portions of the metal material 15 and the barrier film 14 are removed by a CMP method to form a wiring 16 (FIG. 2E).

In this embodiment, in the photolithography process for forming the trench wiring, the wiring width of the densely interconnected portion and the isolated wire portion can be formed with the same precision.
This is because, by arranging the dummy patterns 11 around the isolated wiring pattern 10b at substantially the same pitch as the minimum wiring pitch, the influence of light reflection and the like at the time of exposure of the photoresist 9 can be made the same as that of the wiring dense portion.

Further, in the CMP process for forming the trench wiring, a difference in the wiring height due to a difference in the polishing amount between the densely packed part and the isolated wiring part can be suppressed by forming the dummy wiring 17. This is because the ratio of exposing the interlayer insulating film 8 is substantially the same between the densely interconnected portion and the isolated wire portion, so that the polishing amount can be substantially the same in any pattern in the chip.

In the above example, tungsten is exemplified as the metal material to be embedded. However, the present invention is not limited to this, and copper and aluminum can be similarly formed.

Embodiment 2 Another embodiment of the present invention will be described with reference to FIGS. 4 and 5 are process cross-sectional views showing a process for manufacturing a semiconductor device having a multilayer wiring according to another embodiment.

As in the first embodiment, a silicon oxide film (BPSG film) 6 is formed on a silicon substrate 1 having a MOS transistor 4 in a region defined by the trench isolation 2.
Formed to a thickness of 00 nm to 1 μm, and then made of SiN or SiON as an etching stopper film 17 when forming a trench wiring.
A film having a thickness of 0 to 100 nm is formed. Furthermore, an interlayer insulating film 8 is further formed thereon.
A silicon oxide film by plasma CVD
A film having a thickness of about 600 nm is formed (FIG. 4A).

Next, the wiring groove is patterned by photolithography.
A dummy wiring groove 13 is arranged around 2b. The pattern of the dummy wiring groove formed at this time is the same as that of the first embodiment (FIG. 4B).

Next, after filling the grooves formed in the interlayer insulating film 8 with a coating film 18 having an antireflection effect such as organic SOG, a photoresist 9 is applied and formed, and a photolithography process and a dry etching process are performed. Thus, a pattern for forming a contact hole leading to the source / drain region of the MOS transistor 4 is formed in the photoresist 9, and the anti-reflection film 18 exposed in the opening is formed on the silicon oxide film 6 by oxygen plasma ashing or the like. It is removed by wet etching or the like (FIG. 4C).

After removing the photoresist 9 and the antireflection film 18 (FIG. 5A), titanium nitride as a barrier film 14 is sputtered for the purpose of improving the adhesion to the silicon oxide film as in the first embodiment. A film is formed to a thickness of about 50 nm by a method, and then a 500-800 nm-thick tungsten film is formed as a metal material 15 on the entire surface by a CVD method (FIG. 5B).

Finally, unnecessary portions of the metal material 15 and the barrier film 14 are removed by the CMP method to form the wiring 16 (FIG. 5C).

[0027]

According to the present invention, it is possible to eliminate the dimensional deviation between the densely interconnected portion and the isolated portion by forming the groove pattern serving as the wiring layer and the groove or hole pattern not serving as the wiring layer at the same pitch. After the metal material is buried in the formed groove serving as the wiring layer and the groove or hole not serving as the wiring layer, and the CMP is performed, the wiring height can be prevented from being shifted due to the erosion.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view of a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of the manufacturing process following FIG. 1;

FIG. 3 is a plan view of a wiring pattern and a dummy pattern formed in FIG.

FIG. 4 is a process sectional view of a manufacturing process according to another embodiment of the present invention.

FIG. 5 is a cross-sectional view of the manufacturing process continued from FIG. 4;

FIG. 6 is a conceptual diagram illustrating a problem of a conventional photolithography process.

FIG. 7 is a schematic cross-sectional view illustrating a problem caused by a conventional CMP method.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 trench isolation 3 polysilicon 4 MOS transistor 5 silicide layer 6 silicon oxide film 7 contact plug 8 interlayer insulating film 9 photoresist 10 wiring pattern 10a dense part 10b isolated part 11 dummy pattern 12 wiring groove 12a dense part 12b isolated Part 13 Dummy wiring groove 14 Barrier film 15 Metal material 16 First layer wiring 17 Dummy wiring 18 Etching stopper film 19 Antireflection film 20 Contact hole

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference)

Claims (7)

[Claims] An interlayer film is formed on a substrate of a semiconductor device on which a first-layer wiring or a contact is formed, and a wiring layer communicating with the first-layer wiring or the contact and a wiring layer not communicating with the first layer are formed on the interlayer film. Forming a groove by photolithography, embedding a metal material in the groove, and flattening the surface by chemical mechanical polishing to form a buried wiring. After forming a resist pattern at a wiring interval of, and using the pattern as a mask to form a groove serving as a wiring layer and a discontinuous groove or hole not serving as a wiring layer, it is not possible to form a groove serving as the wiring layer and a wiring layer. A method of manufacturing a semiconductor device having a multi-layered wiring, comprising a step of embedding a metal in a continuous groove or hole and flattening the surface by chemical mechanical polishing. 2. The method according to claim 1, wherein the resist pattern formed on the interlayer film at a predetermined wiring interval has a wiring interval that is 1 to 2 times a minimum pitch of photolithography. A method for manufacturing a semiconductor device having a multilayer wiring. 3. The semiconductor having a multilayer wiring according to claim 1, wherein a longitudinal direction of the discontinuous groove or hole which does not become the wiring layer has a length of a minimum wiring width of two to three. Device manufacturing method. 4. The method according to claim 1, further comprising the step of:
Forming a resist pattern at a predetermined wiring interval in the second interlayer film, and using the pattern as a mask to form a groove and a wiring layer that become a wiring layer. Forming a discontinuous groove or hole that does not become a material, embedding a material having an anti-reflection effect into the groove that becomes the wiring layer and the discontinuous groove or a hole that does not become the wiring layer,
Flattening the surface, forming a resist pattern corresponding to the groove serving as the wiring layer on a material having an antireflection effect, and etching the material having an antireflection effect and the first interlayer film using the pattern as a mask. After removing the resist pattern and the material having an anti-reflection effect, a metal is buried in a groove serving as a wiring layer and a discontinuous groove or hole not serving as a wiring layer, and is subjected to a chemical mechanical polishing method. A method for manufacturing a semiconductor device having a multi-layer wiring, the method including a step of flattening a surface. 5. The wiring pattern according to claim 4, wherein the resist pattern formed on the interlayer film at a predetermined wiring interval has a wiring interval that is 1 to 2 times a minimum pitch of photolithography. A method for manufacturing a semiconductor device having a multilayer wiring. 6. The semiconductor having a multilayer wiring according to claim 4, wherein the longitudinal direction of the discontinuous groove or hole that does not become the wiring layer has a length of a minimum wiring width of two to three. Device manufacturing method. 7. The material having an antireflection effect is an organic SO.
The method for manufacturing a semiconductor device having a multilayer wiring according to claim 4, wherein G is G.