JP2004363254A - Semiconductor device and its fabricating process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing plasma charging damage in plasma process, and to provide its fabricating process. <P>SOLUTION: At least a laminate of a gate insulation film 6 and a gate electrode 7, and an active region 13 are formed on a silicon substrate and then an underlying interlayer insulating film 10 is also formed. An interconnect line 11a being connected with the gate electrode 7 and an interconnect line 11b being connected with the active region 13 and becoming a dummy interconnect line are formed simultaneously on the underlying interlayer insulating film 10. Subsequently, an interlayer insulating film 12 is formed on the underlying interlayer insulating film 10 by plasma process. Charging current from a plasma 14 is discharged by the interconnect line 11b becoming the dummy interconnect line. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, high integration of a semiconductor device including a semiconductor integrated circuit has been greatly advanced. In particular, in a MIS (Metal Insulated Semiconductor) type semiconductor device, elements such as transistors have been miniaturized and improved in performance in order to cope with higher integration, and further miniaturization and higher performance have been demanded. Have been.
[0003]
In the process of forming wiring of such a semiconductor device, use of a plasma process represented by plasma CVD or plasma etching is increasing. This is because the amount of heat treatment is limited in the step of forming wiring of a semiconductor device in terms of diffusion of impurities and heat resistance of metal wiring materials, and the amount of heat treatment can be reduced by the plasma process.
[0004]
Furthermore, in recent years, copper (Cu) wiring may be introduced in order to improve the performance. However, since a damascene method is used for forming the copper (Cu) wiring, in this case, plasma is increasingly used. Increased use of the process.
[0005]
As described above, the plasma process is frequently used not only at the time of etching but also at the time of film formation, and the use of the plasma process is increasing every year. However, as the use of the plasma process increases, device damage due to the plasma process has become apparent. This is mainly referred to as "plasma charging damage" and has been greatly increased in recent years.
[0006]
A semiconductor device that has suffered such plasma charging damage has poor device characteristics and is therefore defective. In the problem of plasma charging damage, deterioration of reliability of the gate insulating film has become a serious problem.
[0007]
Here, the plasma charging damage will be described with reference to FIGS. FIG. 6 is a cross-sectional view partially showing the structure of a conventional semiconductor device, and FIG. 6A is a cross-sectional view taken along a normal direction of a semiconductor substrate forming the semiconductor device, and FIG. FIG. 7 is a cross-sectional view taken along a cutting line CC ′ shown in FIG.
[0008]
As shown in FIG. 6A, the conventional semiconductor device includes an n-type silicon substrate 21. A plurality of element isolations 22 are formed on the silicon substrate 21 by STI (Shallow Trench Isolation) so as to be exposed on the silicon substrate 21 at predetermined intervals.
[0009]
A p-well (p-well) 23 formed inside the silicon substrate 21, a gate insulating film (2.2 nm thick) 26, and n + polysilicon were formed between the element isolations 22 on the silicon substrate 21. An n-channel MOS transistor is formed by the gate electrode 27 and the source (n +) region 24a and the drain (n +) region 24b provided in the surface layer of the silicon substrate 21.
[0010]
The gate insulating film 26 and the gate electrode 27 are formed so as to be aligned with each other, and sidewalls 28 are formed on both sides thereof so as to cover both sides. Reference numeral 35 denotes an n + region, which is an active region functioning as a source region or a drain region of another transistor.
[0011]
On the silicon substrate 21, a base interlayer insulating film 30 and an interlayer insulating film 32 for realizing multilayer wiring are sequentially laminated. Wirings 31 a to 31 c are formed in the underlying interlayer insulating film 30. The wirings 31 a to 31 c are copper wirings (thickness: 500 nm) formed by a damascene method, and are embedded in the underlying interlayer insulating film 30.
[0012]
The wiring 31a is a gate electrode connection wiring connected to the gate electrode 27 via the W plug 29b. The wiring 31c is a source / drain connection wiring connected to the n + region 25 via the W plug 29a. The wirings 31a and 31c are formed in a strip shape as shown in FIG.
[0013]
The W plugs 29a and 29b are formed by filling contact holes formed in the underlying interlayer insulating film 30 with tungsten. Note that W plug 29a is formed to connect to n + region 25, and W plug 29b is formed to connect to gate electrode 27.
[0014]
The wiring 31b is a dummy wiring for ensuring flatness in a CMP (chemical mechanical polishing) process performed by a damascene method, and is formed adjacent to the wiring 31a. As shown in FIG. 6B, the wiring 31b is formed of a plurality of pieces and is formed in a square shape. The entire periphery of the wiring 31b is insulated by the underlying interlayer insulating film 30 and the interlayer insulating film 32, and is in an electrically floating state.
[0015]
FIG. 7 is a cross-sectional view showing a step of forming an interlayer insulating film in the conventional semiconductor device shown in FIG. 6, and conceptually shows occurrence of plasma charging damage.
[0016]
First, a gate insulating film 26 is formed on a silicon substrate 21 provided with an element isolation 22 and a p-well 23. Next, a gate electrode 27 is formed on the gate insulating film 26, and sidewalls 28 are formed on both side surfaces of the gate insulating film 26 and the gate electrode 27. Next, an n + region 25, a source (n +) region 24a, and a drain (n +) region 24b are formed by ion implantation, and a base interlayer insulating film 30 is formed.
[0017]
Next, after forming the W plugs 29a and 29b in the underlying interlayer insulating film 30, the wirings 31a to 31c are simultaneously formed using the damascene method. Specifically, a groove is formed at a position in the base interlayer insulating film 30 where the wirings 31a to 31c are to be provided, and a copper layer is formed so as to fill the groove, and then an excess thickness is removed by polishing by a CMP method. .
[0018]
Next, as shown in FIG. 7, a plasma 33 is generated by a plasma CVD apparatus (not shown), and an interlayer insulating film 32 is formed. In this case, the wiring 31b is electrically floating as described above, and the wiring 31c is directly connected to the silicon substrate 21, so that the charging current from the plasma 33 is applied to the gate electrode 27 and the gate insulating film 26. Will flow to For this reason, the gate insulating film 26 is destroyed, and the device characteristics deteriorate.
[0019]
In order to solve such a problem, Patent Document 1 discloses a semiconductor device in which a protection diode connected to a gate electrode is provided on a semiconductor substrate. In the semiconductor device disclosed in Patent Literature 1, a charging current causing plasma charging damage is released to an installation potential via a protection diode. Therefore, application of a charging current to the gate insulating film is suppressed, and destruction of the gate insulating film is avoided.
[0020]
[Patent Document 1]
JP-A-10-173157 (Paragraph 20, FIG. 2 to FIG. 9)
[0021]
[Problems to be solved by the invention]
However, with the increase in the degree of integration of semiconductor devices, gate insulating films are becoming thinner year by year. As a result, the withstand voltage of the gate insulating film is becoming smaller than the junction withstand voltage of the protection diode. Therefore, as the thickness of the gate insulating film is reduced, a charging current leaking to the gate electrode without flowing through the protection diode is increasing.
[0022]
From this, the effect of suppressing the plasma charging damage by the protection diode becomes smaller as the gate insulating film becomes thinner, and despite the provision of the protection diode, the device characteristics due to the plasma charging damage are reduced. Has deteriorated.
[0023]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which can solve the above problem and can suppress plasma charging damage in a plasma process, and a method of manufacturing the same.
[0024]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate, a gate insulating film provided on the semiconductor substrate, a gate electrode provided on the gate insulating film, and a gate insulating film. A semiconductor device having an insulating layer covering the gate electrode, and a wiring provided on the insulating layer, wherein the wiring is a gate electrode wiring electrically connected to the gate electrode, and a dummy wiring Wherein the dummy wiring is electrically connected to an active region formed in the semiconductor substrate.
[0025]
According to the semiconductor device of the present invention, the dummy wiring is electrically connected to the active region formed on the silicon substrate. Therefore, the charging current due to the plasma flows not to the gate electrode wiring but to the dummy wiring. Further, the dummy wiring is electrically connected to the active region instead of the protection diode disclosed in Patent Document 1 in the related art. Therefore, according to the semiconductor device of the present invention, it is possible to suppress the charging current from leaking to the gate electrode wiring even if the thickness of the gate insulating film is further reduced.
[0026]
In the semiconductor device according to the present invention, it is preferable that the active region to which the dummy wiring is connected is an active region that does not function as any of a source region and a drain region. In this case, an active region functioning as a source region or a drain region is formed in the semiconductor substrate, and the wiring further includes a wiring electrically connected to the active region functioning as the source or drain region. Preferably.
[0027]
Further, in the semiconductor device according to the present invention, the wiring further has a second dummy wiring, and the second dummy wiring is formed at a position adjacent to the dummy wiring. It is preferable that the entire periphery of the dummy wiring is insulated by the insulating layer. In this case, the dummy wiring is arranged at a position adjacent to the gate electrode wiring, the second dummy wiring is composed of a plurality of wirings, and the plurality of wirings constituting the second dummy wiring are: It is preferable that the dummy wiring is arranged so as to surround the dummy wiring on a side not adjacent to the gate electrode wiring.
[0028]
Further, in the semiconductor device according to the present invention, the wiring is formed by a damascene method, and is embedded in the insulating layer, and the active region to which the dummy wiring is connected has a gate insulating property. It is preferable that the semiconductor device is provided at a position adjacent to a region of the semiconductor substrate on which a film is provided, with an element isolation therebetween.
[0029]
Further, it is preferable that the gate electrode wiring, the dummy wiring, and the second dummy wiring are formed of the same metal material, and examples of the metal material include a metal material containing copper.
[0030]
Next, in order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes: (a) forming at least a stacked body of a gate insulating film and a gate electrode and an active region on a semiconductor substrate; (B) forming a first insulating layer covering the stacked body and the active region on the semiconductor substrate; and (c) electrically connecting the first insulating layer to the gate electrode. Simultaneously providing a gate electrode wiring and a dummy wiring electrically connected to the active region; and (d) forming a second insulating layer on the first insulating layer by a plasma process. And a step of performing
[0031]
According to the method for manufacturing a semiconductor device according to the present invention, the second insulating layer is formed while the dummy wiring is electrically connected to the active region formed on the silicon substrate. For this reason, the charging current generated when the second insulating layer is formed by the plasma flows to the dummy wiring instead of the gate electrode wiring. Further, the dummy wiring is electrically connected to the active region instead of the protection diode disclosed in Patent Document 1 in the related art. Therefore, according to the method of manufacturing a semiconductor device according to the present invention, even if the thickness of the gate insulating film is further reduced, it is possible to suppress the charging current from leaking to the gate electrode wiring.
[0032]
In the method of manufacturing a semiconductor device according to the present invention, in the step (d), while discharging the charging current from the plasma generated by the plasma process through the dummy wiring, the second insulating layer is removed. Preferably, it is formed. In the step (c), it is preferable that the gate electrode wiring and the dummy wiring are formed by a damascene method.
[0033]
In the method of manufacturing a semiconductor device according to the present invention, in the step (a), the active region functioning as a source region or a drain region and the active region functioning as neither the source region nor the drain region may be formed. It is preferable that, in the step (c), the dummy wiring is connected to an active region that does not function as any of the source region and the drain region. Further, it is preferable that the first insulating layer is a base interlayer insulating film for forming a multilayer wiring, and the second insulating layer is an interlayer insulating film for forming a multilayer wiring.
[0034]
Further, in the method of manufacturing a semiconductor device according to the present invention, in the step (c), the first insulating layer may insulate the gate electrode and the active region at a position adjacent to the dummy wiring. Preferably, the formed second dummy wiring is formed simultaneously with the gate electrode wiring. Further, it is preferable that the first insulating layer and the second insulating layer are a silicon oxide film or a silicon nitride film.
[0035]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
Hereinafter, a semiconductor device and a method of manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. First, the configuration of the semiconductor device according to the first embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view partially showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a cross-sectional view taken along a normal direction of a semiconductor substrate forming the semiconductor device. FIG. 1B is a cross-sectional view taken along a cutting line AA ′ shown in FIG.
[0036]
As shown in FIG. 1A, the semiconductor device according to the first embodiment includes an n-type silicon substrate 1 similarly to the semiconductor device shown in FIG. A plurality of element isolations 2 are formed at predetermined intervals so as to be exposed on the silicon substrate 1.
[0037]
In addition, between the element isolation 2 on the silicon substrate 1, a p-well (p well) 3 formed inside the silicon substrate 1 and a gate insulating film 6, as in the semiconductor device shown in FIG. , A gate electrode 7 formed of n + polysilicon, and a source (n +) region 4a and a drain (n +) region 4b provided in a surface layer portion of the silicon substrate 1 to form an n-channel MOS transistor.
[0038]
The gate insulating film 6 and the gate electrode 7 are formed so as to be aligned with each other, similarly to the semiconductor device shown in FIG. 6 in the related art. 8 are formed. Reference numeral 5 denotes an n + region, which is an active region functioning as a source region or a drain region of another transistor.
[0039]
Further, on the silicon substrate 1, a base interlayer insulating film 10 and an interlayer insulating film 12 for realizing a multilayer wiring are sequentially stacked as in the semiconductor device shown in FIG. Further, wirings 11 a to 11 c are formed in the base interlayer insulating film 10. The underlying interlayer insulating film 10 and the interlayer insulating film 12 are a silicon oxide film or a silicon nitride film.
[0040]
The wirings 11 a to 11 c are copper wirings (thickness: 500 nm) formed simultaneously by the damascene method, and are embedded in the underlying interlayer insulating film 10. The wiring 11a is a gate electrode connecting wiring connected to the gate electrode 7 via the W plug 9c. The wiring 11c is a source / drain connection wiring connected to the n + region 5 via the W plug 9a. Also in the first embodiment, as shown in FIG. 1B, the wirings 11a and 11c are formed in a strip shape.
[0041]
The wiring 11b is a dummy wiring for ensuring flatness in a CMP process performed by a damascene method, and does not contribute to the function of the semiconductor device. Further, as shown in FIG. 1B, the wiring 11b is composed of a plurality of pieces and is formed in a square shape.
[0042]
As described above, the semiconductor device according to the first embodiment has the same configuration as the semiconductor device shown in FIG. 6 in the related art, but differs from the conventional semiconductor device as described below. Have a point.
[0043]
In the first embodiment, unlike the semiconductor device shown in FIG. 6 in the related art, an active region (n + region) 13 that does not function as any of a source region and a drain region is formed of silicon provided with a gate insulating film 6. An element isolation 2 is provided at a position adjacent to the region of the substrate 1. The wiring 11b, which is a dummy wiring, is not in an electrically floating state and is connected to the active region 13 via the W plug 9b.
[0044]
Note that the “active region that does not function as any of the source region and the drain region” in this specification is formed in the same manner as the source region and the drain region, but has no gate electrode adjacent thereto. A region that does not function as either a source region or a drain region.
[0045]
Also, in the first embodiment, W plugs 9a to 9c are filled with tungsten in contact holes formed in base interlayer insulating film 10, similarly to W plugs 29a and 29b shown in FIG. It is formed. Further, in the first embodiment, wiring and plugs (both not shown) for multilayer wiring are formed in the interlayer insulating film 12, and another plurality of interlayer insulating films are formed on the interlayer insulating film 12. A film can also be formed.
[0046]
Next, a method of manufacturing the semiconductor device according to the first embodiment and the operation of the dummy wiring will be described with reference to FIG. FIG. 2 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 2 shows a step of forming an interlayer insulating film constituting the semiconductor device shown in FIG. FIG. 2 conceptually shows a state in which occurrence of plasma charging damage is suppressed by the first embodiment.
[0047]
First, a gate insulating film 6 is formed on the silicon substrate 1 on which the element isolation 2 and the p well 3 are provided. Next, a gate electrode 7 is formed on the gate insulating film 6, and sidewalls 8 are formed on both side surfaces of the gate insulating film 6 and the gate electrode 7.
[0048]
Next, for example, As and P are ion-implanted to form an n + region 5, a source (n +) region 4a and a drain (n +) region 4b, and an active region 13. Thereafter, plasma is generated by a plasma CVD apparatus (not shown), and the underlying interlayer insulating film 10 is formed. At this time, since the wiring 11a connected to the gate electrode 7 has not been formed yet, no charge current due to plasma is generated.
[0049]
Next, in the underlying interlayer insulating film 10, a contact hole with the n + region 5 exposed on the bottom surface, a contact hole with the active region 13 exposed on the bottom surface, and a contact hole with the gate electrode 7 exposed on the bottom surface are formed. The inside is filled with tungsten to form W plugs 9a to 9c.
[0050]
After that, the wirings 11a to 11c are simultaneously formed using the damascene method. Specifically, grooves are formed in the underlying interlayer insulating film 10 so that the W plugs 9a to 9c are respectively exposed at the bottom surface, and a copper layer is formed so as to fill the grooves. Is removed.
[0051]
Next, as shown in FIG. 2, a plasma 14 is generated by a plasma CVD apparatus (not shown), and an interlayer insulating film 12 is formed. At this time, in the first embodiment, unlike the case of FIG. 7 shown in the prior art, the wiring 11b serving as a dummy wiring is electrically connected to the active region 13 formed in the silicon substrate 1 via the W plug 9b. It is connected. Therefore, the charging current at the time of film formation by the plasma 14 flows not to the wiring 11a connected to the gate electrode 7, but to the wiring 11b.
[0052]
In the first embodiment, the dummy wiring (wiring 11b) is electrically connected to the active region 13 instead of the protection diode disclosed in Patent Document 1 in the related art. Further, the dummy wiring (wiring 11b) is insulated from the gate electrode connecting wiring (wiring 11a). Therefore, even if the thickness of the gate insulating film is further reduced, the charging current flows to the wiring 11b which is a dummy wiring.
[0053]
As described above, according to the first embodiment, even when the withstand voltage of the gate insulating film is reduced due to the thinning, deterioration of the device characteristics due to the destruction of the gate insulating film 6 can be suppressed.
[0054]
In the first embodiment, not all of the formed dummy wires may be connected to the active region 13, and only some of the dummy wires may be connected to the active region 13. In the first embodiment, the connection ratio of the formed dummy wiring to the active region 13 can be appropriately set according to the process conditions such as the thickness of the gate insulating film 6 and the like.
[0055]
(Embodiment 2)
Next, a semiconductor device and a method of manufacturing the semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. First, the configuration of the semiconductor device according to the second embodiment will be described with reference to FIG. FIG. 3 is a cross-sectional view partially showing a configuration of a semiconductor device according to a second embodiment of the present invention. FIG. 3A is a cross-sectional view taken along a normal direction of a semiconductor substrate forming the semiconductor device. FIG. 3B is a cross-sectional view taken along a cutting line BB ′ shown in FIG. In FIGS. 3 and 4, portions denoted by the same reference numerals as those shown in FIG. 1 are the same as those shown in FIG.
[0056]
As shown in FIG. 3, the second embodiment differs from the first embodiment in that a wiring 11d serving as a second dummy wiring is provided. The wiring 11d is also formed simultaneously with the wiring 11a and the wiring 11b by the damascene method, but the entire periphery of the wiring 11d is insulated by the underlying interlayer insulating film 10 and the interlayer insulating film 12, and the wiring 11d is electrically connected. In a floating state.
[0057]
Next, a method of manufacturing the semiconductor device according to the second embodiment and the operation of the dummy wiring will be described with reference to FIG. FIG. 4 is a sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention. FIG. 4 shows a step of forming an interlayer insulating film constituting the semiconductor device shown in FIG. FIG. 4 conceptually shows how plasma charging damage is suppressed from occurring according to the second embodiment.
[0058]
First, as in the first embodiment, a gate insulating film 6 is formed on a silicon substrate 1 provided with an element isolation 2 and a p-well 3, and further, a gate electrode 7 and a sidewall 8 are formed.
[0059]
Next, as in the first embodiment, a source (n +) region 4a and a drain (n +) region 4b are formed by ion implantation, and an active region 13 is formed. Thereafter, plasma is generated by a plasma CVD apparatus (not shown), and the underlying interlayer insulating film 10 is formed. After that, similarly to the first embodiment, after forming W plugs 9b and 9c in the underlying interlayer insulating film 10, the wirings 11a, 11b and 11d are simultaneously formed by using the damascene method.
[0060]
Next, as shown in FIG. 4, a plasma 14 is generated by a plasma CVD apparatus (not shown), and an interlayer insulating film 12 is formed. At this time, also in the second embodiment, as in the case of FIG. 2 shown in the first embodiment, the charging current at the time of film formation by the plasma 14 is not the wiring 11a connected to the gate electrode 7, but the charging current. It flows to the wiring 11b.
[0061]
However, in the second embodiment, unlike the first embodiment, the wiring 11d is provided adjacent to the wiring connected to the active region 13. For this reason, the wiring 11b has a characteristic that charges are more easily collected than in the case described in the first embodiment.
[0062]
That is, according to the second embodiment, the charging current from the plasma 14 can be selectively passed to the wiring 11b by arranging the wiring 11d in an electrically floating state adjacent to the wiring 11b. As a result, more charging current flows through the wiring 11b than in the case of the first embodiment. Therefore, according to the second embodiment, the effect of suppressing the deterioration of the device characteristics can be further enhanced as compared with the first embodiment.
[0063]
In the second embodiment, as shown in FIG. 3B, the wiring 11d serving as the second dummy wiring is configured by a plurality of wirings. Further, the plurality of wirings 11d are formed to be adjacent to the wiring (dummy wiring) 11b connected to the active region 13, and on the side of the wiring 11b which is not adjacent to the wiring 11a (wiring for the gate electrode), It is arranged so as to surround the wiring 11b. Therefore, the charging current can be efficiently concentrated on the wiring 11b.
[0064]
In the second embodiment, the layout of the wiring 11d as the second dummy wiring is not limited to the layout shown in FIG. The layout of the wiring 11d may be appropriately set according to the process characteristics in the CMP process, the dummy wiring rule, and the like.
[0065]
Here, the effects of the semiconductor device and the method of manufacturing the semiconductor device according to the first and second embodiments will be described with reference to FIG. FIG. 5 is a graph illustrating the life of the semiconductor device according to the first and second embodiments.
[0066]
In FIG. 5, the horizontal axis represents the life of the semiconductor device at the time of a constant voltage TDDB (Time Dependent Breakdown) test, which is an index of the reliability life, and the vertical axis represents the cumulative failure rate assuming a Weibull distribution. ing. "Conventional semiconductor device" in FIG. 5 indicates the semiconductor device shown in FIG. In each of the conventional semiconductor device and the semiconductor devices of Embodiments 1 and 2, the thickness of the gate insulating film is 2.2 nm.
[0067]
As can be seen from FIG. 5, when the cumulative failure rate is the same, the time until destruction of the conventional semiconductor device (“O” in the figure) is equal to the time required for the semiconductor device according to the first embodiment of the present invention (“□” in the figure). ) And the time until destruction of the semiconductor device according to the second embodiment (“●” in the figure) is always shorter. This means that the semiconductor device according to the first embodiment of the present invention (“□” in the drawing) and the semiconductor device according to the second embodiment (“●” in the drawing) are different from the conventional semiconductor device (“○” in the drawing). ) Indicates that the life is longer. That is, according to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, it is possible to suppress the deterioration of the device characteristics.
[0068]
Note that the semiconductor device and the method of manufacturing the semiconductor device of the present invention are not limited to the first and second embodiments. For example, in the first and second embodiments, the shape of the dummy wiring is rectangular in order to enhance the effect in the CMP process and to facilitate the rule, but in the present invention, the shape of the dummy wiring is not particularly limited. Not something.
[0069]
In the present invention, it is sufficient that the dummy wiring is electrically connected to an active region that does not function as any of the source region and the drain region. The type of the active region to which the dummy wiring is connected is not limited to n-type, but may be p-type. Further, in the present invention, the semiconductor substrate may be a p-type silicon substrate or a substrate other than a silicon substrate.
[0070]
In the first and second embodiments, the W plug is used for the connection between the dummy wiring and the active region and the connection between the gate electrode connection wiring and the gate electrode, but the Cu plug is used. You can also. Further, instead of providing such a plug, a dual damascene structure may be employed.
[0071]
Further, in the first and second embodiments, the wiring is a Cu wiring, but the present invention is not limited to this. The wiring may be any one formed of a metal material, and may be an Al wiring. . In the case of an Al wiring, the wiring may be formed by etching. In this case, the dummy wiring may be an alignment wiring for confirming alignment in a lithography method performed before performing etching.
[0072]
【The invention's effect】
As described above, according to the semiconductor device and the method of manufacturing the semiconductor device according to the present invention, by optimizing the structure of the dummy wiring disposed around the wiring, the charge in forming the interlayer insulating film by the plasma process can be improved. Wing damage can be suppressed. As a result, a highly reliable semiconductor device and a method for manufacturing the same can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view partially showing a configuration of a semiconductor device according to a first embodiment of the present invention, and FIG. 1A is a cross-section taken along a normal direction of a semiconductor substrate forming the semiconductor device; FIG. 1B is a cross-sectional view taken along a cutting line AA ′ shown in FIG.
FIG. 2 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a cross-sectional view partially showing a configuration of a semiconductor device according to a second embodiment of the present invention; FIG. 3A is a cross-sectional view taken along a normal direction of a semiconductor substrate forming the semiconductor device; FIG. 3B is a cross-sectional view taken along a cutting line BB ′ shown in FIG.
FIG. 4 is a sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;
FIG. 5 is a graph showing the life of the semiconductor device according to the first and second embodiments.
6A and 6B are cross-sectional views partially showing a configuration of a conventional semiconductor device. FIG. 6A is a cross-sectional view taken along a normal direction of a semiconductor substrate forming the semiconductor device, and FIG. FIG. 7 is a cross-sectional view taken along a cutting line CC ′ shown in FIG.
7 is a cross-sectional view showing a step of forming an interlayer insulating film in the conventional semiconductor device shown in FIG. 6, conceptually showing the occurrence of plasma charging damage.
[Explanation of symbols]
1 n-type silicon substrate
2 Element separation
3 p-well
4a Source (n +) area
4b Drain (n +) region
5 n + area
6 Gate insulating film
7 Gate electrode
8 Side wall
9a-9c W plug
10 Underlayer insulating film
11a Wiring (Gate electrode connection wiring)
11b Wiring (dummy wiring)
11c wiring (wiring for source / drain connection)
11d wiring (second dummy wiring)
12 interlayer insulating film
13 Active area (n + area)

Claims (15)

A semiconductor substrate, a gate insulating film provided on the semiconductor substrate, a gate electrode provided on the gate insulating film, an insulating layer covering the gate insulating film and the gate electrode, and A semiconductor device having provided wiring,
The wiring has a wiring for a gate electrode electrically connected to the gate electrode, and a dummy wiring,
The semiconductor device according to claim 1, wherein the dummy wiring is electrically connected to an active region formed on the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the active region to which the dummy wiring is connected is an active region that does not function as any of a source region and a drain region. The wiring further includes a second dummy wiring;
2. The semiconductor device according to claim 1, wherein the second dummy wiring is formed at a position adjacent to the dummy wiring, and the entire periphery of the second dummy wiring is insulated by the insulating layer. 3. The dummy wiring is arranged at a position adjacent to the gate electrode wiring,
The second dummy wiring includes a plurality of wirings, and the plurality of wirings forming the second dummy wiring surround the dummy wiring on a side of the dummy wiring not adjacent to the gate electrode wiring. 4. The semiconductor device according to claim 3, wherein the semiconductor device is arranged as follows. The wiring is formed by a damascene method, and is embedded in the insulating layer;
The device according to claim 1, wherein the active region to which the dummy wiring is connected is provided at a position adjacent to a region of the semiconductor substrate on which the gate insulating film is provided, with an element isolation therebetween. Semiconductor device. An active region functioning as a source region or a drain region is formed in the semiconductor substrate,
The semiconductor device according to claim 2, wherein the wiring further includes a wiring electrically connected to an active region functioning as the source region or the drain region. 5. The semiconductor device according to claim 3, wherein said gate electrode wiring, said dummy wiring, and said second dummy wiring are formed of the same metal material. The semiconductor device according to claim 7, wherein the metal material is a metal material containing copper. (A) forming at least a stacked body of a gate insulating film and a gate electrode and an active region on a semiconductor substrate;
(B) forming a first insulating layer covering the stacked body and the active region on the semiconductor substrate;
(C) simultaneously providing, on the first insulating layer, a gate electrode wiring electrically connected to the gate electrode and a dummy wiring electrically connected to the active region;
(D) forming a second insulating layer on the first insulating layer by a plasma process. 10. The method of manufacturing a semiconductor device according to claim 9, wherein, in the step (d), the second insulating layer is formed while discharging a charging current from plasma generated by the plasma process through the dummy wiring. 10. The method of manufacturing a semiconductor device according to claim 9, wherein in the step (c), the gate electrode wiring and the dummy wiring are formed by a damascene method. In the step (a), an active region functioning as a source region or a drain region and an active region not functioning as any of the source region and the drain region are formed;
10. The method of manufacturing a semiconductor device according to claim 9, wherein in the step (c), the dummy wiring is connected to an active region that does not function as any of the source region and the drain region. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the first insulating layer is a base interlayer insulating film for forming a multilayer wiring, and the second insulating layer is an interlayer insulating film for forming a multilayer wiring. . In the step (c), a second dummy wiring insulated from the gate electrode and the active region by the first insulating layer is provided at a position adjacent to the dummy wiring with the gate electrode wiring. The method for manufacturing a semiconductor device according to claim 9, wherein the semiconductor device is formed simultaneously. The method of manufacturing a semiconductor device according to claim 9, wherein the first insulating layer and the second insulating layer are a silicon oxide film or a silicon nitride film.

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