471125 A7 B7 6l90t\vff.d〇c/008 五、發明說明（ί) (請先閱讀背面之注音心事項再填寫本頁) 本發明是有關於一種積體電路中多重內連線 (Multilevel Interconnects)的製造方法，且特別是有關於 一種雙重金屬鑲嵌（Dual Damascene)的製造方法。 傳統的內連線作法是在用以隔離金屬層的絕緣層上’ 例如氧化矽層，沈積一層金屬層後，再將金屬層定義出預 .定的導線圖案，其中導線層之間有一垂直連接窗口。然後 於窗口中塡入與導電層相同材質或不同材質的金屬，用以 完成導線層的垂直連接。値得重視的是，隨著積體電路中 所需導線層數目的增加，兩層以上的金屬層設計，便逐漸 的成爲許多積體電路所必需採用的方式。在金屬層之間常 以內金屬介電層（Inter-Metal Dielectrics ; IMD)加以隔 離，其中用來連接上下兩層金屬層的導線，在半導體工業 上，稱之爲介層窗（Via)。 習知製造介層窗和內連線的方法有兩種，其中一種是 介層窗和內連線分兩步驟完成，即先在金屬層上方形成介 電層，接著在介電層上方定義光阻（Photoresist)層，然 後利用蝕刻技術完成介層窗，並利用沈積法在此介層窗沈 積導電材料以完成介層窗的製作，之後沈積金屬層，並定 義金屬層，最後再沈積內金屬介電層。 經濟部智慧財產局員工消費合作社印製 另一種是雙重金屬鑲嵌的技術，是一種介層窗和內連 線同時形成的技術。其作法係在基底上先形成一層絕緣 .層，並將其平坦化後，再依照所需之金屬導線的圖案以及 介層窗的位置，蝕刻絕緣層，以形成溝渠以及一介層開口。 然後，再於基底上沈積一層金屬層，使其塡滿溝渠與介層 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 471125 A7 B7 6190t\vff.doc/008 五、發明說明（V) 窗開口，以同時形成金屬導線與介層窗。最後，再以化學 機械硏磨法（Chemical-Mechanical Polishing，CMP)將元 件的表面平坦化，即完成雙重金屬鑲嵌的製作。 (請先閱讀背面之注音心事項再填寫本頁} ^-----r---訂---------線 由於採用雙重金屬鑲嵌的方式’可以避免典型先形成 介層窗再形成金屬導線的方法在微影製程中所面臨疊對誤 差（Overlay Error)與製程偏差（Process Bias)的問題， 而使元件的可靠度增加，並且使製程能力提昇，因此，在 元件高度積集化之後，雙重金屬鑲嵌已逐漸成爲半導體工 業所採用的一種技術。 第1A圖至第1E圖繪示一種習知自動對準（Self、 Aligned)雙重金屬鑲嵌結構的製造流程剖面圖。首先，請 參照第1A圖，在已形成有第一層金屬層102的基底1〇〇 上形成一層介電層l〇4a，介電層104a的厚度與所需之介 層窗的厚度相當。接著，再於其之上覆蓋一層氮化矽蝕刻 終止層105。 經濟部智慧財產局員工消費合作社印製 然後，請參照第1B圖，在氮化矽蝕刻終止層105上 形成一層具有開口圖案的光阻層110，接著，再以光阻層 爲蝕刻罩幕，進行蝕刻，以在氮化矽蝕刻終止層1〇5 中形成開口圖案108，而此開口 1〇8即爲預定形成之介層 窗所在的位置。 其後，請參照第1C圖，在基底100上依序形成第二 層介電層104b與抗反射層1〇6。其中，介電層l〇4b的厚 度與預定形成之雙重金屬鑲嵌結構中第二層金屬餍（金屬 線）所需之厚度相同。471125 A7 B7 6l90t \ vff.d〇c / 008 V. Description of the Invention (ί) (Please read the phonetic notes on the back before filling out this page) The invention relates to a multilevel interconnect in a integrated circuit (Multilevel Interconnects ), And more particularly, to a method for manufacturing a dual damascene. The traditional method of interconnecting wires is to use an insulating layer to isolate the metal layer, such as a silicon oxide layer. After depositing a metal layer, the metal layer is then used to define a predetermined wire pattern, in which there is a vertical connection between the wire layers. window. Then insert a metal of the same material or a different material from the conductive layer into the window to complete the vertical connection of the wire layer. It is important to note that with the increase in the number of conductor layers required in integrated circuits, the design of two or more metal layers has gradually become a necessary method for many integrated circuits. Metal layers are often separated by inter-metal dielectric layers (IMD). The wires used to connect the upper and lower metal layers are called vias in the semiconductor industry. There are two known methods for manufacturing dielectric windows and interconnects. One of them is to complete the dielectric window and interconnect in two steps. First, a dielectric layer is formed above the metal layer, and then the light is defined above the dielectric layer. Resist (Photoresist) layer, and then use an etching technique to complete the interstitial window, and use a deposition method to deposit conductive materials on this interstitial window to complete the fabrication of the interstitial window, then deposit a metal layer, define the metal layer, and finally deposit the inner metal Dielectric layer. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Another technique is double metal inlay. It is a technique in which interlayer windows and interconnects are formed simultaneously. The method is to form an insulating layer on the substrate and flatten it, and then etch the insulating layer according to the required pattern of the metal wire and the position of the interposer window to form a trench and an interposer opening. Then, a metal layer is deposited on the substrate to make it full of trenches and interlayers. The paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 471125 A7 B7 6190t \ vff.doc / 008 V. DESCRIPTION OF THE INVENTION (V) A window opening to form a metal wire and a via window at the same time. Finally, the surface of the element is planarized by chemical-mechanical polishing (CMP) to complete the fabrication of the double metal inlay. (Please read the phonetic notes on the back before filling out this page) ^ ----- r --- Order --------- The line is double-damascene 'to avoid the typical formation of interlayer The method of re-forming the metal wires in the window faces the problems of overlay error and process bias in the lithography process, which increases the reliability of the component and improves the process capability. Therefore, at the height of the component, After accumulation, double metal damascene has gradually become a technology used in the semiconductor industry. Figures 1A to 1E show cross-sectional views of the manufacturing process of a conventional self-aligned (Self, Aligned) double metal damascene structure. First, Referring to FIG. 1A, a dielectric layer 104a is formed on the substrate 100 on which the first metal layer 102 has been formed, and the thickness of the dielectric layer 104a is equivalent to the thickness of the required dielectric window. Next Then, it is covered with a layer of silicon nitride etching stop layer 105. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. Then, please refer to FIG. 1B to form a layer of light with an opening pattern on the silicon nitride etching stop layer 105. Resistance layer 110 Then, the photoresist layer is used as an etching mask, and etching is performed to form an opening pattern 108 in the silicon nitride etching stop layer 105, and the opening 108 is a position where a via window is to be formed. Thereafter, referring to FIG. 1C, a second dielectric layer 104b and an anti-reflection layer 106 are sequentially formed on the substrate 100. Among them, the thickness of the dielectric layer 104b and the planned double metal damascene structure The second layer of metal rhenium (metal wire) requires the same thickness.
本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） 471125 A7 B7 6 190twff.doc/008 五、發明說明) - 接著，請參照第1D圖，在抗反射層106上形成一層 具有開口圖案的光阻層112,並以光阻層112爲蝕刻罩幕， 蝕刻介電層l〇4b，以形成溝渠開口 114a。其後，再以氮 化矽蝕刻終止層1〇5爲蝕刻終點，蝕刻介電層104a，以形 成介層窗開口 U4b，裸露出第一層金屬層102，使溝渠開 口 114a與介層窗開口 114b共同形成雙重金屬鑲嵌開口 114。 之後，請參照第1E圖，移除光阻層112，然後，在 ’基底1〇〇上覆蓋一層導體材料，使其塡滿雙重金屬鑲嵌開 口 114,並進行平坦化，以形成雙重金屬鑲嵌結構120。 其中，典型的導體材料例如爲具有鈦/氮化鈦作爲黏著層 的金屬銅。 在上述的方法中，蝕刻介電層104a以形成雙重金屬 鑲嵌開口 1H時，選擇對介電層l〇4a具有高蝕刻選擇率 的氮化矽作爲蝕刻終止層105之材質。然而，氮化矽不但 具有較氧化砂材質爲高的介電常數，易造成較高的寄生電 容，而且氮化矽亦容易產生較大的應力，而導致其與介電 層之間產生龜裂或剝離的現象，甚至在後續的高溫製程中 造成基底100的彎曲變形，使得後續的微影製程產生問題。 另一方面，在形成雙重金屬鑲嵌接觸窗時，需要進行 兩袭的光阻覆蓋步驟、兩次的微影蝕刻步驟及兩次的去除 光阻步驟，這也會使得製程的步驟較爲繁複。 此外，當預定形成之雙重金屬鑲嵌結構中介層窗的深 度車父深，或金屬線的線寬較窄時，因深寬比(Aspect Ratio) 5 ^•紙張尺i適用中國國家標準（CNS)A4規格（210 χ 297公釐） ------------ ‘於-----„----^---------辦 (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 471125 A7 B7 6190twff.doc/()08 五、發明說明（V ) •較大使蝕刻困難，介層窗與第一金屬層102的接觸面積將 因而減少，而使阻値增加。 有鑑於此，本發明的目的就是在提供一種雙重金屬鑲 嵌結構的製造方法，可以不需採用對氧化介電層具有高蝕 刻率的氮化矽作爲蝕刻終止層，避免採用氮化矽所衍生的 寄生電容與應力等問題，而有效控制雙重金屬鑲嵌結構中 金屬線與介層窗的深度。 因此，本發明提供^種製造雙重金屬鑲嵌的方法。依 .照本發明一較佳實施例，此方法是提供一個具有介電層的 基底，於介電層上連續形成兩層光阻層，各具有介層窗圖 案及溝渠圖案，並以此兩光阻層爲蝕刻罩幕，對介電層進 行蝕刻步驟，於介電層中形成雙重金屬鑲嵌接觸窗，再將 導體塡入雙重金屬鑲嵌接觸窗中，以形成雙重金屬鑲嵌。 由於光阻層的圖案可以藉由蝕刻步驟轉移至介電層中，因 此如果在光阻層曝光時，同時定義金屬插塞接觸窗以及內 連線的圖案，則也可以於介電層中同時形成金屬插塞以及 .內連線。 本發明中連續形成之兩層光阻層由一第一光阻層與一 直接形成於該第一光阻層上之第二光阻層所構成，該第一 光阻層具有介層窗圖案，而該第二光阻層具有溝渠圖案， 用作罩幕以便在介電層中蝕刻出雙重金屬鑲嵌接觸窗。 此外，具有雙重金屬鑲嵌結構之光阻層也可以使用於 具有蝕刻終止層的介電層結構，其方法是在基底上方依序 形成下層介電層、蝕刻終止層與上層介電層以形成介電 6 尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 一 " '' —------------k·----^— —訂·--------線' ί (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 471125 6190t\vff.doc/008 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（f) 層，並於上層介電層上形成具有雙重鑲嵌結構之光阻層。 •之後，進行蝕刻步驟，於介電層中形成雙重金屬鑲嵌接觸 窗，並且塡入導體以形成雙重金屬鑲嵌。 本發明的優點在於形成雙重金屬鑲嵌接觸窗時，可以 連續地進行塗佈光阻物質以及曝光的步驟，並且只進行一 次蝕刻及一次移除光阻之步驟，因此可以簡化製程。另外， 可以藉由控制光阻層與介電層之間的蝕刻選擇比以及光阻 層的厚度，不論介電層中是否具有蝕刻終止層，都可以形 成雙重金屬鑲嵌。 ‘ I爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1E圖繪示一種習知自動對準（Self_ Aligned)雙重金屬鑲嵌結構的製造流程剖面圖。 第2A圖至第2G圖繪示依照本發明一較佳實施例的 一種雙重金屬鑲嵌結構的製造流程剖面圖。 ‘ 圖式之標記說明： 100、200 :基底 102、202 :第一金屬層 104a、104b、204a、204b :介電層 105、 205 :蝕刻終止層 106、 206 ··抗反射層 108 :蝕刻終止層開口 • 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------- ^-----=---I -------^ (請先閱讀背面之注意事項再填寫本頁) 471125 A7 B7 6 I 90tvvff.doc/008 五、發明說明（ς) 110、210 :第一光阻層 210a :圖案化第一光阻層 112、212 :第二光阻層 212a:圖案化第二光阻層 114a :溝渠開口 114b :介層窗開口 114、214 :雙重金屬鑲嵌接觸窗 216 :襯層 218 :導電層 . 120、220 :雙重金屬鑲嵌 222 ··金屬插塞 224 :內連線 實施例 請參照第2A圖至第2G圖’其繪示依照本發明一較 佳實施例的一種雙重金屬鑲嵌結構的製造流程剖面圖。 請參照第2A圖，在已形成有第〜層金屬層202的基 底200上形成一層介電層204a，並將其平坦化，以使介電 .層204a的厚度與所需之介層窗的厚度相當。接著，再於 其之上覆蓋一層蝕刻終止層205，蝕刻終止層205之材質 包括氮化矽或氮氧化矽（SlxOyNz)，而氮氧化矽在光源爲 深紫外線（Deep UV)時又可作爲抗反射層。接著，在基 底200上依序形成第二曆介電層204b與抗反射層206。抗 反射層2〇6可視情況省略。其中，介電層204b的厚度與 預定形成之雙重金屬鑲嵌結構中第二層金屬層（金屬線） 8 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公g 1 · --------! ---- -----^----訂---------^線 (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 Λ7 471125 6 1 90twff.doc/〇 〇8 五、發明說明（7 ) 所需之厚度相同。典型的介電層204a與204b之材質包括 氧化矽或其他低介電係數之物質，如Sllk或C〇ral，形成 的方法例如爲化學氣相沈積法。而平坦化的方法例如爲化 學機械硏磨法。 在本發明之另一實施例中，g亥蝕刻終止層2 〇 5可以省 略，而直接形成一介電層，其厚度與雙重金屬鑲嵌結構所 需之厚度相同。 在已形成有介電層204a、204b的基底200上方形成第 一光阻層210。其中，第一光阻層210爲一負光阻層，負 光阻比起正光阻具有更良好之附著力，特別是針對一些低 介電係數之物質。於形成第一光阻層210之後再進行軟烤 (Soft Bake)的步驟。軟烤的作用在於去除光阻中的溶劑、 增加光阻的附著力以及增加後續步驟中所使用之顯影劑對 曝光與未曝光之光阻的選擇性等等。 請參照第2B圖，進行曝光以定義介層窗，再進行曝 光後烘烤（Post Exposure Bake)之步驟，並顯影使第一光阻 層210圖案化爲第一光阻層210a。顯影後，只有照光處倉 光阻層才會餘留。由於負光阻對於介電層之蝕刻選擇率比 起正光阻對於介電層之蝕刻選擇率要高，因此負光阻層可 以較薄，而這對增加顯影之解析度（Resolution)及改善顯影 製程裕度（Process Window)是有幫助的。 請參照第2C圖，於第一光阻層21〇a上形成第二光阻 層212，並進行軟烤的步驟。再參照第2〇圖，進行曝光、 曝光後烘烤、顯影以定義溝渠，使部分的第二光阻層212 9 -------------- X衣-----：----訂---------^ (請先閱讀背面之注音？事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 ^•張尺度適用中國國家標準（CNS)A4 X 297公釐） 經濟部智慧財產局員工消費合作社印製 471125 A7 _ 6190twff.doc/008_^_ 一 " " '--------- 五、發明說明（^ ) 變成第二光阻層212a。其中第二光阻層212所传 ^ t J场一正光阻 層、，一負光阻層或_ ^層含矽光阻層。若第：：腠 ‘臀先阻層212 .爲負光阻，則不需使用塡補間隙(Gap FUUng)材料來塡補第 一層光阻之圖案，反之，若第二層光阻層212 m正光阻％ 則一般情形下會使用塡補間隙材料來塡補第 案間隙。 ^ 請參照第2E及第2F圖，移除部分的介電層，以形成 雙重金屬鑲嵌結構之開口 214。 參照第2E圖，根據第一光阻層210對介電層之f虫刻 選擇率，利用控制第一光阻層210之厚度，進行非等向个生 •蝕刻，移除部分的介電層204b，達到如圖所示之触刻結果。 可以利用蝕刻終止層205爲触刻終點，以增加蝕刻製程格： 度；或如本發明另一實施例中，沒有形成蝕刻終止層，而 只是以精確控制（Fine Tune)第一光阻層之厚度來控制軸刻 結果。 參照第2F圖，根據第二光阻層212對介電層之蝕刻 選擇率，利用控制第二光阻層212之厚度，繼續進行 向性蝕刻達到如圖所示之蝕刻結果，以將雙重金屬鑲嵌結 構之圖案轉移至介電層。同樣地，可以利用蝕刻終止層2〇5 爲蝕刻終點，以增加蝕刻製程裕度；或如本發明另一鸷施 例中，沒有形成蝕刻終止層，而只是以第二光阻層212對 介電層之蝕刻選擇率來控制蝕刻結果。 第2E，2F圖中所述之蝕刻步驟，實際上爲一單一蝕刻 步驟，只不過是依照不同光阻層之蝕刻選擇率，分爲兩(1 皆 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ;K-----r---訂---------綠 471125 6 1 90tvvff.doc/008 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明) 段選用不同之蝕刻條件（不同之氣體或比例）來蝕刻介電 層。但若是第一與第二光阻層爲同一材質，則此步驟即無 須更換蝕刻條件。 請參照第2G圖，移除光阻，沿著於介電層2(M的表 面形成一層襯層(Liner Layer) 216，再形成一層導電層218 於襯層216上，並將其平坦化，以形成雙重金屬鑲嵌220、 金屬插塞222以及內連線224。其中，典型之導電層材料 爲金屬。 而由於本發明中光阻層的圖案可以藉由蝕刻步驟轉移 至介邊層中，因此如果在光阻層曝光時，同時定義金屬插 塞接觸窗以及內連線的圖案，則可以於介電層中同時形成 金屬插塞222以及內連線224。 r本發明之特徵在於以一次蝕刻的方式將光阻層的圖形 轉移至介電層中。由於蝕刻的次數只有一次，因此可以簡 化製程。此外，藉由控制光阻層與介電層之間的蝕刻選擇 比，可以控制所形成之內連線在介電層中的深度。以及在 不論是否具有蝕刻終止層的情形下，都能以一次的蝕刻步 驟，在介電層中形成雙重金屬鑲嵌接觸窗。 由上述本發明較佳實施例可知，應用本發明具有下列 優點： (1) 形成雙重金屬鑲嵌接觸窗時，可以連續地進行塗 佈光阻物質以及曝光的步驟，並且只進行一次飽 刻及一次移除光阻之步驟，因此可以簡化製程。 (2) 可以藉由控制光阻層與介電層之間的蝕刻選擇比 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公愛） I-----------b----l·—!訂---------姨 (請先閱讀背面之注意事項再填寫本頁) 6 1 90t\vff.doc/008 471125 A7 ____B7___ 五、發明說明（ 以及光阻層的厚度，來掌握內連線的深度以及不 論介電層中是否具有蝕刻終止層，都可以形成雙 重金臑鑲嵌。 ’ （3)由於負光阻對於介電層之蝕刻選擇率比起正光阻 對於介電層之蝕刻選擇率要高，因此負光阻層可 以較薄，而這對增加顯影之解析度及改善顯影製 程裕度是有幫助的。而且在深寬比較大之情況下， 使用較薄之負光阻層對正光阻之殘殘留有改善。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）This paper size is in accordance with Chinese National Standard (CNS) A4 specification (21 × 297 mm) 471125 A7 B7 6 190twff.doc / 008 V. Description of the invention-Next, please refer to Figure 1D and form on the anti-reflection layer 106 A layer of photoresist layer 112 having an opening pattern, and using the photoresist layer 112 as an etching mask, the dielectric layer 104b is etched to form a trench opening 114a. After that, the silicon nitride etching stop layer 105 is used as an etching end point, and the dielectric layer 104a is etched to form a dielectric window opening U4b. The first metal layer 102 is exposed to expose the trench opening 114a and the dielectric window. 114b collectively form a double metal inlaid opening 114. After that, please refer to FIG. 1E, remove the photoresist layer 112, and then cover the substrate 100 with a layer of conductive material to fill the double metal damascene opening 114 and planarize it to form a double metal damascene structure. 120. Among them, a typical conductive material is, for example, metallic copper having titanium / titanium nitride as an adhesive layer. In the above method, when the dielectric layer 104a is etched to form the double metal damascene opening 1H, silicon nitride having a high etch selectivity to the dielectric layer 104a is selected as the material of the etch stop layer 105. However, silicon nitride not only has a higher dielectric constant than that of sand oxide materials, but also tends to cause higher parasitic capacitance. Moreover, silicon nitride is also prone to generate larger stress, which causes cracks between the silicon nitride layer and the dielectric layer. The phenomenon of peeling, or even the subsequent deformation of the substrate 100 in the subsequent high-temperature process, causes problems in the subsequent lithography process. On the other hand, when forming a double metal damascene contact window, two photoresist covering steps, two lithographic etching steps, and two photoresist removing steps are required, which also makes the process steps more complicated. In addition, when the depth of the interlayer window of the double metal mosaic structure that is planned to be formed is deep, or the line width of the metal wire is narrow, the aspect ratio 5 ^ • paper rule i applies the Chinese National Standard (CNS) A4 specification (210 χ 297 mm) ------------ 'Yu ----- „---- ^ --------- Do (please read the first Phonetic notation? Please fill in this page again.) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. 471125 A7 B7 6190twff.doc / () 08 V. Description of Invention (V) • Larger makes etching difficult. Therefore, the contact area will be reduced and the resistance will be increased. In view of this, the object of the present invention is to provide a method for manufacturing a dual metal damascene structure without using silicon nitride with a high etch rate for the oxide dielectric layer. As an etch stop layer, the problems of parasitic capacitance and stress derived from silicon nitride are avoided, and the depth of metal lines and interlayer windows in a dual metal damascene structure is effectively controlled. Therefore, the present invention provides a method for manufacturing a dual metal damascene. According to a preferred embodiment of the present invention, this method is to provide a A substrate with a dielectric layer is formed with two photoresistive layers continuously on the dielectric layer, each having a dielectric window pattern and a trench pattern, and using the two photoresistive layers as an etching mask to perform an etching step on the dielectric layer. A double metal damascene contact window is formed in the dielectric layer, and then a conductor is inserted into the double metal damascene contact window to form a double metal damascene. Since the pattern of the photoresist layer can be transferred to the dielectric layer by an etching step, if When the photoresist layer is exposed, while defining the pattern of the metal plug contact window and the interconnect, it is also possible to simultaneously form the metal plug and the interconnect in the dielectric layer. Two layers of photoresist formed in the present invention The layer is composed of a first photoresist layer and a second photoresist layer directly formed on the first photoresist layer. The first photoresist layer has a via window pattern and the second photoresist layer has a trench. Pattern, used as a mask to etch a double metal damascene contact window in the dielectric layer. In addition, a photoresist layer with a double metal damascene structure can also be used for a dielectric layer structure with an etch stop layer. Above Form a lower dielectric layer, an etch stop layer, and an upper dielectric layer in order to form a dielectric. The 6-dimension standard is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). &Quot; '' ------- ------ k · ---- ^ — —Order · -------- Line 'ί (Please read the phonetic on the back? Matters before filling out this page) Consumer Cooperatives of Intellectual Property Bureau, Ministry of Economic Affairs Printed 471125 6190t \ vff.doc / 008 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (f) layer, and a photoresist layer with a dual mosaic structure is formed on the upper dielectric layer. An etching step is performed to form a double damascene contact window in the dielectric layer, and a conductor is inserted to form a double damascene. The advantage of the present invention is that when forming a double metal inlaid contact window, the steps of coating the photoresist substance and exposing can be performed continuously, and only the steps of etching and removing the photoresist are performed once, so the manufacturing process can be simplified. In addition, by controlling the etching selection ratio between the photoresist layer and the dielectric layer and the thickness of the photoresist layer, a double metal damascene can be formed regardless of whether the dielectric layer has an etch stop layer. 'In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: Brief description of the drawings: 1A to 1E are cross-sectional views of a manufacturing process of a conventional self-aligned (Self-Aligned) dual metal damascene structure. FIG. 2A to FIG. 2G are cross-sectional views illustrating a manufacturing process of a dual metal damascene structure according to a preferred embodiment of the present invention. '' Symbols of the drawings: 100, 200: substrates 102, 202: first metal layers 104a, 104b, 204a, 204b: dielectric layers 105, 205: etch stop layers 106, 206. · anti-reflection layer 108: etch stop Layer opening • 7 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------- ^ ----- = --- I --- ---- ^ (Please read the precautions on the back before filling this page) 471125 A7 B7 6 I 90tvvff.doc / 008 V. Description of the invention (ς) 110, 210: First photoresist layer 210a: Patterned first Photoresist layers 112, 212: second photoresist layer 212a: patterned second photoresist layer 114a: trench opening 114b: interlayer window opening 114, 214: double metal inlaid contact window 216: liner layer 218: conductive layer. 120 , 220: double metal inlay 222 · · metal plug 224: Inner wiring embodiment, please refer to FIGS. 2A to 2G ′, which shows a cross-section of the manufacturing process of a double metal inlaid structure according to a preferred embodiment of the present invention Illustration. Referring to FIG. 2A, a dielectric layer 204a is formed on the substrate 200 on which the first to second metal layers 202 have been formed, and planarized to make the dielectric. The thickness of the layer 204a and the required dielectric layer window The thickness is comparable. Then, an etch stop layer 205 is covered thereon. The material of the etch stop layer 205 includes silicon nitride or silicon oxynitride (SlxOyNz), and the silicon oxynitride can also act as an anti-corrosive agent when the light source is deep ultraviolet (Deep UV). Reflective layer. Next, a second dielectric layer 204b and an anti-reflection layer 206 are sequentially formed on the substrate 200. The anti-reflection layer 206 may be omitted as appropriate. Among them, the thickness of the dielectric layer 204b and the second metal layer (metal wire) in the dual metal damascene structure that is to be formed 8 This paper size applies to the Chinese National Standard (CNS) A4 specification (21〇χ 297 g 1 ·- ------! ---- ----- ^ ---- Order --------- ^ line (Please read the phonetic on the back? Matters before filling out this page) Ministry of Economy Wisdom Printed by the Consumer Cooperative of the Property Bureau Λ7 471125 6 1 90twff.doc / 〇〇8 5. Description of the invention (7) The required thickness is the same. Typical materials of the dielectric layers 204a and 204b include silicon oxide or other low dielectric constant A substance, such as Sllk or Coral, is formed by, for example, a chemical vapor deposition method, and a planarization method is by, for example, a chemical mechanical honing method. In another embodiment of the present invention, the etch stop layer 2 is formed. 〇5 can be omitted, and a dielectric layer is directly formed with the same thickness as that required for the dual metal damascene structure. A first photoresist layer 210 is formed over the substrate 200 on which the dielectric layers 204a and 204b have been formed. Among them, The first photoresist layer 210 is a negative photoresist layer, and the negative photoresist has better adhesion than the positive photoresist, especially For some materials with low dielectric constant. After the first photoresist layer 210 is formed, a soft bake step is performed. The role of soft bake is to remove the solvent in the photoresist, increase the adhesion of the photoresist, and increase the subsequent The selectivity of the developer used in the step to the exposed and unexposed photoresist, etc. Please refer to Figure 2B, perform exposure to define the interlayer window, and then perform the step of Post Exposure Bake, and The development patterned the first photoresist layer 210 into the first photoresist layer 210a. After development, only the photoresist layer remains in the place where the light was irradiated. Since the selectivity of the negative photoresist to the dielectric layer is higher than that of the positive photoresist The electrical layer has a higher etching selectivity, so the negative photoresist layer can be thinner, which is helpful to increase the resolution of the development and improve the process window of the development. Please refer to Figure 2C. A second photoresist layer 212 is formed on the first photoresist layer 21a, and a soft baking step is performed. Referring to FIG. 20, exposure, post-exposure baking, and development are performed to define a trench, and part of the second Photoresist layer 212 9 ------------- -X Clothing -----: ---- Order --------- ^ (Please read the phonetic on the back? Matters before filling out this page} Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ • Zhang scale is applicable to Chinese National Standard (CNS) A4 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 471125 A7 _ 6190twff.doc / 008 _ ^ _ I " " '--------- 5. Description of the Invention (^) becomes the second photoresist layer 212a. The ^ t field transmitted by the second photoresist layer 212 is a positive photoresist layer, a negative photoresist layer, or a silicon-containing photoresist layer. If the first: 臀 'hip first resist layer 212. is negative photoresist, it is not necessary to use Gap FUUng material to complement the pattern of the first photoresist, otherwise, if the second photoresist layer 212 m positive photoresistance%, in general, a gap compensation material will be used to compensate the case gap. ^ Please refer to Figures 2E and 2F to remove a portion of the dielectric layer to form a double metal damascene opening 214. Referring to FIG. 2E, according to the f-etching selectivity of the first photoresist layer 210 to the dielectric layer, by controlling the thickness of the first photoresist layer 210, anisotropic growth and etching are performed, and a part of the dielectric layer is removed. 204b, achieving the engraving result as shown in the figure. The etch stop layer 205 can be used as the end point of the etch to increase the etching process grid; or as in another embodiment of the present invention, the etch stop layer is not formed, but only to precisely control (Fine Tune) the first photoresist layer. Thickness to control the results of the axial cut. Referring to FIG. 2F, according to the etching selectivity of the second photoresist layer 212 to the dielectric layer, the thickness of the second photoresist layer 212 is controlled, and the directional etching is continued to achieve the etching result shown in the figure, so as to convert the double metal The pattern of the mosaic structure is transferred to the dielectric layer. Similarly, the etch stop layer 205 can be used as the end point of the etch to increase the margin of the etch process; or as in another embodiment of the present invention, the etch stop layer is not formed, and only the second photoresist layer 212 is used to intervene. The etching selectivity of the electrical layer controls the etching result. The etching step described in Figures 2E and 2F is actually a single etching step, but it is divided into two according to the etching selectivity of different photoresist layers (1 All paper sizes are applicable to Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) (Please read the precautions on the back before filling out this page); K ----- r --- Order --------- Green471125 6 1 90tvvff.doc / 008 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention) Different etching conditions (different gases or proportions) are used to etch the dielectric layer. However, if the first and second photoresist layers are made of the same material, there is no need to change the etching conditions in this step. Referring to FIG. 2G, the photoresist is removed, a liner layer 216 is formed along the surface of the dielectric layer 2 (M, and then a conductive layer 218 is formed on the liner 216 and planarized. A double metal damascene 220, a metal plug 222, and an interconnect 224 are formed. Among them, a typical conductive layer material is metal. Since the photoresist layer pattern in the present invention can be transferred to the interlayer by an etching step, If the pattern of the metal plug contact window and the interconnect is defined at the same time when the photoresist layer is exposed, the metal plug 222 and the interconnect 224 can be formed in the dielectric layer at the same time. R The present invention is characterized by one etching The pattern of the photoresist layer is transferred to the dielectric layer. Since the number of etchings is only one, the process can be simplified. In addition, by controlling the etching selection ratio between the photoresist layer and the dielectric layer, the formation can be controlled The depth of the interconnects in the dielectric layer, and whether or not an etch stop layer is present, a double metal damascene contact window can be formed in the dielectric layer in a single etching step. It can be known from the preferred embodiments that the application of the present invention has the following advantages: (1) When forming a double metal inlaid contact window, the steps of applying a photoresist substance and exposing can be performed continuously, and only one photoetching and one photoresist removal are performed. The process can be simplified. (2) The etching selection between the photoresist layer and the dielectric layer can be controlled by controlling the Chinese paper standard (CNS) A4 (210 X 297). -------- b ---- l · —! Order --------- Aunt (Please read the notes on the back before filling this page) 6 1 90t \ vff.doc / 008 471125 A7 ____B7___ 5. Description of the invention (and the thickness of the photoresist layer, to grasp the depth of the interconnect and whether or not the dielectric layer has an etch stop layer, a double gold damascene can be formed. '(3) Because of the negative photoresist The etching selectivity of the dielectric layer is higher than that of the positive photoresist for the dielectric layer, so the negative photoresist layer can be thinner, which is helpful to increase the resolution of the development and improve the development process margin. . And in the case of larger depth and width, use a thinner negative photoresist layer pair. The photoresist residue has been improved. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art can make it without departing from the spirit and scope of the present invention. Various changes and retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs Paper size applies to China National Standard (CNS) A4 (210 X 297 mm)