451327 6590twf.doc/006 經濟部智慧財產局貝工消费合作社印製 五、發明說明（I) 本發明是有關於一種金屬內連線之製造方法，且特別 是有關於一種之雙重金屬鑲嵌（Dual Damascene)之製造方 法。 傳統的內連線作法是在用以隔離金屬層的絕緣層上， 例如氧化矽層，沈積一層金屬層後，再將金屬層定義出預 定的導線圖案，繼之使導線層之間形成一垂直連接窗口。 然後於窗口中塡入與導電層相同材質或不同材質的金屬， 用以完成導線層的垂直連接。値得重視的是，隨著積體電 路中所需導線層數目的增加，兩層以上的金屬層設計，便 逐漸的成爲許多積體電路所必需採用的方式。在金屬層之 間常以內金屬介電層（Inter-Metal Dielectrics ; IMD)加以 隔離，其中用來連接上下兩層金屬層的導線，在半導體工 業上，稱之爲介層窗（Via)。 習知製造介層窗和內連線的方法有兩種，其中一種是 介層窗和內連線分兩步驟完成，即先在金屬層上方形成介 電層，接著在介電層上方定義光阻（Photoresist)層，然 後利用蝕刻技術完成介層窗，並利用沈積法在此介層窗沈 積導電材料以完成介層窗的製做，之後沈積金屬層，並定 義金屬層，最後再沈積內金屬介電層β 另一種是雙重金屬鑲嵌的技術，是一種介層窗和內連 線同時形成的技術。其作法係在基底上先形成一層絕緣 層，並將其平坦化後，再依照所需之金屬導線的圖案以及 介層窗的位置，蝕刻絕緣層，以形成溝渠以及一介層開口。 然後，再於基底上沈積一層金屬層，使其塡滿溝渠與介層 3 本紙張尺度遶ϋ S國家摞準（CNSM4規格（210 297公釐） (請先《讀背面之注寫木頁) 丨)!裝 訂· - .線 4 51 3 27 65 90twf.doc/006 經濟部暫慧財產局貝工消费合作社印製 五、發明說明（l) 窗開口，以同時形成金屬導線與介層窗。最後，再以化學 機械硏磨法（Chemical-Mechanical Polishing，CMP)將元 件的表面平坦化，即完成雙重金屬鑲嵌的製作。 由於採用雙重金屬鑲嵌的方式，可以避免典型先形成 介層窗再形成金屬導線的方法在微影製程中所面臨疊對誤 差（Overlay Error)與製程偏差（Process Bias)的問題， 而使元件的可靠度增加，並且使製程能力提昇，因此，在 元件高度積集化之後，雙重金屬鑲嵌已逐漸成爲半導體工 業所採用的一種技術。 目前在超大型積體電路(VLSI)製程中，許多高積集度 (High Integration)的半導體元件，都具有兩層以上的內連線 金屬層，稱爲多重金屬內連線(multilevel interconnects)。當 積體電路的積集度持續增加，對於製造良率佳，以及可靠 度好的金屬內連線的困難度也會增加；而雙重金屬鑲嵌法 可以滿足製程中對高可靠度及高良率內連線的要求，所以 此法將成爲在深次微米(Sub-Quarter Micron)中內連線製造 方法的最佳選擇》然而，目前仍有許多關於雙重金屬鑲嵌 之問題尙在硏究之中，例如由於不平坦的光阻層表面而造 成介層窗的輪廓變形等，於下文說明之。 第1A圖到第1D圖爲習知的雙重金屬鑲嵌部份製程剖 面示意圖。請參照第1A圖，首先，提供一半導體基底1〇〇, 在基底100中已形成有一層金屬層102。接著，在金屬層 102和基底100上方依序形成第一介電層104、蝕刻終止層 106和第二介電層1〇8。然後，在第二介電層108上形成一 訂 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 451327 6590twf.doc/006 經濟部智慧財產局貝工消费合作社印黎 五、發明說明（>) 光阻層110，光阻層110具有預定形成溝渠之圖形。 接著，請參照第1B圖’以光阻層110(第1A圖)爲罩 幕，蝕刻終止層106爲終點，進行非等向性蝕刻，去除部 份第二介電層〗08，以在其中形成溝渠U2。接著，在基 底100上全面性形成一層光阻層114，覆蓋第二介電層108 並塡入溝渠112之中。由於溝渠112底部和第二介電層108 表面之間有相當大的高度差（介電層的厚度約3000-8000 埃）β因此形成的光阻層114表面的平坦度亦不佳。 之後，請參照第1C圖，圖案化光阻層114，在光阻層 中形成欲形成介層窗之開口 116。然而由於光阻層114的 表面並不平坦，故形成之開口 116之形狀亦會無法達到預 期的結果；特別是在對不準(Misalignment)時，導致後續以 光阻層114爲罩幕來進行第一介電層之蝕刻，會無法控制 形成介層窗的關鍵尺寸(CD)。 如第1D圖所示，當以圖案化光阻層1U爲罩幕來進 行非等向性之蝕刻時，因對不準而導致部分溝渠旁之第二 介電層108暴露出來，而使得溝渠之寬度加寬，但是介層 窗之寬度卻未達到預定之尺寸，故介層窗的關鍵尺寸比預 定的窄，如此容易導致接觸不完全，或甚至斷路。 但是，如果增加光阻層厚度來改進此情形時’又會對 微影的解析度造成負面之影響。 因此本發明的目的之一，就是在提供一種雙重金屬鑲 嵌的製程，可改進光阻表面之平坦度，並進而降低對於對 準精確度（Alignment Accuracy)之要求，提局製程裕度 5 !i!-裝 *! ί諝先閲讀背面之注f x本霣) 訂-451327 6590twf.doc / 006 Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (I) The present invention relates to a method for manufacturing a metal interconnect, and in particular to a dual metal inlay (Dual Damascene). The traditional method of interconnecting wires is to deposit a metal layer on an insulating layer used to isolate a metal layer, such as a silicon oxide layer, and then define the metal layer to define a predetermined wire pattern, and then form a vertical line between the wire layers. Connection window. A metal of the same material or a different material as the conductive layer is inserted into the window to complete the vertical connection of the wire layer. It is important to note that with the increase in the number of conductor layers required in integrated circuits, the design of two or more metal layers has gradually become a necessary method for many integrated circuits. Intermetallic layers (IMD) are often used to isolate metal layers. The wires used to connect the upper and lower metal layers are called vias in the semiconductor industry. There are two known methods for manufacturing dielectric windows and interconnects. One of them is to complete the dielectric window and interconnect in two steps. First, a dielectric layer is formed above the metal layer, and then the light is defined above the dielectric layer. Resist (Photoresist) layer, and then use an etching technique to complete the interstitial window, and use a deposition method to deposit conductive materials on this interstitial window to complete the fabrication of the interstitial window, then deposit a metal layer, define the metal layer, and finally deposit the Metal dielectric layer β The other is a double metal damascene technology, which is a technology in which a dielectric window and interconnects are formed simultaneously. The method is to first form an insulating layer on the substrate and planarize it, and then etch the insulating layer according to the required pattern of the metal wire and the position of the via window to form a trench and a via opening. Then, a metal layer is deposited on the substrate so that it covers the trenches and interlayers. This paper scales around the national standard (CNSM4 specification (210 297 mm)) (please first read the note on the back page)丨)! Binding ·-. Thread 4 51 3 27 65 90twf.doc / 006 Printed by the Pui Gong Consumer Cooperative of the Ministry of Economic Affairs of the Ministry of Economic Affairs. 5. Description of the invention (l) Window openings to form metal wires and interlayer windows at the same time. Finally, the surface of the element is planarized by chemical-mechanical polishing (CMP) to complete the fabrication of the double metal inlay. Due to the use of the double metal inlay method, the typical method of forming the interlayer window first and then forming the metal wires can avoid the problems of overlay error and process bias in the lithography process, and make the component's Reliability is increased and process capability is improved. Therefore, after the components are highly integrated, dual metal damascene has gradually become a technology used by the semiconductor industry. At present, in the process of very large scale integrated circuits (VLSI), many high integration semiconductor devices have two or more interconnect metal layers, which are called multilevel interconnects. When the integration degree of integrated circuits continues to increase, the difficulty of manufacturing metal interconnects with good yield and reliability will also increase; and the dual metal damascene method can meet the requirements of high reliability and high yield in the manufacturing process. The connection requirements, so this method will become the best choice for the production method of interconnects in Sub-Quarter Micron. However, there are still many questions about double metal inlays being studied, For example, the contour deformation of the via window caused by the uneven photoresist layer surface will be described below. Figures 1A to 1D are schematic cross-sectional views of a conventional double metal inlay process. Referring to FIG. 1A, first, a semiconductor substrate 100 is provided, and a metal layer 102 has been formed in the substrate 100. Next, a first dielectric layer 104, an etch stop layer 106, and a second dielectric layer 108 are sequentially formed over the metal layer 102 and the substrate 100. Then, a guideline is formed on the second dielectric layer 108. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 451327 6590twf.doc / 006 Intellectual Property Bureau, Ministry of Economic Affairs, Shellfish Consumer Cooperative, India Li V. Description of the Invention (>) The photoresist layer 110 has a pattern in which trenches are intended to be formed. Next, referring to FIG. 1B ′, using the photoresist layer 110 (FIG. 1A) as a mask and the etch stop layer 106 as an end point, perform anisotropic etching to remove a portion of the second dielectric layer. Form a trench U2. Next, a photoresist layer 114 is formed on the substrate 100, covering the second dielectric layer 108 and being inserted into the trench 112. Due to the considerable height difference between the bottom of the trench 112 and the surface of the second dielectric layer 108 (the thickness of the dielectric layer is about 3000-8000 Angstroms) β, the flatness of the surface of the photoresist layer 114 formed is also not good. After that, referring to FIG. 1C, the photoresist layer 114 is patterned to form an opening 116 in the photoresist layer where a via window is to be formed. However, because the surface of the photoresist layer 114 is not flat, the shape of the opening 116 may not reach the expected result; especially when the alignment is misaligned, the subsequent use of the photoresist layer 114 as a mask will be performed. The etching of the first dielectric layer cannot control the critical dimension (CD) of the dielectric window. As shown in FIG. 1D, when the patterned photoresist layer 1U is used as a mask to perform anisotropic etching, the second dielectric layer 108 next to a portion of the trench is exposed due to misalignment, which causes the trench. The width of the interstitial window is widened, but the width of the interstitial window does not reach the predetermined size. Therefore, the key dimension of the interstitial window is narrower than the predetermined size, so it is easy to cause incomplete contact or even break. However, if the thickness of the photoresist layer is increased to improve the situation, the resolution of the lithography will be adversely affected. Therefore, one of the objectives of the present invention is to provide a dual metal damascene process, which can improve the flatness of the photoresist surface, and further reduce the requirement for alignment accuracy, and provide a process margin of 5! I. !-装 *! Ί 谞 Read the note on the back fx 本 霣) Order-
/(V 本紙張尺度適用令两因家標準（CNS)A4規格（2J0 X 297公釐） 6590twf.doc/006 A7 經濟部智慧財產局貝工消费合作杜印製 五、發明說明（¥) (Window Process) ° 本發明提供一種雙重金屬鑲嵌的製程，溝渠形成後， 蝕刻介層窗前，利用聚合物(Polymer)形成一平坦層將基底 表面平坦化，之後再於平坦層的平坦表面上形成一層具有 平坦表面之光阻層，以避免因光阻表面不平坦而造成之問 題。 本發明提供一種雙重金屬鑲嵌製程，在半導體基底中 先形成有一導體層，在基底和導體層上形成一介電層。首 先定義該介電層，在其中形成一溝渠，之後，形成一平迫 層於介電層上並塡滿溝渠**然後，形成圖案化之一光阻層 於平坦層上。接著以圖案化之光阻層爲罩幕，去除部份平 坦層和介電層，以在其中形成一介層窗，其中介層窗位於 溝渠之中。之後，在去除光阻層及平坦層後，形成一金屬 層塡滿溝渠和介層窗，完成雙重金屬鑲嵌製程。 本發明提供另一種雙重金屬鑲嵌製程，在半導體基底 中先形成有一導體層，在基底和導體層上依序爲一第一介 電層、一蝕刻終止層，一第二介電層。首先定義第二介電 層，在其中形成一溝渠，暴露出蝕刻終止層。之後，形成 一平坦層於第二介電層上和溝渠之中。然後，形成圖案化 ·,· 之一光阻層於平坦層上。接著，以圖案化之光阻層爲罩幕’ 去除部份平坦層、蝕刻終止層和第一介電層，以在其中形 成一介層窗。之後，在去除光阻層及平坦層後，於溝渠和 介層窗中之形成一金屬層，完成雙重金屬鑲嵌製程。 本發明尙有其他目的、特徵和優點，將顯示在上述之 6 ------------^)!裝--- <锖先明讀背«之注$項1^寫本ί 訂- ο 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Λ51 327 6590twf,doc/006 A7 B7 經濟部智慧財產局員工消费合作杜印製/ (V This paper size is applicable to two domestic standards (CNS) A4 specifications (2J0 X 297 mm) 6590twf.doc / 006 A7 Printed by Shellfish Consumer Cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of invention (¥) ( Window Process) ° The present invention provides a dual metal damascene process. After the trench is formed, the surface of the substrate is planarized by forming a flat layer using a polymer (Polymer) before etching the interlayer window, and then formed on the flat surface of the flat layer. A photoresist layer with a flat surface to avoid problems caused by uneven photoresist surfaces. The present invention provides a dual metal damascene process. A semiconductor layer is first formed in a semiconductor substrate, and a dielectric layer is formed on the substrate and the conductor layer. Electrical layer. The dielectric layer is first defined, a trench is formed therein, and then a flattening layer is formed on the dielectric layer and fills the trench **. Then, a patterned photoresist layer is formed on the flat layer. The patterned photoresist layer is a mask, and a part of the planarization layer and the dielectric layer are removed to form a dielectric window therein, wherein the dielectric window is located in the trench. After that, the photoresist layer and the planarization layer are removed. After that, a metal layer is formed to fill the trench and the interlayer window to complete the dual metal damascene process. The present invention provides another dual metal damascene process. A semiconductor layer is first formed in the semiconductor substrate, and the substrate and the conductor layer are sequentially A first dielectric layer, an etch stop layer, and a second dielectric layer. The second dielectric layer is first defined, and a trench is formed therein to expose the etch stop layer. After that, a flat layer is formed on the second dielectric layer. Up and in the trench. Then, a patterned photoresist layer is formed on the flat layer. Then, the patterned photoresist layer is used as a mask to remove some of the flat layer, the etch stop layer and the first dielectric layer. An electrical layer to form a dielectric window therein. After removing the photoresist layer and the flat layer, a metal layer is formed in the trench and the dielectric window to complete the dual metal damascene process. The present invention has other objects and features. And advantages, will be displayed in the above 6 ------------ ^)! Packing --- < 明 Xianming read back «Note $ Item 1 ^ copybook ί order-ο thread paper Dimensions are applicable to China National Standard (CNS) A4 (210 X 297 mm) Λ51 327 6590twf, doc / 006 A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economy
五、發明說明（Γ) 說明、下述之實施例以及專利申請範圍之中，或是可在實 施本發明的過程中顯示出來。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下 圖式之簡單說明： 第1Α圖到第1D圖是習知一種雙重金屬鑲嵌製程剖面 示意圖；以及 第2Α圖到第2G圖是依照本發明一較佳實施例，一種 雙重金屬鑲嵌製程流程剖面示意圖。 圖式之標記說明： 100、200 :基底 102、202 :導體層 104、108、204、208 :內金屬介電層 106、206 :蝕刻終止層 110、114、214 :光阻層 112、210 :溝渠 116 :開口 212 ;平坦層 216 :介層窗 218 :金屬層 實施例 第2Α圖至第2G圖，其繪示依照本發明一較佳實施例， 一種利用金屬鑲嵌製程製作多重金屬內連線的流程剖面示 本^張尺度適用中國國家標準(CNS)A4規格(210X 297公HV. Description of the invention (Γ) The description, the following examples, and the scope of patent applications may be displayed during the implementation of the present invention. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description of the following simple illustrations: Figure 1A to FIG. 1D is a schematic cross-sectional view of a conventional dual metal damascene process; and FIGS. 2A to 2G are cross-sectional schematic views of a dual metal damascene process according to a preferred embodiment of the present invention. Description of the drawing symbols: 100, 200: substrates 102, 202: conductor layers 104, 108, 204, 208: inner metal dielectric layers 106, 206: etch stop layers 110, 114, 214: photoresist layers 112, 210: The trench 116: the opening 212; the flat layer 216: the interlayer window 218: the metal layer embodiment 2A to 2G, which illustrate a preferred embodiment of the present invention, a method of making multiple metal interconnections using a metal damascene process The flow profile shown here is based on the Chinese National Standard (CNS) A4 specification (210X 297 male H)
451 327 6590twf.doc/006 雉濟部智慧財產局貝工消t合作社印製 五、發明說明（έ) 意圖。 請參照第2A圖，首先，提供一半導體基底200，在基 底200中已形成有一層導體層202，例如是字元線、位元 線或是金屬線等。接著，是在導體層202和基底200上形 成一層第一介電層204,例如是以化學氣相沈積法形成一 層厚度約6000_10000埃的氧化矽層。接著，在第一內金屬 介電層204上形成一層蝕刻終止層206,蝕刻終止層206 的厚度約爲300-600埃，其材質例如是氮化矽或是氮氧化 矽，較佳爲氮化矽，典型的形成方法例如是化學氣相沈積 法β接著，在蝕刻終止層206上方形成一層第二內金屬介 電層208。例如是以傳統的化學氣相沈積法，形成一層厚 度約爲3000-8000埃的二氧化矽。 本發明中之另一實施例，其中以在導體層202和基底 200上形成單一層介電層來取代依序形成兩層內金屬介電 層，例如是以傳統的化學氣相沈積法，形成一層厚度約爲 8000-20000埃的二氧化矽，而蝕刻終止層可以省略不用》 請再參照第2Β圖，定義第二內金屬介電層208，以在 其中形成溝渠210,典型的方法例如是利用習知的微影蝕 刻製程，對第二內金屬介電層208進行非等向性乾蝕刻， 直到蝕刻終止層206暴露出來爲止。本發明中之另一實施 例，其中可以省略不用蝕刻終止層，利用例如：時間控制 (Time Control)之蝕刻方法，來控制蝕刻溝渠210之深度。 請參照第2C圖，在第二內金屬介電層208上以及溝 渠210之中形成一層平坦層212,並平坦化此平坦層212 本紙張尺度適用中國@標準（CNS)A4規格（210 X 297公釐) 一 裝 訂. o' .線 4 5 1 3 2. 6590twf.doc/006 鋥濟部智慧財產局員工消费合作杜印製 五、發明說明（q > 直至暴露出該第二內金屬介電層208之表面。其中平坦層 212可以是任何聚合材質(Polymer)，只要其蝕刻選擇率與 介電層之蝕刻選擇率相近即可，也就是蝕刻時平坦層之蝕 刻速度可略快於介電層之蝕刻速度；例如爲低介電係數之 氟较玻璃(Fluorinated Silicate Glass, FSG) »或旋塗式有機聚 合物(Spin-On Organic Polymer)(如 Flare, SILK 等）。因爲有 機聚合物的介電常數較低，而且可輕易地利用02電漿或 是利用蝕刻機台來去除。可與光阻時同時被去除。平坦化 該平坦層212之方法可爲利用非等向性回蝕(Etch Back)或 化學機械硏磨法(CMP)。 接著，然後請參照第2D圖，在平坦層212上形成一 層圖案化之光阻層214，此光阻層214具有欲形成介層窗 之圖形。 請參照第2Ε圖，將光阻層214上的圖形轉移到平坦 層212上，例如先以光阻層214爲罩幕，進行非等向性蝕 刻，而當對不準發生時，則該光阻層214之圖案會轉移至 平坦層212上以及部分第二內金屬介電層208上（如圖所 示）；繼續蝕刻蝕刻終止層206和第一內金屬介電層204, 在其中形成介層窗216。蝕刻劑之選擇則視所使用之平坦 層與介電層而定，只要平坦層與介電層之蝕刻選擇率相近 即可，也就是蝕刻時平坦層之被蝕刻速度不能慢於介電層 之被蝕刻速度。此時光阻層214亦會被去除份高度而變薄。 之後，請參照第2F圖，去除光阻層214和平坦層212。 例如利用氧電漿蝕刻來進行，將光阻層214和平坦層212 9 <請先和讀背面之注 訂· Λ—/ i .線 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） 4 5132# 6590twf,doc/006 ---- I _ 五、發明說明（f) 完全去除。其中可以依次去除或一次去除該光阻層214和 平坦層212，視使用之材質而定。 接著，如第2G圖所示，在介層窗216與溝渠210中 形成一層平坦化之金屬層218例如是以氮化鉅/鉅做黏著層 之銅金屬層，完成雙重金屬鑲嵌。由於並非本發明之重點， 不再多作赘述。 由上述本發明較佳實施例可知，本發明係利用聚合物 層造成較佳平坦表面之特性，使得光阻層形成時，亦可得 到平坦之表面，進行微影時，形成的開口不會變形。 本發明除了可以用來製作雙重金屬插塞製程外，尙可 應用於更多重的金屬內連線製程》 雖然本發明已以一較佳實施例揭露如上*然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 嫌先閲讀背面之注$ n n I 1 項ιϊϊ 訂· ο -·線 經濟部智慧財產局具工消費合作社印製 本紙張尺度適用中國國家標芈（CNS)A4規格（210 X 297公釐）451 327 6590twf.doc / 006 Printed by Bei Gong Xiao Cooperative, Bureau of Intellectual Property of the Ministry of Economic Affairs. 5. Description of the invention. Referring to FIG. 2A, first, a semiconductor substrate 200 is provided. A conductive layer 202, such as a word line, a bit line, or a metal line, has been formed in the base 200. Next, a first dielectric layer 204 is formed on the conductor layer 202 and the substrate 200. For example, a silicon oxide layer having a thickness of about 6000 to 10,000 angstroms is formed by a chemical vapor deposition method. Next, an etch stop layer 206 is formed on the first inner metal dielectric layer 204. The thickness of the etch stop layer 206 is about 300-600 angstroms, and the material is, for example, silicon nitride or silicon oxynitride, preferably nitride. A typical method for forming silicon is, for example, chemical vapor deposition method β. Next, a second inner metal dielectric layer 208 is formed over the etch stop layer 206. For example, a conventional chemical vapor deposition method is used to form a layer of silicon dioxide with a thickness of about 3000-8000 angstroms. In another embodiment of the present invention, a single dielectric layer is formed on the conductor layer 202 and the substrate 200 instead of sequentially forming the two inner metal dielectric layers, for example, by a conventional chemical vapor deposition method. A layer of silicon dioxide with a thickness of about 8000-20000 angstroms, and the etch stop layer can be omitted. Please refer to FIG. 2B again to define a second inner metal dielectric layer 208 to form a trench 210 therein. A typical method is Using a conventional lithographic etching process, anisotropic dry etching is performed on the second inner metal dielectric layer 208 until the etching stop layer 206 is exposed. In another embodiment of the present invention, the depth of the etching trench 210 can be controlled by using an etching method such as Time Control without using an etching stop layer. Referring to FIG. 2C, a flat layer 212 is formed on the second inner metal dielectric layer 208 and in the trench 210, and the flat layer 212 is flattened. This paper size is applicable to China @ standard (CNS) A4 specification (210 X 297). (Mm) One binding. O '. Line 4 5 1 3 2. 6590twf.doc / 006 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperation Du printed 5. Description of the invention (q > until the second inner metal medium is exposed The surface of the electrical layer 208. The flat layer 212 can be any polymer material, as long as its etching selectivity is similar to that of the dielectric layer, that is, the etching speed of the flat layer can be slightly faster than that of the dielectric layer. Etching speed of electrical layers; for example, low dielectric constant Fluorinated Silicate Glass (FSG) »or Spin-On Organic Polymer (such as Flare, SILK, etc.). Because organic polymers The dielectric constant is relatively low, and can be easily removed by using 02 plasma or an etching machine. It can be removed at the same time as the photoresist. The method of planarizing the flat layer 212 can be anisotropic etchback (Etch Back) or chemical mechanical honing (CMP ). Then, referring to FIG. 2D, a patterned photoresist layer 214 is formed on the flat layer 212. This photoresist layer 214 has a pattern of a via window to be formed. Referring to FIG. 2E, the photoresist layer is formed. The pattern on 214 is transferred to the flat layer 212. For example, the photoresist layer 214 is used as a mask to perform anisotropic etching. When misalignment occurs, the pattern of the photoresist layer 214 is transferred to the flat layer. 212 and part of the second inner metal dielectric layer 208 (as shown); continue to etch the etch stop layer 206 and the first inner metal dielectric layer 204 to form a dielectric window 216 therein. The choice of etchant depends on The flat layer and the dielectric layer are used, as long as the etching selectivity of the flat layer and the dielectric layer are similar, that is, the etching speed of the flat layer cannot be slower than that of the dielectric layer during etching. At this time, light The resist layer 214 will also be thinned by removing the height. After that, please refer to FIG. 2F to remove the photoresist layer 214 and the flat layer 212. For example, the plasma resist layer 214 and the flat layer 212 may be removed by an oxygen plasma etching 9 < Please read the note on the back · Λ— / i. Applicable to Chinese national standard (CNS > A4 specification (210 X 297 mm) 4 5132 # 6590twf, doc / 006 ---- I _ 5. Description of the invention (f) Complete removal. The photoresist can be removed in sequence or once. The layer 214 and the flat layer 212 depend on the material used. Next, as shown in FIG. 2G, a planarized metal layer 218 is formed in the via window 216 and the trench 210. Layer of copper metal layer to complete the double metal inlay. Since it is not the focus of the present invention, it will not be repeated here. It can be known from the foregoing preferred embodiments of the present invention that the present invention uses the characteristics of the polymer layer to create a better flat surface, so that when the photoresist layer is formed, a flat surface can also be obtained, and the formed openings will not be deformed during lithography. . In addition to the dual metal plug process, the present invention can also be applied to more heavy metal interconnect process. "Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. Read the note on the back of the paper first. $ N n I 1 Item Order ο-· Line Printed by the Industrial Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)