4685tvvf.cloc/006 409362 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（/ ) 本發明是有關於一種金屬內連線之製造方法，且特別 是有關於一種之雙重金屬鑲嵌（Dual Damascene)之製造方 法。 目前在超大型積體電路（VLSI)製程中，許多高積集度 .(Hlgh Integration)的半導體元件，都具有兩層以上的內連線 金屬層，稱爲多重金屬內連線(multilevel interconnects)。當 積體電路的積集度持續增加，.對於製造良率佳，以及可靠 度好的金屬內連線的困難度也會增加；雙重金屬鑲嵌法係 一種在介電層中先蝕刻出金屬內連線的溝渠，再塡入金屬 當作內連線的方法，此法可以滿足製程中對高可靠度及高 良率內連線的要求，所以此法將成爲在深次微米（Sub-Quaner Micron)中內連線製造方法的最佳選擇。然而，目 前仍有許多關於雙重金屬鑲嵌之問題尙在硏究之中，例如 由於不平坦的光阻層表面而造成介層窗的輪廓變形等，於 下文說明之。 第1A圖到第1C圖爲習知的雙重金屬鑲嵌部份製程剖 面示意圖。請參照第1A圖，首先，提供一半導體基底100, 在基底100中已形成有一層金屬層102。接著，在金屬層 102和基底100上方依序形成第一介電層104、蝕刻終止層 106和第二介電層108。然後，在第二介電層108上形成一 層光阻圖形110，光阻圖形110具有預定形成溝渠之圖形。 接著，請參照第1B圖，以光阻圖形11〇(第1A圖）爲 罩幕，蝕刻終止層106爲終點，進行非等向性蝕刻，去除 部份第二介電層108，以在其中形成溝渠112。 (請先閱讀背面之注意事項再填寫本頁〕4685tvvf.cloc / 006 409362 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (/) The present invention relates to a method for manufacturing a metal interconnect, and in particular to a dual metal inlay ( Dual Damascene). At present, in the VLSI process, many semiconductor devices with high integration (Hlgh Integration) have more than two metal interconnect layers, called multilevel interconnects. . When the integration degree of integrated circuits continues to increase, the difficulty of manufacturing metal interconnects with good yield and reliability will also increase; the dual metal damascene method is a method of first etching out the metal in the dielectric layer The method of interconnecting trenches and injecting metal into the interconnect can meet the requirements for high reliability and high yield interconnects in the manufacturing process. Therefore, this method will become a sub-Quaner Micron ) The best choice for the manufacturing method of the interconnects. However, there are still many questions about double metal damascene, such as the deformation of the contour of the interlayer window caused by the uneven surface of the photoresist layer, etc., as described below. Figures 1A to 1C are schematic cross-sectional views of a conventional double metal damascene process. Referring to FIG. 1A, first, a semiconductor substrate 100 is provided, and a metal layer 102 has been formed in the substrate 100. Next, a first dielectric layer 104, an etch stop layer 106, and a second dielectric layer 108 are sequentially formed over the metal layer 102 and the substrate 100. Then, a layer of a photoresist pattern 110 is formed on the second dielectric layer 108, and the photoresist pattern 110 has a pattern for forming a trench. Next, referring to FIG. 1B, using the photoresist pattern 11 (FIG. 1A) as a mask and the etch stop layer 106 as an end point, anisotropic etching is performed, and a part of the second dielectric layer 108 is removed, so that Form a ditch 112. (Please read the notes on the back before filling this page)
本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 4685twf.cfoc/〇〇6 , A7 4Π9362 B7 五、發明説明（2) 接著請參照第1C圖，在基底100上全面性形成一層 光阻層114，覆蓋第二介電層108並塡入溝渠112之中。 由於溝渠112底部和第二介電層108表面之間有相當大的 高度差（介電層的厚度約3000-8000埃）。因此形成的光阻 .層114表面的平坦度亦不佳。之後，圖案化光阻層114， .在光阻層中形成欲形成介層窗之開口 116。然而由於光阻 層1M的表面並不平坦，故形成之開口 1丨6亦會變形（如圖 所示）1進而後續以光阻層114爲罩幕來進行第一介電層之 蝕刻時，無法控制形成介層窗的關鍵尺寸（CD)。如果增加 光阻層厚度來改進此情形時，又會對微影的解析度造成負 面之影響。 因此本發明的目的之一，就是在提供一種雙重金屬鑲 嵌的製程，可改進光阻表面之平坦度。 本發明提供一種雙重金屬鑲嵌的製程，溝渠形成後， 蝕刻介層窗前，利用旋塗聚合物（Spin-On Polymer)將基底 表面平坦化，之後再於旋塗檠合物的平坦表面上形成一層 平具有平坦表面之光阻層。 本發明提供一種雙重金屬鑲嵌製程，在半導體基底中 先形成有〜導體層，在基底和導體層上依序爲一第一介電 層、—蝕刻終止層，一第二介電層。首先定義第二介電層， 在其中形成一溝渠，暴露出蝕刻終止層。之後，以旋轉塗 形成〜旋塗式聚合物層於第二介電層上和溝渠之中。 然、胃’形成圖案化之一光阻層於旋塗式聚合物層上。接著 以'圖案化之旋塗式聚合物層爲罩幕，去除部份旋塗式聚合 4 本紙張尺度適ϋ國') Α4·Τ210Χ297^¥1 (請先閲讀背面之注意事項再填寫本頁) IT- -線 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 A7 46 8 5t\vf.doc/00 6 409302 五、發明説明（彡） 物層、蝕刻終止層和第一介電層，以在其中形成一介層窗， 其中介層窗位於溝渠之中。之後，在去除光阻層及旋塗聚 合物層後，於溝渠和介層窗中之形成一金屬層，完成雙重 金屬鑲嵌製程。 本發明尙有其他目的、特徵和優點，將顯示在上述之 說明、下述之實施例以及專利申請範圍之中，或是可在實 施本發明的過程中顯示出來。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下= 圖式之簡單說明： 第1A圖到第1C圖是習知一種雙重金屬鑲嵌製程剖面 示意圖；以及 第2A圖到第2F圖是依照本發明一較佳實施例，一種 雙重金屬鑲嵌製程流程剖面示意圖。 圖式之標記說明： 100、200 :基底 102、202 :導體層 104、108、204、208 :內金屬介電層 )06、206 :蝕刻終止層 110、1 14、214 :光阻層 112、210 :溝渠 116 :開口 212 ;平坦層(旋塗聚合物層） (請先閲讀背面之注意事項再填寫本頁) 訂_ 線- 本紙張又度適用中國國家標準（CNS ) A4規格（210Χ297公釐） 4685twf.doc/000 _AB7__ 五、發明説明（¥ ) 216 :介層窗 218 :金屬層 實施例 第2A圖至第2F圖’其繪示依照本發明一較佳實施例， •一種利用金屬鑲嵌製程製作多重金屬內連線的流程剖面示 意圖。 請參照第2A圖，首先，提供—半導體基底200，在基 底200中已形成有一層導體層2〇2，例如是字元線、位元 線或是金屬線等。接著，是在導體層202和基底200上形 成一層第一內金屬介電層204,例如是以化學氣相沈積法 形成一層厚度約6000-10000埃的氧化矽層。接著，在第一 內介電層204上形成一層蝕刻終止層206，蝕刻終止層206 的厚度約爲300-600埃，其材質例如是氮化矽枣是氮氧化 矽，較佳爲氮氧化矽，典型的形成方法例如是化學氣相沈 積法。接著，在蝕刻終止層206上方形成一層第二內金屬 介電層208。例如是以傳統的化學氣相沈積法，形成一層 厚度約爲3000-8000埃的二氧化矽。 請再參照第2B圖，定義第二內金屬介電層208，以在 其中形成溝渠210,典型的方法例如是利用習知的微影蝕 刻製程，對第二內金屬介電層208進行非等向性乾蝕刻直 到蝕刻終止層暴露出來爲止。 請參照第2C圖，在第二內金屬介電層208上以及溝 渠210之中形成一層平坦層212，並平坦化此平坦層212。 其中平坦層212可以是任何適用旋轉塗覆法之材質，如 6 (請先閲讀背面之注意事頃再填寫本頁) T·.:—訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ^6851 wf,doc/0 06 4093½ A7 B7 五 經濟部智慧財產局員工消費合作社印製 發明説明（y) :G(Spin-On Glass)等旋塗式聚合物’較佳爲旋塗式有機聚 Q 物（Spin-〇n Oi-ganic p〇lymer)(如 Flare，SILK 等）。因爲有 f聚合物的介電常數較低，而且可輕易地利用〇2電漿或 =利用蝕刻機台來去除。可與光阻時同時被去除。旋塗聚 合物層212由於是利用旋轉塗覆法所製作，故具有平坦之 表面。接著’在旋塗聚合物層Μ〗上形成一層圖案化之光 阻層214 ’此光阻層214具有欲形成介層窗之圖形。 然後ρβ參Pm弟2D圖’將光阻層214上的圖形轉移到 旋塗聚合物層212上，之後再轉移到第—內金屬介電層204 上。例如先以光阻層214爲罩幕，進行非等向性蝕刻，待 貪虫刻終止層206暴露出爲止，再同一蝕刻機台中，改變蝕 刻劑’依序蝕刻蝕刻終止層206和第二內金屬介電層2〇4， 在其中形成介層窗216。此時光阻層214亦會被去除份高 度而變薄。 之後’請參照第2E圖，去除光阻層214和旋塗聚合 物層212。例如利用氧電漿或是；piare蝕刻機來進行，將光 阻層214和旋塗聚合物層212完全去除。 接著’在介層窗216與溝渠214中沉積一層金屬層218 例如是銅金屬層，完成如第2E圖所示之雙重金屬鑲嵌° 由於並非本發明之重點，不再多作贅述。 由上述本發明較佳實施例可知，本發明係利用旋塗聚 合物層有較佳平坦表面之特性，使得光阻層形成時，亦可 得到平坦之表面，進行微影時，形成的開口不會變形。 而且以旋塗聚合物層之材質爲有機聚合物，可與光阻 本紙張尺度適用中國國家操準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) -裝； -訂 線 4 6 8 51 w f. d o c / Ο Ο 6 409362 A7 B7 五、發明説明（G) 層同時移除。 本發明除了可以用來製作雙重金屬插塞製程外，尙可 應用於更多重的金屬內連線製程。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 {請先聞讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS > A4規格（210 X 297公釐）This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 4685twf.cfoc / 〇〇6, A7 4Π9362 B7 V. Description of the invention (2) Then please refer to Figure 1C to form a layer on the substrate 100. The photoresist layer 114 covers the second dielectric layer 108 and is inserted into the trench 112. Due to the considerable height difference between the bottom of the trench 112 and the surface of the second dielectric layer 108 (the thickness of the dielectric layer is about 3000-8000 angstroms). Therefore, the flatness of the surface of the photoresist layer 114 is not good. Thereafter, the photoresist layer 114 is patterned to form an opening 116 in the photoresist layer to form a via window. However, because the surface of the photoresist layer 1M is not flat, the openings 1 丨 6 formed will also be deformed (as shown in the figure). 1 When the photoresist layer 114 is used as a mask to etch the first dielectric layer, There is no control over the critical dimension (CD) that forms the via. If the thickness of the photoresist layer is increased to improve this situation, it will negatively affect the resolution of the lithography. Therefore, one of the objectives of the present invention is to provide a double metal embedding process, which can improve the flatness of the photoresist surface. The invention provides a double metal inlaying process. After the trench is formed, the surface of the substrate is flattened by using a spin-on polymer before etching the interlayer window, and then formed on the flat surface of the spin-on compound A flat photoresist layer with a flat surface. The present invention provides a dual metal damascene process. A semiconductor layer is first formed in a semiconductor substrate, and a first dielectric layer, an etch stop layer, and a second dielectric layer are sequentially formed on the substrate and the conductor layer. First define a second dielectric layer, form a trench therein, and expose the etch stop layer. Then, a spin-on polymer layer is formed on the second dielectric layer and in the trench by spin coating. However, the stomach 'forms a patterned photoresist layer on the spin-on polymer layer. Then use the "patterned spin-coating polymer layer as a mask, removing some of the spin-coating polymer 4 paper size suitable country") Α4 · Τ210χ297 ^ ¥ 1 (Please read the precautions on the back before filling this page ) IT--Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 46 8 5t \ vf.doc / 00 6 409302 V. Description of the invention (彡) Physical layer, etching stop layer And the first dielectric layer to form a dielectric window therein, wherein the dielectric window is located in the trench. After that, after removing the photoresist layer and the spin-coating polymer layer, a metal layer is formed in the trench and the via window to complete the dual metal damascene process. The present invention has other objects, features, and advantages, and will be shown in the above description, the following embodiments, and the scope of patent applications, or it can be shown in the process of implementing the present invention. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below, and the following detailed description is given in conjunction with the accompanying drawings. = Brief description of the drawings: Figure 1A FIG. 1C is a schematic cross-sectional view of a conventional dual metal damascene process; and FIGS. 2A to 2F are schematic cross-sectional schematic views of a dual metal damascene process according to a preferred embodiment of the present invention. Explanation of the marks of the drawings: 100, 200: substrates 102, 202: conductor layers 104, 108, 204, 208: inner metal dielectric layers) 06, 206: etch stop layers 110, 114, 214: photoresist layers 112, 210: trench 116: opening 212; flat layer (spin-coated polymer layer) (please read the precautions on the back before filling out this page) Order _ Line-This paper is also applicable to China National Standard (CNS) A4 specification (210 × 297) (Centi) 4685twf.doc / 000 _AB7__ V. Description of the invention (¥) 216: Interlayer window 218: Metal layer embodiment Figures 2A to 2F 'It shows a preferred embodiment according to the present invention, Schematic cross-sectional view of the process of making multiple metal interconnects by the damascene process. Referring to FIG. 2A, first, a semiconductor substrate 200 is provided. A conductive layer 202 has been formed in the substrate 200, such as a word line, a bit line, or a metal line. Next, a first inner metal dielectric layer 204 is formed on the conductor layer 202 and the substrate 200. For example, a silicon oxide layer having a thickness of about 6000-10,000 angstroms is formed by a chemical vapor deposition method. Next, an etch stop layer 206 is formed on the first inner dielectric layer 204. The thickness of the etch stop layer 206 is about 300-600 angstroms. The material is, for example, silicon nitride, silicon oxynitride, and preferably silicon oxynitride A typical formation method is, for example, a chemical vapor deposition method. Next, a second inner metal dielectric layer 208 is formed over the etch stop layer 206. For example, a conventional chemical vapor deposition method is used to form a layer of silicon dioxide with a thickness of about 3000-8000 angstroms. Please refer to FIG. 2B again to define the second inner metal dielectric layer 208 to form the trench 210 therein. A typical method is to use a conventional lithography etching process to perform non-equalization on the second inner metal dielectric layer 208. Anisotropically dry etch until the etch stop layer is exposed. Referring to FIG. 2C, a flat layer 212 is formed on the second inner metal dielectric layer 208 and in the trench 210, and the flat layer 212 is planarized. The flat layer 212 can be any material suitable for the spin coating method, such as 6 (Please read the notes on the back before filling in this page) Applicable to China National Standard (CNS) A4 specification (210X297 mm) ^ 6851 wf, doc / 0 06 4093½ A7 B7 Five printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, Invention Description (y): G (Spin-On Glass), etc. The spin-coating polymer is preferably a spin-on organic polymer (such as Flare, SILK, etc.). Because of the low dielectric constant of the f polymer, it can be easily removed by using a 02 plasma or an etching machine. Can be removed simultaneously with photoresist. The spin-coating polymer layer 212 has a flat surface because it is produced by a spin coating method. Next, a patterned photoresist layer 214 is formed on the spin-coated polymer layer M. This photoresist layer 214 has a pattern of a via window to be formed. Then the ρβ and Pm 2D pattern 'transfers the pattern on the photoresist layer 214 to the spin-on polymer layer 212, and then to the first inner metal dielectric layer 204. For example, first use the photoresist layer 214 as a mask to perform anisotropic etching until the etch stop layer 206 is exposed, and then in the same etching machine, change the etchant to sequentially etch the etch stop layer 206 and the second inner layer. A metal dielectric layer 204 is formed with a dielectric window 216 therein. At this time, the photoresist layer 214 is also thinned by removing the height. After that, referring to FIG. 2E, the photoresist layer 214 and the spin-on polymer layer 212 are removed. For example, using an oxygen plasma or a piare etching machine, the photoresist layer 214 and the spin-on polymer layer 212 are completely removed. Next, a metal layer 218, such as a copper metal layer, is deposited in the interlayer window 216 and the trench 214, and the double metal inlay shown in FIG. 2E is completed. It can be known from the above-mentioned preferred embodiments of the present invention that the present invention utilizes the characteristics of a better flat surface of the spin-coated polymer layer, so that when the photoresist layer is formed, a flat surface can also be obtained. Will deform. Moreover, the material of the spin-coated polymer layer is organic polymer, which can be used with the photoresist. The paper size is applicable to China National Standards (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page)- Assembly;-Thread 4 6 8 51 w f. Doc / Ο Ο 6 409362 A7 B7 5. The description of the invention (G) layer is removed at the same time. The invention can be used to make double metal plugs, and it can also be applied to more heavy metal interconnects. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. {Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to Chinese national standards (CNS > A4 specifications (210 X 297 mm)