415032 A7 _______B7 五、發明说明（） 發明領域： 本發明係有關於一種形成雙鎮澈（duai damascence) 結構於積體電路元件之方法，特別是一種無須利用蝕刻中 止層之雙鑲嵌製程。 發明背景： 當積體電路趨向高積集度發展，晶片表面已無法提 供足夠面積製作所需的内連線時，為了配合電晶體縮小 後所增加的内連線需求，兩層以上的金屬層設計已成為 許多積體電路採用的方式，特別是—些較複雜的產品， 如微處理器’甚至需要四層或五層的多層金屬層 (multiple metal levels)，才得以完成各元件之間的 連接。 其中雙鑲嵌技術被用在越來越多的半導體製程中，因 為雙鑲嵌技術同時形成内連線及插塞，可以減少好幾個分 別形成它們的傳統步驟。然而，在建立積體結構時，若沒 有發展特定的步驟’以好好發揮鑲嵌的優點，内連線及插 塞的特性通常會被降低= 鑲嵌技術是將金屬内連線鑲入底材上的溝槽，並且是 積體電路中’一種較被喜愛的内連線製程技術。相反的， 較傳統的内連接是在如二氧化矽的絕緣層上，全面性地沈 積一導電物質，然後在導電層上，蝕刻出需要的線路圖案。 ________第；;頁_ 本紙張尺度埴用中國國家搮準（CNS ) M規格（2丨〇)<297公釐） {請先閏讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產馬員工消#合作社印製 415032 A7 __ B7 五、發明説明（） 在線路層間的垂直連接，是分別在隔離金屬層的絕緣層上 鑽洞’然後用相同或不同的導電物質來填滿它們。 一般而言’半導體底材包含被動區及主動區，其主動 區含有在半導體底材表面附近形成的主動元件，主動元件 藉由内導體層做内連接。一或更多的金屬連線層，藉由重 疊内介電層而形成’並被絕緣層隔離。線條紋藉由穿過絕 緣層’且填滿金屬的洞，彼此間互相連接，並且與元件在 適當的地方連接。穿過絕緣層連接金屬線的洞叫做插塞洞 (via hole)，而穿過絕緣層到達元件下面的洞叫做接觸洞 (contact hole)。典型來說，絕緣層沈積在底材上後，洞 才被蝕刻在絕緣層。通常這樣便於下一次全面性地沈積金 屬在絕緣層上，並順便將洞填滿，然後藉著有圖案的光阻 罩’將光阻罩的圈案姓刻在金屬層上後，形成金厲線。對 第一層金屬層而言’是由接觸洞或視窗，與元件下面做電 性接觸，如此允許金屬向下穿過介電絕緣層而至元件。對 接下來第一層的連線層而言’重複上面的製程過程，金屬 層之間的接觸，是透過插塞洞，其允許金屬向下延伸到另 一層金屬層。通常先用金屬分別將洞填滿，以形成金屬插 塞，次以絕緣層表面為基準’做平坦化，再沈積一金屬層， 使金屬層與插塞洞接觸，最後再如前地蝕刻，以形成因應 不同需要的連線層。 利用雙鑲嵌以形成内連接的過程，由第一圖至第三圖 作說明。參考第一围，於一具有内連線金屬導電層125的 基材110上’依序形成第一絕緣層130、蝕刻中止層138 及第二絕緣層140,接著於第二絕緣層14〇上塗覆一光阻 —丄/ 代 π、——-mm--- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作杜印製 ^------ L 【 - S <1 A7 B7 115032 五、發明説明（ (沒有顯示在圖上）’此一光阻藉著第一光罩投影插塞開口 135的圖案而曝光，第二絕緣層14 0.的圖案是非等向性姓 刻’且往下直到蝕刻中止層1 38。參考第二圖，第一光罩 圖案對齊後’光阻現在藉由第二光罩投影導線開口 ί5〇的 圖案°非等向性蚀刻第二絕緣層的導電開口 1 5 〇時，第二 絕緣層140的插塞開口 us，同時被蝕刻及複製在第一絕 緣層130。參考第三圖’蝕刻完成後，插塞開口 U5及導 線開口 1 50，被金屬1 60填滿，並將底材作祀學機械研磨 (CMP) ’直到第二絕緣層140的上表面為止，鑲了金屬的底 材表面’完成平坦化後，以用於更進一步的製程β 傳統的雙鑲嵌製程，一定必須利用蝕刻中止層，以 做為姓刻插塞圖案與導線開口圖案的區別，然而，在製 造兩密度的深次微米（deep sub - micron)尺寸元件或 是更小尺寸元件的製程中，元件之間的連線結構，必須 能滿足更小線寬的要求，而又要能夠維持低電阻的特 性，方能確保元件低消耗功率及低發熱量的特性而蝕 刻中止層之高介電常數將有礙於高操作速度、低電阻— 電容延遲效應（RC-del ay)以及高可靠度之電路的發 展。因此’雙鑲嵌製程將朝無蝕刻中止層的方向發展， 然而，基材的導線密度於各個不同的區域有異，將導致 這些不同密度之基材區域有不同的蝕刻速率，此將阻礙 無蝕刻中止層之雙鑲嵌製程的發展。 因此，本發明即針對此一困難，提供一無須利用蝕刻 中止層之雙鑲嵌的製程方法。 各紙張从適用中ig家標準{CNS)八4胁（210χϋ兔 <請先閱婧背面之注意事項再填寫本夏) 、1Τ Λ丨- 經濟部智慧財產局員工消費合作杜印製 A7 _________B7 五、發明説明（） 發明目的及概.述： 本發明之目的為提供一種無蝕刻中止層之雙鎮嵌 的連線結構，以減少半導體製程的步驟。 本發明之另一目的為提供一種無蝕刻中止層之雙 鑲嵌結構，以提供高操作速度與低電阻-電容的延遲效 應。 本發明所提供之無蝕刻中止層的雙鑲嵌製製作方 法，該方法至少包含下列步驟：首先，提供一半導艘基 材，基材上已具有銅導線層，接著於基材上形成第_絕、緣 層，並形成第二絕緣層，其中第一絕緣層與第二絕緣層最 好選擇低介電常數的物質。 接著利用微影與蝕刻技術，形成一介層洞開σ於第— 絕緣層與第二絕緣層中’並利用第二次的微影與麵刻步鄉於 第二絕緣層中形成溝渠開口，由於第二次的蝕刻步称對第_ 絕緣層具有相對於第二絕緣層較小之蝕刻速率，因此，第— 絕緣層並不會被侵蝕。最後，以物理氣相沈積法，沈積_金 屬層於基材上’介層洞開口與溝渠開口被金屬填滿，並將基 材作化學機械研磨（CMP)，直到第二絕緣層的上表面為止 以完成雙鑲嵌结構之製程。 圖式簡軍說明= 第一圊為半導體晶圓的截面圖，圊中顯示習知技術中 本紙張尺度通用中國國家揉率（CNS ) A4規格（210Χ2$14 } (請先聞讀背面之注項再填寫本頁) 、1Τ ύά! 經濟部智慧財產局員工消費合作社印製 415032 Λ7 Α7 -----87 五、發明説明（） 形成插塞開口的情形，其中於第一絕緣層與第二絕緣層之 間存在一钱刻中止層。 第二圏為半導體晶圓的截面圖，圖中顯示習知技術中 形成導電開口的情形。 第三圊為半導體晶圓的截面圖，圖中顯示習知技術中 形成插塞結構與導電結構的情形。 第四圖為半導體晶圓的載面圓，圖中顯示本發明中形 成介層洞開口的情形，其中並無應用蝕刻中止層的存在。 第五圖為半導體晶圓的截面圖’圖中顯示本發明中形 成導電開口的情形。 第六圖為半導體晶圓的截面圖，圖中顯示本發明中形 成插塞結構與導電結構的情形》 發明詳細說明： 經濟部智慧財產局員工消費合作杜印製 ------------,水------π (請先閱讀背面之注意事項再填寫本頁)415032 A7 _______B7 V. INTRODUCTION TO THE INVENTION Field of the Invention: The present invention relates to a method for forming a duai damascence structure on an integrated circuit element, particularly a dual damascene process without using an etching stop layer. Background of the Invention: When integrated circuits tend to develop with a high degree of integration and the surface of the chip can no longer provide sufficient area for the interconnections required for fabrication, in order to meet the increased interconnection requirements after the transistor has shrunk, there are more than two metal layers. Design has become the approach adopted by many integrated circuits, especially some more complex products, such as microprocessors, which even require four or five layers of multiple metal levels in order to complete the connection. The dual damascene technology is used in more and more semiconductor processes, because the dual damascene technology simultaneously forms interconnects and plugs, which can reduce several traditional steps to form them. However, when building an integrated structure, if there are no specific steps developed to take full advantage of the inlay, the characteristics of the interconnects and plugs will usually be reduced = Mosaic technology is to insert metal interconnects into the substrate Trenches are one of the most popular interconnect technology in integrated circuits. In contrast, the more traditional internal connection is to deposit a conductive substance on an insulating layer such as silicon dioxide, and then etch the required circuit pattern on the conductive layer. ________ 第 ;; page_ This paper size is in accordance with China National Standards (CNS) M specification (2 丨 〇) < 297 mm) {Please read the notes on the back before filling this page) Order the wisdom of the Ministry of Economic Affairs Property Horse Employees Consumer #Cooperative Society Printing 415032 A7 __ B7 V. Description of the invention () The vertical connection between circuit layers is to drill holes in the insulation layer of the isolation metal layer and then fill them with the same or different conductive materials . Generally speaking, a 'semiconductor substrate includes a passive region and an active region. The active region contains an active element formed near the surface of the semiconductor substrate. The active element is internally connected by an inner conductor layer. One or more metal wiring layers are formed 'by overlapping the inner dielectric layer and are isolated by the insulating layer. The line stripes are connected to each other by passing through the insulating layer 'and filled with metal holes, and are connected to the components at appropriate places. The hole that connects the metal line through the insulation layer is called a via hole, and the hole that passes through the insulation layer and under the component is called a contact hole. Typically, the holes are etched into the insulating layer after the insulating layer is deposited on the substrate. Usually this is convenient for the next comprehensive deposition of metal on the insulating layer, and by the way fill the hole, and then use the patterned photoresist mask to engrav the circle name of the photoresist mask on the metal layer to form gold. line. For the first metal layer, 'is a contact hole or window that makes electrical contact with the component underneath. This allows the metal to pass through the dielectric insulation layer down to the component. For the next connection layer of the first layer, the process is repeated. The contact between the metal layers is through the plug hole, which allows the metal to extend down to another metal layer. Usually, the holes are first filled with metal to form metal plugs, then the surface of the insulating layer is used as a reference for planarization, and then a metal layer is deposited to make the metal layer contact the plug hole, and finally etched as before. In order to form a wiring layer corresponding to different needs. The process of using dual damascene to form an interconnect is illustrated by the first to third figures. Referring to the first circumference, a first insulating layer 130, an etching stop layer 138, and a second insulating layer 140 are sequentially formed on a substrate 110 having an interconnect metal conductive layer 125, and then coated on the second insulating layer 140. Cover a photoresistor— 丄 / 代 π, ——- mm --- (Please read the precautions on the back before filling out this page) Order the consumer cooperation agreement of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ ------ L [-S < 1 A7 B7 115032 5. Description of the invention ((not shown on the figure) 'This photoresist is exposed by projecting the pattern of the plug opening 135 through the first photomask, and the second insulating layer 14 0. The pattern is engraved with an anisotropic name and it goes down to the etching stop layer 1 38. Referring to the second figure, after the first photomask pattern is aligned, the photoresist is now patterned by the projection of the opening of the wire through the second photomask. When the conductive opening of the second insulating layer is etched 150 °, the plug opening us of the second insulating layer 140 is simultaneously etched and copied in the first insulating layer 130. Refer to the third figure 'After the etching is completed, the plug opening U5 and wire openings 1 50, filled with metal 1 60, and the substrate is used as a mechanical mechanical polishing (CMP) 'until Up to the upper surface of the two insulating layers 140, the surface of the metal-inlaid substrate is 'planarized' and used for further processing. In the traditional double-damascene process, the etching stop layer must be used as a plug for the last name. The difference between the pattern and the wire opening pattern. However, in the process of manufacturing two-density deep sub-micron size components or smaller size components, the connection structure between the components must be able to meet the smaller lines. Wide requirements, while maintaining the characteristics of low resistance, can ensure the low power consumption and low heat generation characteristics of the device, and the high dielectric constant of the etching stop layer will hinder high operating speed, low resistance-capacitance delay effect (RC-del ay) and the development of high-reliability circuits. Therefore, the 'dual damascene process will develop in the direction of no etch stop layer. However, the wire density of the substrate is different in different regions, which will lead to these different densities. The substrate area has different etch rates, which will hinder the development of a dual damascene process without an etch stop layer. Therefore, the present invention addresses this difficulty and provides nothing. It is necessary to use the double inlaying process of the etching stop layer. Each paper is from the applicable Chinese standard {CNS) Ya 4 4 (210χϋ 兔 < please read the precautions on the back of Jing before filling in this summer), 1Τ Λ 丨-Economy The Intellectual Property Bureau of the Ministry of Intellectual Property Bureau's consumer cooperation printed A7 _________B7 V. Description of the invention () Purpose and summary of the invention: The purpose of the present invention is to provide a double-embedded connection structure without an etch stop layer to reduce the semiconductor manufacturing process. step. Another object of the present invention is to provide a dual damascene structure without an etch stop layer to provide a high operation speed and a low resistance-capacitance delay effect. The method for manufacturing a dual damascene without an etching stop layer provided by the present invention includes at least the following steps: First, a half of the guide substrate is provided, the substrate already has a copper wire layer, and then a first insulating layer is formed on the substrate. And a marginal layer, and form a second insulating layer, wherein the first insulating layer and the second insulating layer are preferably selected from a substance having a low dielectric constant. Then use lithography and etching technology to form a via hole σ in the first insulation layer and the second insulation layer, and use the second lithography and surface engraving step to form a trench opening in the second insulation layer. The second etching step is said to have a smaller etching rate for the first insulating layer than the second insulating layer, so the first insulating layer will not be eroded. Finally, a physical vapor deposition method is used to deposit a metal layer on the substrate. The interstitial hole openings and trench openings are filled with metal, and the substrate is subjected to chemical mechanical polishing (CMP) until the upper surface of the second insulating layer. So far to complete the process of dual mosaic structure. Brief explanation of the drawing = The first part is a cross-sectional view of a semiconductor wafer. The second part shows the conventional Chinese paper size (CNS) A4 size (210 × 2 $ 14) in the conventional technology. (Please read the note on the back first. Fill out this page again), 1Τ ύά! Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 415032 Λ7 Α7 ----- 87 V. Description of the invention () The situation where the plug opening is formed, where the first insulation layer and the second There is a coin-cut stop layer between the insulating layers. The second part is a cross-sectional view of a semiconductor wafer, which shows the conductive opening formed in the conventional technology. The third part is a cross-sectional view of a semiconductor wafer, which shows The situation of forming the plug structure and the conductive structure in the known technology. The fourth figure is the circle carrying surface of the semiconductor wafer, and the figure shows the situation of the formation of the via hole in the present invention, in which the presence of the etching stop layer is not applied. The fifth figure is a cross-sectional view of a semiconductor wafer. The figure shows a situation where a conductive opening is formed in the present invention. The sixth figure is a cross-sectional view of a semiconductor wafer, which shows a situation where a plug structure and a conductive structure are formed in the present invention. " Detailed description of the invention: Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed ------------, water ------ π (Please read the precautions on the back before filling this page)
參考第四圖’首先’提供一半導體基材21〇,基材21〇 上已具有銅導線層225，接著’於基材上形成厚約 至9000埃的第一絕緣層230’其係利用一般化學氣相沈積 製程形成，如PECVD或LPCVD等。接著，以pecvD或LPCVD 等沈積法形成厚約4000至1 0000埃的第二絕緣層24〇。以 —較佳的實施例而言’第一絕緣層230與第二絕緣層24〇 最好選擇低介電常數的物質。 接著於第二絕緣層240上塗覆一光阻（沒有顯示在圖 ____161___ 本紙張尺度適用中囷國家標準（CNS ) A4規格（210X297公釐） - 415032 A7 B7 五、發明説明（ 上）’此一光阻藉著第一光罩投影開口 235的圖案而曝光， 接著以非等向性蝕刻技術，蝕刻第一絕緣層230與第二絕緣 層240 ’且往下直到銅導線層225，而開口 235係用於產生 銅導線層225與第二絕緣層24〇之溝渠間的介層洞（vi& ho 1 e) ’然後除去該第一光阻層。以一較佳的實施例而言， 此處所選擇的蝕刻劑，對第一絕緣層2 3 〇與第二絕緣層 240並無太大的蝕刻速率差異，例如選擇第一絕緣層 為氟矽玻璃（f l〇urine si i icate glass, FSG)，第二絕緣 層240為二氧化矽，並利用含氮氣與氧氣於溫度約25它至 500 C，與壓力1至i〇〇0t〇rr之間進行此一蝕刻步驟。 參考第五圖，將光阻與第二光罩圖案對齊後，光阻現 在藉由第二光罩投影溝渠開口 25〇的圖案，並實施非等向性 蝕刻，而於第二絕緣層240中形成溝渠開口 25〇，由於此處 所選擇之非等向性蝕刻劑對第一絕緣層23〇具有相對於第 二絕緣層240較小之蝕刻速率，因此，第一絕緣層23〇並不 會被侵蝕。以一較佳實施例而言，例如選擇第一絕緣層23〇 為氟矽玻璃（flourine silicate gUss，FSG),選擇第二 絕緣層240為二氧化矽’此兩物質均為低介電常數物質， 且利用含氟氣與氧軋的蚀刻劑，於溫度約2 5 至5 〇 〇 °c , 與壓力1至1 000 torr之間進行此一蝕刻步驟。氟矽玻璃 (FSG)較無摻雜矽玻璃（lJSG)的蝕刻速率高約1〇〇至 1 0000%。 本紙張尺度逷用中國國家標準（CNS ) A4規格（ (請先W讀背面之注意ί項再填寫本頁) -訂 經濟部智慧財產局員工消費合作杜印製 415032 A7 --------B7 __ 五、發明説明（） 形成溝渠開口 235於第二絕緣層240後，以物理氣相 沈積法，沈積一金屬層160於基材210上，介層洞235與溝 渠開口 23 5被金屬160填滿，並將基材作化學機械研磨 (CMP)，直到第二絕緣層240的上表面為止，鑲了金屬的底 材表面，完成平坦化後，以用於更進一步的製程。 綜上所述，本發明所提供之製程方法，係於形成介層 洞開口與溝渠開口時，利用不同蝕刻劑之選擇，以達成無蝕 刻中止層之雙鑲嵌結構的製程，本發明由於無須高介電常數 之蝕刻中止層的使用’因此，不僅可提高元件的操作速度、 減少電阻-電容延遲效應（RC-delay)以及提高電路之可靠 度’並可簡化傳統之製程步驟，以節省製程成本。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離本發明所揭示之精 神下所完成之等效改變或修飾，均應包含在下述之申請專利 範圍内。 II------I (請先閲讀背面之注意事項再填寫本買) 經濟部智慧財產局員工消費合作杜印製Referring to the fourth figure, 'First', a semiconductor substrate 21 is provided, which has a copper wire layer 225 on it, and then a first insulating layer 230 having a thickness of about 9000 angstroms is formed on the substrate. Chemical vapor deposition processes, such as PECVD or LPCVD. Next, a second insulating layer 24 is formed to a thickness of about 4000 to 10,000 angstroms by a deposition method such as pecvD or LPCVD. In a preferred embodiment, the first insulating layer 230 and the second insulating layer 24 are preferably made of a low dielectric constant material. Then apply a photoresist on the second insulating layer 240 (not shown in the figure ____161___) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm)-415032 A7 B7 V. Description of the invention (top) A photoresist is exposed by projecting the pattern of the opening 235 through the first mask, and then anisotropic etching is used to etch the first insulating layer 230 and the second insulating layer 240 ′ and go down to the copper wire layer 225 to open the opening. 235 is used to generate a via hole (vi & ho 1 e) between the copper wire layer 225 and the trench of the second insulating layer 24. Then, the first photoresist layer is removed. In a preferred embodiment, The etchant selected here does not have a large difference in etching rate between the first insulating layer 2 3 0 and the second insulating layer 240. For example, the first insulating layer is selected as fluorosilicic glass (Flourine si i icate glass, FSG). ), The second insulating layer 240 is silicon dioxide, and this etching step is performed using nitrogen and oxygen at a temperature of about 25 to 500 C, and a pressure of 1 to 1000 trr. Referring to the fifth figure, After aligning the photoresist with the second mask pattern, the photoresist is now The photomask projects the pattern of the trench opening 25 ° and performs anisotropic etching, and a trench opening 25 ° is formed in the second insulating layer 240. The first insulating layer 23 is formed by the non-isotropic etchant selected here. It has a lower etch rate than the second insulating layer 240. Therefore, the first insulating layer 23 will not be eroded. In a preferred embodiment, for example, the first insulating layer 23 is selected as a fluorosilicon glass ( flourine silicate gUss (FSG), the second insulating layer 240 is selected as silicon dioxide, both of which are low-dielectric constant materials, and use fluorine-containing gas and oxygen rolling etchant at a temperature of about 25 to 5 00. ° C, this etching step is performed at a pressure of 1 to 1,000 torr. Fluorosilicate glass (FSG) has an etching rate about 100 to 10,000% higher than that of undoped silica glass (1JSG). Use Chinese National Standard (CNS) A4 specification ((Please read the note on the back and fill in this page first)-Order the consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs Du printed 415032 A7 -------- B7 __ V. Description of the invention () After forming the trench opening 235 behind the second insulating layer 240, In the phase deposition method, a metal layer 160 is deposited on the substrate 210, the vias 235 and the trench openings 23 are filled with the metal 160, and the substrate is subjected to chemical mechanical polishing (CMP) until the second insulating layer 240 is formed on the substrate 210. Up to the surface, the surface of the metal substrate is inlaid and used for further processing after planarization. In summary, the manufacturing method provided by the present invention is used to form the openings of the vias and trenches. Selection of different etchants to achieve a dual damascene structure without etch stop layer (RC-delay) and improve the reliability of the circuit 'and simplify the traditional process steps to save process costs. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application. II ------ I (Please read the precautions on the back before filling in this purchase) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs for consumer cooperation