3442t\vf.doc/008 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（I ) 本發明是有關於一種積體電路中多重內連線 (Mu丨tilevel Interconnects)的製造方法，且特別是有關於 一種雙重金屬鑲嵌（Dual Damascene)的製造方法。 傳統的內連線作法是在用以隔離金屬層的絕緣層上， 例如氧化矽層，沈積一層金屬層後，再將金屬層定義出預 定的導線圖案，繼之使導線層之間形成一垂直連接窗口。 然後於窗口中塡入與導電層相同材質或不同材質的金 屬，用以完成導線層的垂直連接。値得重視的是，隨著積 體電路中所需導線層數目的增加，兩層以上的金屬層設 計，便逐漸的成爲許多積體電路所必需採用的方式。在金 屬層之間常以內金屬介電層（Inter-Metal Dielectrics; IMD)加以隔離，其中用來連接上下兩層金屬層的導線， 在半導體工業上，稱之爲介層窗（Via)。 習知製造介層窗和內連線的方法有兩種，其中一種是 介層窗和內連線分兩步驟完成，即先在金屬層上方形成介 電層，接著在介電層上方定義光阻（Photoresist)層，然 後利用鈾刻技術完成介層窗，並利用沈積法在此介層窗沈 積導電材料以完成介層窗的製做，之後沈積金屬層，並定 義金屬層，最後再沈積內金屬介電層。 另一種是雙重金屬鑲嵌的技術，是一種介層窗內連 線同時形成的技術。 ^ 雙重金屬鑲嵌的製程係在基底結構上先形成一絕緣 層，並將其平坦化後，再依照所需之金屬導線的圖案和介 層窗開口的位置，蝕刻絕緣層以形成一水平溝渠和一垂直 介層窗開口，亦即蝕刻上層絕緣層，而形成一水平溝渠， 請 先 閲 背 意： 事 項 再- 填 寫 本 頁 訂 線 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 經濟部中央標準局員工消費合作社印製 A7 3442twf.doc/008 B7 五、發明説明（2 ) 並且蝕刻下層絕緣層至暴露出其下方之元件區或導線，以 形成一垂直介層窗開口。然後，於基底結構上沈積一金屬 層，使其塡滿水平溝渠與垂直介層窗開口，以.同時形成金 屬線與介層窗。最後，以化學機械硏磨法（Chemical-Mechanical Polishing ; CMP) 將元件的表面平坦化 ，並再 進行另一個雙重金屬鑲嵌結構的形成，亦即水平溝渠與垂 直介層窗開口的金屬鑲嵌即爲一雙重金屬鑲嵌製程。 第1A圖至第1G圖係繪示傳統式雙重金屬鑲嵌之製造 流程的剖面示意圖。 請參照第1A圖，首先提供具有一平坦表面的基底結 構100，其中基底100的元件，並沒有完全被繪出。圖示 中的導電區102可以是電晶體元件的源極/汲極區，也可以 是閘極結構的金屬層或內連線的金屬層。先於基底1 〇〇上 依序形成內金屬介電層104和餓刻終止層106，其中介電 層104的材質例如是二氧化矽。蝕刻終止層106的材質例 如是氮化矽，厚度約爲1〇〇〇埃至2000埃。之後，再於蝕 刻終止層106上方形成一已定義圖案的光阻層108，此光 阻層108暴露出欲形成介層窗開口的區域。 '請參照第1B圖，以此光阻層108爲罩幕，進行鈾刻 終止層106的乾蝕刻製程，在蝕刻終止層106a中形成開口 107，以暴露出位於其下方的介電層104。之後，再將光阻 層108剝除。 請參照第1C圖，於基底100上形成另一內金屬介電 層114，例如以化學氣相沈積法，且覆蓋蝕刻終止層106a 和部份的介電層104。 _____ 4__ 本紙張尺度適用中國國家標準(匸阳）八4規格（210><297公釐） I--------(------訂------線' (請先閱讀背面之注4-事項#-填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 3442twf.doc/〇〇8 B7 五、發明説明（々） 然後，請參照第ID圖，於內金屬介電層114上形成 另一已定義圖案的光阻層118，此光阻層118暴露出介電 層Π4中欲形成內連線溝渠的部份。 請參照第1E圖，以光阻層118爲罩幕，利用高Si02/SiN 鈾刻選擇比之乾蝕刻（Dry Etching)法，分別對內金屬介 電層（第1D圖中的內金屬介電層114)之欲形成溝渠處進 行蝕刻，而形成內連線溝渠120a與內連線溝渠122，且在 內金屬介電層l〇4a中形成介層窗開口 120b，同時暴露出 部分的蝕刻終止層106a，以及暴露出部分的導電區102。 由於有鈾刻終止層106a的存在，所以在進行介電層l〇4a 高Si02/SiN蝕刻選擇比的蝕刻步驟後，可以形成雙重金屬 镶嵌結構的開口 120。 請參照第1F圖，'剝除光阻層11·8。之後沈積一層與介 層窗開口 120b、內連線溝渠120a和內連線溝渠122側壁 共形的（Conformal)黏著/阻障層（Glue/Barrier Layer) 124，以增加隨後沈積的金屬層與其他材質的附著能力。 爾後，於介層窗開口 120b、內連線溝渠120a和內連線溝 渠122中，以及內余屬介電層IMa上沈積一層金屬層，再 經化學機械硏磨法（CMP)，直到暴露出內金屬介電層 114a，並且分別在雙重金屬鑲嵌結構的開口 120和內連線 溝渠122中形成金屬層126和金屬層128，進而完成雙重 金屬鑲嵌製程。 請參照第1G圖，由於雙重金屬鑲嵌開口 120的輪廓， 係由用以定義雙重金屬鑲嵌結構的光阻層，以及定義有開 口圖案的餽刻終止層106a決定，因此，一旦光罩在對準時 ____5__ 本紙張尺度適用中國國家;^準（CNS ) A4現格(210^297公Ϊ"! 一 " (請先閲讀背面之注意事項I填寫本頁)3442t \ vf.doc / 008 A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (I) The present invention relates to a method for manufacturing multiple interconnects (Mu 丨 level interconnects) in integrated circuits. In particular, it relates to a manufacturing method of dual metal damascene. The traditional method of interconnecting wires is to deposit a metal layer on an insulating layer used to isolate a metal layer, such as a silicon oxide layer, and then define the metal layer to define a predetermined wire pattern, and then form a vertical line between the wire layers. Connection window. Then insert a metal of the same material or a different material from the conductive layer into the window to complete the vertical connection of the wire layer. It is important to note that with the increase in the number of conductor layers required in integrated circuits, the design of two or more metal layers has gradually become a necessary method for many integrated circuits. Intermetallic layers (IMD) are often used to isolate metal layers. The wires used to connect the upper and lower metal layers are called vias in the semiconductor industry. There are two known methods for manufacturing dielectric windows and interconnects. One of them is to complete the dielectric window and interconnect in two steps. First, a dielectric layer is formed above the metal layer, and then the light is defined above the dielectric layer. Resist (Photoresist) layer, and then use uranium etching technology to complete the interstitial window, and use the deposition method to deposit conductive materials on this interstitial window to complete the fabrication of the interstitial window, then deposit a metal layer, define the metal layer, and then deposit Inner metal dielectric layer. The other is the double metal damascene technology, which is a technology that simultaneously forms the interconnects in the interlayer window. ^ The process of double metal damascene is to first form an insulating layer on the base structure and flatten it, and then etch the insulating layer to form a horizontal trench and A vertical interstitial window opening, that is, an upper insulating layer is etched to form a horizontal trench. Please read the following: Matters before-Fill in this page to make a line. This paper applies the Chinese National Standard (CNS) A4 specification (210 X 297). Printed by A7 3442twf.doc / 008 B7 of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (2) and etching the lower insulating layer to expose the component area or wires below it to form a vertical interlayer window Opening. Then, a metal layer is deposited on the base structure so that it fills the horizontal trenches and the openings of the vertical vias to form metal lines and vias at the same time. Finally, chemical-mechanical polishing (CMP) is used to planarize the surface of the element, and then another double metal damascene structure is formed, that is, the metal damascene of the horizontal trench and the vertical interstitial window opening is A double metal inlay process. Figures 1A to 1G are schematic cross-sectional views showing the manufacturing process of a conventional double metal inlay. Referring to FIG. 1A, a base structure 100 having a flat surface is first provided, and the components of the base 100 are not completely drawn. The conductive region 102 in the figure may be a source / drain region of a transistor element, or a metal layer of a gate structure or a metal layer of an interconnect. The inner metal dielectric layer 104 and the etch stop layer 106 are sequentially formed on the substrate 100, and the material of the dielectric layer 104 is, for example, silicon dioxide. The material of the etch stop layer 106 is, for example, silicon nitride, and has a thickness of about 1,000 to 2000 angstroms. Then, a photoresist layer 108 having a defined pattern is formed over the etch stop layer 106, and the photoresist layer 108 exposes the area where the opening of the interlayer window is to be formed. 'Please refer to FIG. 1B. Using the photoresist layer 108 as a mask, a dry etching process of the uranium etch stop layer 106 is performed, and an opening 107 is formed in the etch stop layer 106a to expose the dielectric layer 104 below it. After that, the photoresist layer 108 is stripped again. Referring to FIG. 1C, another inner metal dielectric layer 114 is formed on the substrate 100, for example, by chemical vapor deposition, and covers the etch stop layer 106a and a portion of the dielectric layer 104. _____ 4__ This paper size is applicable to China National Standard (Liyang) 8 4 specifications (210 > < 297 mm) I -------- (------ Order ------ Line ' (Please read Note 4- Matter # -Fill this page on the back first) Printed by A7 3442twf.doc / 〇〇8 B7 of the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (々) Then, please refer to Figure ID, A photoresist layer 118 having another defined pattern is formed on the inner metal dielectric layer 114, and this photoresist layer 118 exposes the portion of the dielectric layer Π4 where the interconnecting trenches are to be formed. Please refer to FIG. 1E. The resist layer 118 is a cover screen, and a trench is formed on the inner metal dielectric layer (the inner metal dielectric layer 114 in FIG. 1D) by using a dry etching method (Dry Etching) with a high Si02 / SiN uranium etching ratio. Etching is performed to form interconnecting trenches 120a and interconnecting trenches 122, and an interlayer window opening 120b is formed in the inner metal dielectric layer 104a, while exposing a part of the etch stop layer 106a, and exposing part of the Conductive region 102. Due to the presence of the uranium etch stop layer 106a, after performing the etching step of the dielectric layer 104a with a high Si02 / SiN etching selectivity ratio, the In order to form a double metal damascene structure opening 120, please refer to FIG. 1F, 'peel off the photoresist layer 11.8. Then deposit a layer conformal to the sidewall of the via 120b, interconnect trench 120a, and interconnect trench 122 side wall. (Conformal) Glue / Barrier Layer 124 to increase the adhesion of subsequently deposited metal layers to other materials. Then, in the interlayer window opening 120b, interconnecting trench 120a and interconnecting trench In 122, a metal layer is deposited on the inner residual dielectric layer IMa, and then chemical mechanical honing (CMP) is performed until the inner metal dielectric layer 114a is exposed, and is located in the opening 120 and the inner portion of the dual metal damascene structure, respectively. A metal layer 126 and a metal layer 128 are formed in the connection trench 122 to complete the dual metal damascene process. Please refer to FIG. 1G, because the contour of the dual metal damascene opening 120 is a photoresist layer used to define the dual metal damascene structure, And the feed-stop layer 106a that defines the opening pattern is determined, so once the photomask is aligned ____5__ This paper size applies to the Chinese country; ^ 准 (CNS) A4 is now (210 ^ 297 public Ϊ "! ONE " (Please read the notes on the back I fill out this page)
A7 B7 3442twf.doc/008 五、發明説明（κ) 發生對準失誤（Misalignment)，將使得雙重金屬鑲嵌開 □ 120’其中的介層窗開口 i2〇b，的開口大小減小 (Shdnk) ’其在塡入金屬層之後所形成的介層窗126’與 導電;層102的接觸面積亦將因而縮小，而導致接觸電阻値 的增加。 '綜上所述，習知之雙重金屬鑲嵌製程的缺點至少包 括： 需要沈積二次的內金屬介電層（IMD)，且至少需要 多沈積一層以上的蝕刻終止層，因此習知的製程需要進行 多次的沈積步驟，故習知之製程較費時且成本較高。 做爲蝕刻終止層之氮化矽層不但具有較氧化矽材質爲 高的介電常數，易造成較高的身生電容，而且氮化矽與內 金屬介電層（如氧化矽）之應力（Stress)差異甚大，且爲 相反的應力，亦即氮化矽爲伸張（Tensile)應力，而氧化 砂爲壓縮（Compressive )應力，在筆續的高溫金屬製程中， 會導致鈾刻終止層與介電層相接觸之側壁角落（Sidewall Comer)產生龜裂或斜離的現象，甚至造成基底的彎曲變 形，使得後續的製程產生問題。 以習知的方法在進行雙重金屬鑲嵌開口的定義時，一 旦光罩在對準時發生對準失誤，將使得雙重金屬鑲嵌開口 中之介層窗開口的寬度減小，其在塡入金屬層之後所形成 的金屬層與下層導電區的接觸面積亦將因而縮小，而導致 接觸電阻値的增加。 有鑑於此，本發明的主要目的就是在提供一種雙重金 屬鑲嵌的製造方法，只需沈積一層內金屬介電層，並利用 6 ______ (請先閲讀背面之注^事項再填寫本頁) f.... 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） A7 B7 五 ._一_I_I_ 經濟部中央標率局員Η消費合作社印製 3442twf.doc/008 發明説明（t) 離子植入（Ion implantation)歩驟以改變內金屬介電層的 蝕刻速率，進而控制內金屬介電層或內層介電層（Inter_ Layer Dielectrics ; ILD)的飩刻深度，並且只進行一次的 蝕刻步驟，以達成雙重金屬鑲嵌的製程，故本發明之雙重 金屬鑲嵌的製造方法較習知簡單。本發明又因爲沒有蝕刻 /終止層的存在’所以假使在定義雙重金屬鑲嵌開口時發生 對準失誤，不會造成如習知之介層窗開口的寬度減小的缺 點。另外，本發明之雙重金屬鑲嵌開口中的溝渠和介層窗 開口’係在一次蝕刻步驟中同時完成，所以溝渠和介層窗 開口具有自行對準（Self-aligned)的特性。 根據本發明的主要目的，提出一種雙重金屬鑲嵌的製 造方法，包括.在具有一導電區的基底上形成一·介電層。 之後，進行一離子植入步驟，用以在對應於導電區上方的 介電層中形成一摻雜區，進而使摻雜區的蝕刻速率較摻雜 區以外之介電層的部份快。接著，蝕刻摻雜區和部份的介 電層’直到暴露出導電層，進而在介電層中形成一雙重金 屬鑲嵌開口。然後’在雙重金屬鑲嵌開口的導線溝渠和介 層窗開口中形成一金屬層，以完成雙重金屬鑲嵌製程。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： . 圖式之簡單說明·- 第1A圖至第1G圖係繪示傳統式雙重金屬鑲嵌之製造 流程的剖面示意圖；以及 第2A圖至第2E圖係繪示根據本發明之一較佳實施 本紙張尺度適用中國國家榡準（CNs ) Α4規格（210X297公釐〉 請 先 閲 讀 背A7 B7 3442twf.doc / 008 V. Explanation of the invention (κ) Misalignment will cause the double metal inlaid opening 120 ', the interstitial window opening i2〇b, and the opening size will be reduced (Shdnk)' The contact area of the interlayer window 126 'formed after the metal layer is inserted into the metal layer is conductive, and the contact area of the layer 102 will also be reduced, resulting in an increase in contact resistance 値. 'In summary, the shortcomings of the conventional dual metal damascene process include at least: the need to deposit a second internal metal dielectric layer (IMD), and at least one more etch stop layer needs to be deposited, so the conventional process needs to be performed With multiple deposition steps, the conventional process is time consuming and costly. The silicon nitride layer used as the etch stop layer not only has a higher dielectric constant than the silicon oxide material, which tends to cause a higher physical capacitance, but also the stress of the silicon nitride and the inner metal dielectric layer (such as silicon oxide) ( Stress is very different, and it is the opposite stress, that is, silicon nitride is Tensile stress, and sand oxide is Compressive stress. In the continuous high-temperature metal process, it will cause the uranium etch stop layer and the dielectric. Sidewall corners (Sidewall Comer) where the electrical layers are in contact can cause cracking or oblique separation, and even cause bending and deformation of the substrate, which causes problems in subsequent processes. When using a conventional method to define the double metal inlaid opening, once the photomask is misaligned during alignment, the width of the interstitial window opening in the double metal inlaid opening will be reduced. The contact area between the formed metal layer and the lower conductive region will also be reduced, resulting in an increase in contact resistance 値. In view of this, the main purpose of the present invention is to provide a method for manufacturing a dual metal damascene, which only needs to deposit an inner metal dielectric layer and use 6 ______ (please read the notes on the back before filling this page) f. ... Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and Consumer Cooperatives This paper is printed in accordance with the Chinese National Standard (CNS) A4 (210X297 mm) A7 B7 V._ 一 _I_I_ Printed by the Central Coordination Bureau of the Ministry of Economic Affairs and printed by Consumer Cooperative 3442twf.doc / 008 Description of the Invention (t) Ion implantation step to change the etching rate of the inner metal dielectric layer, and then control the inner metal dielectric layer or the inter-layer dielectric layer (ILD) The engraving depth is only 1 and the etching step is performed only once to achieve the double metal damascene process. Therefore, the manufacturing method of the double metal damascene of the present invention is simpler than conventional. In the present invention, because there is no etch / stop layer ', if the misalignment occurs when defining the double metal damascene opening, it will not cause the defect that the width of the via window opening is reduced as is known in the art. In addition, the trench and via window openings in the dual metal inlaid openings of the present invention are completed simultaneously in one etching step, so the trench and via window openings have a self-aligned characteristic. According to the main object of the present invention, a method for manufacturing a dual metal damascene is proposed, which includes forming a dielectric layer on a substrate having a conductive region. Then, an ion implantation step is performed to form a doped region in the dielectric layer corresponding to the conductive region, so that the etching rate of the doped region is faster than that of the dielectric layer outside the doped region. Next, the doped region and a portion of the dielectric layer are etched until the conductive layer is exposed, and a double metal damascene opening is formed in the dielectric layer. Then, a metal layer is formed in the wire trench of the double metal damascene opening and the opening of the interlayer window to complete the double metal damascene process. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below in conjunction with the accompanying drawings, which are described in detail as follows: Figures 1A to 1G are schematic cross-sectional views showing the manufacturing process of a traditional dual metal inlay; and Figures 2A to 2E are drawings showing the preferred implementation of this paper according to one of the present invention. ) Α4 size (210X297mm) Please read the back first
事 項 再-填 I r 頁 I 訂 A7 B7 3442twf.doc/008 五、發明説明（6 ) 例，一種雙重金屬鑲嵌之製造流程的剖面示意圖。 圖式之標記說明：雙重金屬鑲嵌的製造方法 100, 200 基底 102, 202 導電區 104, 104a, 1 14, 204, 204a 介電層 106, 1 06a 餓刻終止層 107, 207, 217a, 217b 開口 108, 1 18, 208, 218 光阻層 120, 120’，220 雙重金屬鑲嵌結構的開口 120a，120a’，122, 122’，220a，222 內連線溝渠 120b, 120b’，220b 介層窗開口 124, 124’，224 黏著/阻障層 126, 126’，128, 128’，226, 228 金屬層 212 摻雜區 實施例 第2A圖至第2E圖係繪示根據本發明之一較佳實施 例，一種雙重金屬鑲嵌之製造流程的剖面示意圖。 請參照第2A圖，首先提供具有一平坦表面的基底結 構200，其中基底200的元件並沒有完全被繪出。圖示中 的導電區202可以是電晶體元件的源極/汲極區，也可以是 閘極結構的金屬層或內連線的金屬層。先於基底200上形 成內金屬介電層204，介電層204例如以化學氣相沈積法 (CVD )沈積的氧化矽層，或是以矽酸四乙酯（Tetra-ethyl-ortho-silicate ; TEOS)爲氣體源，較佳爲使用化學氣 相沈積法（CVD)或電漿增強化學氣相沈積法（Plasma 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 請 先 閲 4. 背 ιέ 之 注 1 Γ 訂 線 經濟部中央標準局員工消費合作社印製 經濟部中央標準局員工消費合作社印製 A7 3 4 4 21 wf. d 〇 c/〇 Ο 8 B7 五、發明説明（0 )Event Re-fill I r page I order A7 B7 3442twf.doc / 008 V. Description of the invention (6) Example, a cross-sectional schematic diagram of the manufacturing process of a double metal inlay. Description of the drawing marks: Manufacturing method of double metal inlays 100, 200 substrates 102, 202 conductive regions 104, 104a, 1 14, 204, 204a dielectric layers 106, 1 06a etch stop layers 107, 207, 217a, 217b openings 108, 1 18, 208, 218 Photoresist layer 120, 120 ', 220 openings of double metal damascene structure 120a, 120a', 122, 122 ', 220a, 222 interconnecting trenches 120b, 120b', 220b openings for interlayer windows 124, 124 ', 224 Adhesive / barrier layers 126, 126', 128, 128 ', 226, 228 Metal layer 212 Example of doped regions Figures 2A to 2E show a preferred implementation according to the present invention Example, a schematic cross-sectional view of the manufacturing process of a dual metal inlay. Referring to FIG. 2A, a base structure 200 having a flat surface is first provided, in which components of the base 200 are not completely drawn. The conductive region 202 in the figure may be a source / drain region of a transistor element, or a metal layer of a gate structure or a metal layer of an interconnect. First, an inner metal dielectric layer 204 is formed on the substrate 200. The dielectric layer 204 is, for example, a silicon oxide layer deposited by a chemical vapor deposition (CVD) method, or is a tetraethyl ethyl silicate (Tetra-ethyl-ortho-silicate); TEOS) is a gas source, preferably using chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (Plasma) This paper is sized for China National Standard (CNS) A4 (210X 297 mm). Please read 4. Backnote 1 Γ Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Printed by A7 3 4 4 21 wf. D 〇c / 〇〇 8 B7 V. Description of the invention ( 0)
Enhanced Chemical Vapor Deposition ; PECVD)沈積的氧 化矽層。之後，進行介電層204的平坦化步驟，例如以化 學機械硏磨法（CMP)，藉以平坦化介電層204的表面， 直到介電層2〇4的厚度約與後續形成之介層窗開口和溝渠 的高度總和相當。 請參照第2B圖，於介電層204上方形成一已定義圖 案的光阻層208，此光阻層208具有開口 207，而開口 207 暴露出介電層204中欲形成雙重金屬鑲嵌之介層窗開口的 區域，且開口 207的寬度約與雙重金屬鑲嵌之介層窗開口 的寬度相當。 之後，利用離子植入步驟（如圖中所示之箭號210)， 在內金屬介電層204中，且對應於導電區202的上方形成 摻雜區212，用以改變介電層204中摻雜區212的蝕刻速 率，進而控制介電層204的鈾刻深度，由於開口 207的寬 度約與雙重金屬鑲嵌之介層窗開口的寬度相當，所以摻雜 區212的寬度約與雙重金屬鑲嵌之介層窗開口的寬度相 當。此步驟較佳的是在光阻層208之開口 207所暴露出的 介電層204的區域中，以氬離子（Ar+)做爲摻雜離子，進 行離子植入步驟，其中離子植入的能量約爲70KeV，離子 植入的劑量約爲1.0xl014/cm2，摻雜區212之離子植入的 深度假設爲h。在此離子植入劑焉的條件下，介電層.2〇4 中進行離子植入區域之蝕刻速率約爲未進行離子植入區域 的2倍，因此在後續進行介電層2〇4的蝕刻步驟時，摻雜 區212的蝕刻速率約爲摻雜區212以外之介電層204的部 份（即介電層204中未進行離子植入區域）的2倍。接著， ____ 9_ 本紙張尺度適用中國國家標準（CNS M4規格（210X 297公釐） (請先閱讀背面之注^事項再填寫本頁) r''v 訂 -線' A7 B7 3442twf.doc/008 五、發明説明（δ ) 去除光阻層208。 接著請參照第2C圖，於介電層2〇4上方形成一已定義 圖案的光阻層218 ’此光阻層218具有開口 217a和開口 2^7b，其中開口 2na暴露出介電層2〇4中欲形成雙重金屬 鑲嵌之內連線溝渠的區域，此區域同時包含了摻雜區212 和部份的介電層204,且開口 217a的寬度約與雙重金屬鑲 欣之內連線溝渠的寬度相當，而開口 217t)則暴露出介電 層2〇4中欲形成另一內連線溝渠的區域。 接著請參照第2D圖，以光阻層218爲罩幕，進行介電 層2〇4的蝕刻製程，例如以非等向性蝕刻法，在介電層2〇4a 中形成雙重金屬鑲嵌開口 220和內連線溝渠222，直到雙 重金屬鑲嵌開口 220暴露出位於其下方的導電區202。接 著’再將光阻層218剝除。由於光阻層218的開口 217a 同時暴露出摻雜區212與其外圍之部份的介電層204 (請 同時參照第2C圖），而且又因爲摻雜區212的蝕刻速率 大於其外圍之介電層204，所以在進行蝕刻步驟之後，可 以形成上寬下窄型的雙重金屬鑲嵌開口 22〇,而雙重金屬 鑲嵌開口 220包括內連線溝渠220a和介層窗開口 22〇b。 假設摻雜區2U之離子植入的深度爲h (如第2C圖所 示）’雙重金屬鑲嵌開口 22〇中介層窗開口 22〇b的深产 爲H ’內連線溝渠222的深度爲d ’而摻雜區2U相對二 其餘未進行離子植入之介電層2〇4部份的蝕刻速率爲^ : 則由蝕刻雙重金屬鑲嵌開口 2 2 〇的時間與蝕刻內連線溝泡 222的時間相等，可以推出關係式： a 本紙張尺度適用中國國家標準（CNS ) Μ規格（210X297公釐） I'^vl II 訂— n » (請先閲讀背面之注^事項#填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 3442twf.doc/0〇8 五、發明説明π ) h , (H+d)-h _ dEnhanced Chemical Vapor Deposition; PECVD). Then, a planarization step of the dielectric layer 204 is performed, for example, a chemical mechanical honing method (CMP) is used to planarize the surface of the dielectric layer 204 until the thickness of the dielectric layer 204 is approximately the same as that of a subsequently formed dielectric window. The sum of the heights of the openings and trenches is comparable. Referring to FIG. 2B, a photoresist layer 208 having a defined pattern is formed over the dielectric layer 204. The photoresist layer 208 has an opening 207, and the opening 207 exposes the dielectric layer in the dielectric layer 204 to form a double metal inlay. The area of the window opening, and the width of the opening 207 is approximately the same as the width of the double metal inlaid interlayer window opening. After that, an ion implantation step (arrow 210 shown in the figure) is used to form a doped region 212 in the inner metal dielectric layer 204 and corresponding to the conductive region 202 to change the dielectric layer 204. The etching rate of the doped region 212 further controls the uranium etch depth of the dielectric layer 204. Since the width of the opening 207 is approximately the same as the width of the double metal damascene window opening, the width of the doped region 212 is approximately the same as the double metal damascene The width of the interstitial window openings is comparable. This step is preferably performed in the region of the dielectric layer 204 exposed by the opening 207 of the photoresist layer 208 with argon ions (Ar +) as doping ions, in which the energy of ion implantation is performed. It is about 70KeV, the dose of ion implantation is about 1.0xl014 / cm2, and the depth of ion implantation in the doped region 212 is assumed to be h. Under the conditions of this ion implantation agent, the etching rate of the ion implanted area in the dielectric layer .204 is about twice that of the area where the ion implantation is not performed. Therefore, the dielectric layer During the etching step, the etching rate of the doped region 212 is about twice the portion of the dielectric layer 204 (that is, the region where the ion implantation is not performed in the dielectric layer 204) outside the doped region 212. Then, ____ 9_ This paper size applies to Chinese national standards (CNS M4 specification (210X 297 mm) (please read the notes on the back before filling out this page) r'v order-line 'A7 B7 3442twf.doc / 008 V. Description of the invention (δ) Remove the photoresist layer 208. Next, referring to FIG. 2C, a photoresist layer 218 having a defined pattern is formed over the dielectric layer 204. The photoresist layer 218 has an opening 217a and an opening 2 ^ 7b, where the opening 2na exposes the area of the dielectric layer 204 where a double metal damascene interconnect trench is to be formed. This area contains both the doped region 212 and a portion of the dielectric layer 204, and the opening 217a The width is about the same as the width of the interconnecting trench of the double metal insert, and the opening 217t) exposes the area in the dielectric layer 204 where another interconnecting trench is to be formed. Next, referring to FIG. 2D, the photoresist layer 218 is used as a mask to perform an etching process of the dielectric layer 204. For example, by using an anisotropic etching method, a double metal inlaid opening 220 is formed in the dielectric layer 204a. And interconnect the trench 222 until the double metal damascene opening 220 exposes the conductive region 202 below it. Next, the photoresist layer 218 is peeled off. The opening 217a of the photoresist layer 218 simultaneously exposes the doped region 212 and the dielectric layer 204 of the periphery thereof (please refer to FIG. 2C at the same time), and because the etching rate of the doped region 212 is greater than the dielectric of the periphery thereof Layer 204, so that after the etching step is performed, a double metal damascene opening 22 with a wide upper and a narrow shape can be formed, and the double metal damascene opening 220 includes an interconnecting trench 220a and a via window 22b. Assume that the depth of the ion implantation in the doped region 2U is h (as shown in FIG. 2C). The depth of the double metal damascene opening 22 and the interposer window opening 22b is H. The depth of the interconnecting trench 222 is d. 'And the etching rate of the doped region 2U relative to the other two portions of the dielectric layer 204 which have not been ion implanted is ^: the time of etching the double metal damascene opening 2 2 0 and the etching of the interconnecting trench 222 Equal time, you can introduce the relationship: a This paper size applies the Chinese National Standard (CNS) M specifications (210X297 mm) I '^ vl II Order — n »(Please read the note on the back ^ Matters #Fill this page) Economy Printed by A7 B7 3442twf.doc / 0〇8, the Consumer Cooperatives of the Ministry of Standards of the People's Republic of China V. Description of Invention π) h, (H + d) -h _ d
R +—~Ϊ— T 經整理之後可得： h = iH (1) R -1 所以前述摻雜區212之離子植入的深度h，可以由式（1) 來決定’亦即由摻雜區212相對於其餘未進行離子植入之 介電層2〇4部份的蝕刻速率R，以及雙重金屬鑲嵌開口 22〇 中介層窗開口 22〇b的深度η來決定。 請參照第2Ε圖，在基底200上沈積一層與介層窗開 口 220b、內連線溝渠220a和內連線溝渠222側壁共形的 黏著/阻障層224，例如是鈦/氮化鈦（Ti/TiN)、钽/氮化 鉬（Ta/TaN)等的導電材料，以增加隨後沈積的金屬層與 其他材質的附著能力。爾後，於介層窗開口 220b、內連線 溝渠210a和內連線溝渠222中，以及內金屬介電層204a 上沈積一層金屬層，例如是銅、鋁、鋁銅合金等的金屬材 料’再經化學機械硏磨法（CMP)，直到暴露出內金屬介 電層204a’並且分別在雙重金屬鑲嵌結構的開口 22〇和內 連線溝渠222中形成金屬層226和金屬層228，進而完成 雙重金屬鑲嵌製程。 綜上所述，本發明的特徵在於： 1. 本發明利用離子植入步驟以改變內金屬介電層的 蝕刻速率，進而控制內金屬介電層（IMD)或內層介電層 (ILD)的蝕刻深度，以達成雙重金屬鑲嵌的製程，故本 發明之雙重金屬鑲嵌的製造方法較習知簡單。 2. 本發明只需沈積一層內金屬介電層，且只進行一次 本纸張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） f) (請先閲讀背面之注t事項再填寫本頁) --° Γ 經濟部中央標準局貝工消費合作社印製 A7 A7 3442twf.doc/0 08 B7 五、發明説明（丨 的鈾刻步驟，而本發明又因爲沒有蝕刻終止層的存在，所 以假使在定義雙重金屬鑲嵌開口時發生對準失誤，不會造 成如習知之介層窗開口的寬度減小的缺點。 3. 本發明之雙重金屬鑲嵌開口中的溝渠和介層窗開 口，係在一次蝕刻步驟中同時完成，所以溝渠和介層窗開 口具有自行對準的特性。 4. 本發明的製程均與現有的製程相容，極適合廠商的 生產安排。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 ----------r'、------ΐτ------手· (請先閱讀背面之注*·'事項#·填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（匚奶）人4規格（210><297公釐）R + — ~ Ϊ— T can be obtained after finishing: h = iH (1) R -1 So the depth of ion implantation h of the aforementioned doped region 212 can be determined by formula (1), that is, by doping The etch rate R of the region 212 with respect to the rest of the dielectric layer 204 that has not been ion implanted, and the depth η of the double metal damascene opening 22o and the interposer window opening 22ob are determined. Referring to FIG. 2E, an adhesive / barrier layer 224 conforming to the sidewalls of the via window opening 220b, the interconnector trench 220a, and the interconnector trench 222 is deposited on the substrate 200, such as titanium / titanium nitride (Ti / TiN), tantalum / molybdenum nitride (Ta / TaN) and other conductive materials to increase the adhesion of subsequently deposited metal layers to other materials. Thereafter, a metal layer, such as a metal material such as copper, aluminum, aluminum-copper alloy, is deposited on the interlayer window opening 220b, the interconnecting trenches 210a and interconnecting trenches 222, and the interconnecting metal dielectric layer 204a. After chemical mechanical honing (CMP), until the inner metal dielectric layer 204a 'is exposed and a metal layer 226 and a metal layer 228 are formed in the opening 22o of the dual metal damascene structure and the interconnecting trenches 222, respectively, the double layer is completed. Heavy metal inlaying process. In summary, the present invention is characterized by: 1. The present invention utilizes an ion implantation step to change the etching rate of the inner metal dielectric layer, thereby controlling the inner metal dielectric layer (IMD) or the inner dielectric layer (ILD). To achieve a double metal damascene process, the manufacturing method of the double metal damashes of the present invention is simpler than conventional. 2. The present invention only needs to deposit an inner metal dielectric layer, and it is carried out only once. The paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297 mm) f) (Please read the note on the back before filling in (This page)-° Γ Printed by the Central Standards Bureau of the Ministry of Economy, Shellfish Consumer Cooperative, printed A7 A7 3442twf.doc / 0 08 B7 V. Description of the invention (Uranium engraving step, and the present invention is because there is no etching stop layer, Therefore, if misalignment occurs when defining the double metal inlaid opening, the disadvantage of reducing the width of the interstitial window opening as in the conventional one will not be caused. 3. The trenches and interstitial window openings in the double metal inlaid opening of the present invention are related to It is completed in one etching step at the same time, so the trench and the interstitial window openings have the characteristics of self-alignment. 4. The process of the present invention is compatible with the existing process and is very suitable for the manufacturer's production arrangement. Although the present invention has been compared with The preferred embodiment is disclosed as above, but it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. ---------- r '、 ------ ΐτ ------ hand · (Please read the Note * · 'Item # · Fill in this page) The paper size printed by the Employees' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs applies to the Chinese National Standard (Milk) Person 4 Specification (210 > < 297 mm)