32 1 9twfl /005 Μ B7 五、發明説明（丨） 本發明是有關於一種介層窗（Via)的製造方法，且特 別是有關於一種未接著介層窗（Unlanded Via)的製造方 法。 隨著積體電路中所需導線層數目的增加，兩層以上的 金屬層設計，便逐漸的成爲許多積體電路所必需採用的方 式。在金屬層之間常以內金屬介電層（Inter-Metal Dielectric ; IMD)力口以隔離，其中用來連接上下兩層金屬 層的導線，在半導體工業上即稱之爲介層窗。 傳統的內連線製作方法是在用以隔離金屬層的絕緣層 上’例如氧化矽層，沈積一層金屬層後，再將金屬層定義 出預定的導線圖案，繼之使導線層之間形成一垂直連接的 介層窗。然後於介層窗開口中塡入與導電層相同材質或不 同材質的金屬，用以完成導線層的垂直連接。 習知製造介層窗和內連線的方法，通常是介層窗和內 連線分兩步驟完成，即在金屬層上方形成介電層，之後在 介電層上方定義光阻（Photoresist)層，然後利用蝕刻技 術完成介層窗開口，並利用沈積法在此介層窗開口中沈積 導電材料以完成介層窗的製做，之後沈積金屬層，並定義 金屬層，最後再沈積內金屬介電層（IMD)。 然而，隨著半導體製程線寬的減小與積集度的增加， 相對的在定義介電層以形成介層窗開口時，習知的方法易 因過度蝕刻的控制不當，而造成介層窗開口深入於導線層 下層的絕緣層中，甚至達導線層下層的另一導電區，在後 續形成介層窗插塞後，此插塞會與導線層下層之絕緣靥中 3 本紙乐尺度適用中國國家標準（CNS ) A4規格（210X297&i ) ' ' (請先閲讀背面之注意事項再填寫本頁) 裝_32 1 9twfl / 005 Μ B7 V. Description of the Invention (丨) The present invention relates to a method for manufacturing an interlayer window (Via), and particularly to a method for manufacturing an unlanded via (Unlanded Via). With the increase in the number of conductor layers required in integrated circuits, the design of two or more metal layers has gradually become a necessary method for many integrated circuits. Intermetallic layers (Inter-Metal Dielectric; IMD) are often used for isolation between the metal layers. The wires used to connect the upper and lower metal layers are called dielectric windows in the semiconductor industry. The traditional method of making interconnects is to deposit a metal layer on an insulating layer used to isolate the metal layer, such as a silicon oxide layer, and then define the metal layer to define a predetermined wire pattern, and then form a wire pattern between the wire layers. Vertically connected vias. Then insert a metal of the same material or a different material from the conductive layer into the opening of the via window to complete the vertical connection of the wire layer. Known methods for manufacturing dielectric windows and interconnects are usually completed in two steps, that is, forming a dielectric layer above the metal layer, and then defining a photoresist layer above the dielectric layer , And then use an etching technique to complete the opening of the interposer, and use a deposition method to deposit a conductive material in the opening of the interposer to complete the fabrication of the interposer, then deposit a metal layer, define the metal layer, and finally deposit the inner metal interposer. Electrical layer (IMD). However, with the decrease of the semiconductor process line width and the increase of the accumulation degree, when defining the dielectric layer to form the opening of the dielectric window, the conventional method is apt to cause the interlayer window due to improper control of over-etching. The opening penetrates deep into the insulation layer below the wire layer, and even reaches another conductive area under the wire layer. After the subsequent formation of the via window plug, this plug will be in contact with the insulation of the lower layer of the wire layer. National Standard (CNS) A4 Specification (210X297 & i) '' (Please read the precautions on the back before filling this page) 装 _
*1T 經濟部中央標準局負工消費合作社印裝 32 1 9twfl /005 A7 32 1 9twfl /005 A7 經濟部中央標準局員工消費合作社印製 __---〜_____B7_ 五、發明説明（> ) 的另一導電區相接觸，因此會造成不正常的導通，即造成 短路（Short)，而引起元件的失效。 第1A晴至第1£圖係繪示傳統式未接著介層窗之製造 流程的剖面禾意圖。 參照第1A圖，首先提供具有一平坦表面的介電層 100 (此介電層1〇〇以下之基底的部份並未完全畫出）， 介電層1〇〇例如是內金屬介電層（IMD)或是內層介電層 (Inter-Layer Dielectrics ; ILD)等的介電材料層，並且於 介電層1〇〇上形成一層導電層1〇2，例如以擺鍍 (Sputtering)的方式或化學氣相沈積法（CVD形成的銅、 鋁、錫銅合金等金屬材料所構成的導電層1〇2。 請參照第1B圖’利用傳統的微影、蝕刻製程定義導電 層102，例如以非等向性的蝕刻法，而在介電層1〇〇上形 成導線 102a，l〇2b, 102c。 請參照第1C圖，在介電層100上形成—層內金屬介電 層106,例如以化學氣相沈積法（CVD)沈積的氧化矽層， 且覆盘導線102a，102b，l〇2c。之後，進行介電層1〇6的平 坦化，例如以化學機械硏磨法（CMP)。 請參照第1D圖’利用傳統的微影、蝕刻程序定義介電 層106 ’而在介電層l〇6a中形成一介層窗開口 1〇8。由於 在定義介層窗開口 108時，過度鈾刻的控制不當，所以易 蝕穿介電層106a而到達介電層1〇〇中，進而到達介電層 100中的另一導電區（圖中未顯示），因而形成未接著的 介層窗開口 108。如此一來，在後續形成介層窗之後，會 4 本紙張尺度適用中國國家標準（CNS ) A4規棺1 210 X Μ?公瘦) (請先閱讀背面之注意事項再填寫本頁) -裝-* 1T Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 32 1 9twfl / 005 A7 32 1 9twfl / 005 A7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs __--- ~ _____ B7_ V. Description of Invention The other conductive areas of the two are in contact with each other, which will cause abnormal conduction, that is, short circuit, and cause component failure. Figures 1A to 1 £ are cross-sectional views of the manufacturing process of a conventional non-adhered window. Referring to FIG. 1A, a dielectric layer 100 having a flat surface is first provided (the portion of the substrate below the dielectric layer 100 is not completely drawn). The dielectric layer 100 is, for example, an inner metal dielectric layer (IMD) or a dielectric material layer such as Inter-Layer Dielectrics (ILD), and a conductive layer 10 is formed on the dielectric layer 100, for example, by sputtering. Method or chemical vapor deposition (CVD, copper, aluminum, tin-copper alloy and other metal materials composed of a conductive layer 102. Please refer to Figure 1B, using the traditional lithography and etching process to define the conductive layer 102, such as Wires 102a, 102b, and 102c are formed on the dielectric layer 100 by anisotropic etching. Referring to FIG. 1C, a dielectric metal layer 106 is formed on the dielectric layer 100, For example, a silicon oxide layer deposited by a chemical vapor deposition (CVD) method and the covered wires 102a, 102b, and 102c. Thereafter, the dielectric layer 106 is planarized, such as by a chemical mechanical honing method (CMP). ) Please refer to FIG. 1D, 'Define dielectric layer 106 using conventional lithography and etching procedures' A dielectric window opening 108 is formed in 6a. Because the excessive uranium etching is not properly controlled when defining the dielectric window opening 108, it is easy to etch through the dielectric layer 106a to reach the dielectric layer 100, and then to the dielectric. Another conductive region (not shown in the figure) in the layer 100 forms an unconnected via window opening 108. In this way, after the subsequent formation of the via window, 4 paper sizes will be applied to the Chinese National Standard (CNS) A4 gauge coffin 1 210 X Μ? Male thin) (Please read the precautions on the back before filling this page)-装-
、1T A7 3219twfl/〇〇5 B7 Γ——— ~ ~1 _ — 五、發明説明〇 ) ~--- 造成不正常的導通，而引起元件的失效。 H· - II - n #^i n I ^—I I I n —2— T (請先閱讀背面之注意事項再填寫本頁) 請參照第IE ffl，於鈾刻介電層1〇6a所形成的介· 開口 108中，沈積一層與介層窗開口 1〇8的表面共形的 (Conformal )黏著/阻障層11〇 ’例如是鈦/氮化欽 (Ti/TiN)、鉬/氮化組（Ta/TaN)等的導電材料，用以增 加隨後沈積的導電層與其他材質間的附著力。 接著，在介電層106a上沈積一層導電層，例如是以化 學氣相沈積法（CVD)形成的鎢金屬層，且塡滿介層窗開 口 108 ’進而與金屬線102b電性親接。之後，移除介電層 106a上過剩的導電層，例如使用回蝕刻（Etching Back) 的方式或以化學機械硏磨法（CMP)，以移除介電層i〇6a 上部份的導電層，而在介電層106a中的介層窗開口 1〇8 內形成與金屬線l〇2b電性耦接的介層窗插塞112。 然而，由於在定義介層窗開口 108時，過度蝕刻的控 制不當，所以易蝕穿介電層106a而到達介電層1〇〇中的另 一導電區（圖中未顯示）。因此，在形成介層窗插塞112 之後，介層窗插塞112會深入於介電層1〇〇中，進而與介 電層100中的另一導電區相接觸。 經濟部中央標準局員工消費合作社印裝 如上所述，以習知之方法製造的介層窗插塞112，易 因過度蝕刻的控制不當，而造成介層窗開口 108深入於介 電層1〇〇中，甚至到達介電層100中的另一導電區，在後 續形成介層窗插塞112後，此插塞112會與介電層1〇〇中 的另一導電區相接觸，因此會造成不正常的導通，即造成 短路，進而引起元件的失效。 5 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） 32 1 9twfl /005 A7 B7 五、發明説明（f ) 有鑑於此，本發明的主要目的就是在提供一種未接著 介層窗的製造方法，丛麗篮歷通蝕刻終止層的雙層結搆， 做爲導線層的內金屬介電層，在內金屬介電層中形成未接 著介層窗開口時，由於絕緣層和蝕刻終止層的材質不同， 所以可以避免因過度蝕刻的控制不當，而造成內金屬介電 層的蝕穿，故可以避免介層窗插塞與導線層下層之介電層 中的另一導電區之間形成不正常的導通，即造成短路，而 引起元件的失效。 根據本發明的主要目的，提出一種未接著介層窗的製 造方法，包括：在介電層上形成蝕刻終止層和第一絕緣 層，續定義第一絕緣層和蝕刻終止層以形成一溝渠。之 後，在溝渠中形成一導線，並且在第一絕緣層上形成覆蓋 導線的第二絕緣層。接著，蝕刻第二絕緣層和第一絕緣層 以形成一介層窗開口，直到暴露出蝕刻終止層。然後，在 介層窗開口中形成介層窗插塞，此插塞與導線的上表面和 部份側壁均電性耦接。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1E圖係繪示傳統式未接著介層窗之製造 流程的剖面示意圖；以及 第2A圖至第2E圖係繪示根據本發明之一較佳實施 例，一種未接著介層窗之製造流程的剖面示意圖。 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ' I 批衣 訂 氣 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印聚 3219t\vfl/005 A 7 B7 五、發明説明（Γ) 圖式之標記說明： 100, 200 介電層 102 導電層 102a, 102b, 102c, 208a, 208b, 208c 導線 106, 106a, 204, 204a, 214 絕緣層 108,216 介層窗開口 no, 218 黏著/阻障層 112, 220 插塞 202, 202a 蝕刻終止層 206a, 206b, 206c 溝渠 實施例 第2A圖至第2E圖係繪示根據本發明之一較佳實施 例，一種未接著介層窗之製造流程的剖面示意圖。 經濟部中央標準局員工消費合作社印製 請參照第2A圖，首先提供具有一平坦表面的介電層 200 (此介電層200以下之基底的部份並未完全畫出）， 介電層200例如是內金屬介電層（IMD)或是內層介電層 (ILD)等的介電材料層，並且在介電層200上形成一層 飩刻終止層202，例如以化學氣相沈積法（CVD)形成之 氮化砂層，厚度約爲2000埃。之後，在触刻終止層202 上形成一層絕緣層204，例如以化學氣相沈積法（CVD) 形成之氧化砂層，厚度約爲8000埃。触刻終止層202和 絕緣層204之厚度的總和，約與後續形成第一層導線之溝 渠的高度相當。 請參照第2B圖，以習知之微影、蝕刻製程，例如以非 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210父297公釐） 3219twfl/005 A7 3219twfl/005 A7 經濟部中央標準局員工消費合作社印製 B7__, 五、發明説明（“） 等向性蝕刻法，定義絕緣層204和蝕刻終止層202，進而 在蝕刻終止層202a和絕緣層204a中形成後續用以形成第 一層導線的溝渠206a，206b和206c，且暴露出部份介電層 200的表面。 請參照第2C圖，於介電層200上形成一層導電層（圖 中未顯示），例如是銅、鋁、鋁銅合金等的金屬材料，且 塡滿溝渠206a，206b和206c。之後，移除絕緣層2〇4a上 的部份導電層，例如以化學機械硏磨法（CMP)，直到暴 露出絕緣層204a的表面，而分別在溝渠206a，206b和206c 中形成第一層導線208a，208b和208c。 請參照第2D圖，在介電層200上形成一絕緣層214， 例如以化學氣相沈積法（CVD)沈積的氧化矽層，或是以 矽酸四乙酯（Tetra-ethyl-ortho-silicate，TEOS)爲氣體源， 較佳爲使用化學氣相沈積法（CVD)或電漿增強化學氣相 沈積法（Plasma Enhanced Chemical Vapor Deposition ; PECVD)沈積的氧化矽層，且覆蓋導線208a, 208b，208c 和絕緣層204a。之後，進行絕緣層214的平坦化，例如以 化學機械硏磨法（CMP)，以平坦化絕緣層214的表面， 直到絕緣層214的厚度約與後續形成之介層窗開口的高度 相當。 之後，利用傳統的微影、蝕刻程序，以蝕刻終止層202a 爲蝕刻程序的終止層，定義絕緣層214，以形成一開口 216 ’例如使用非等向性蝕刻法，此開口 216的寬度大於 導線208b的寬度，且暴露出的導線2〇8b的上表面和部份 8 本紙張尺度適用中國國家兩^ (CNS) M驗（210x撕公董 ----------^------、玎------4 - / (請先閱讀背面之注意事項再填寫本頁) 32l9twfl/005 A7 B7 五、發明説明（7 ) 側壁’故在後續形成介層窗插塞後，可以增加介層窗插塞 和導線2〇8b間的接觸面積。 (請先聞讀背面之注意事項再填寫本頁) 在定義介層窗開口 216時，由於導線2〇8b外圍的內金 屬介電層係由蝕刻終止層2〇2a和絕緣層2〇4a的雙層結構 所構成，且蝕刻終止層202a和絕緣層2〇4a的材質不同， 因此即使過度蝕刻的控制不當，在絕緣層214、絕緣層204a 和蝕刻終止層202a中定義介層窗開口 216時，鈾刻終止層 202a可做爲蝕刻絕緣層214和絕緣層2〇4的蝕刻終止層， 故不會造成內金屬介電層（IMD)的蝕穿，甚至到達導線 層下層之介電層200中的另一導電區，而發生如習知之不 正常的導通’而引起元件的失效。 因此’利用傳統的微影、蝕刻程序，例如使用反應性 離子触刻法（RIE ) ’以局触刻選擇比（絕緣層214和絕 緣層204a對蝕刻終止層202a)的蝕刻劑，以蝕刻終止層 202a爲蝕刻程序的終止層，在絕緣層214和絕緣層204a 中定義開口 216時，開口 216暴露出導線208b的上表面 和部份側壁。 經濟部中央標準局員工消費合作社印裝 因爲本發明以絕緣層204a和蝕刻終止層202a的雙層 結構’做爲第一層導線208a，208b和2〇8c的內金屬介電 層（IMD)，在形成未接著介層窗開口 216時，可以暴露 出導線208b的上表面和部份側壁，增加導線208b與後續 形成之插塞的接觸面積，進而降低導線208b與後續形成 之插塞的接觸電阻値。而且蝕刻終止層2〇2a可以做爲未接 著介層窗開口 210a的鈾刻終止層’所以不會造成內金屬介 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 3219twfl/〇〇5 A7 B7_ , 五、發明説明（？） 電層的蝕穿，故可以防止介層窗與導線層下層之介電層中 其他導電區之間形成不正常的導通，而引起元件的失效。 請參照第2E圖，在絕緣層214中的介層窗開口 216 中，沈積一層與介層窗開口 216的表面共形的黏著/阻障層 218，例如是鈦/氮化鈦（Ti/TiN)、鉬/氮化钽（Ta/TaN) 等的導電材料，用以增加隨後沈積的導電層與其他材質間 的附著力。 接著，在介電層200上沈積一層導電層，例如是以化 學氣相沈積法（CVD)形成的鎢金屬層，且至少塡滿介層 窗開口 216，進而與導線208b的上表面和部份側壁相接 觸。之後，移除絕緣層214上的部份導電層，例如使用回 蝕刻的方式或化學機械硏磨法（CMP)，直到暴露出絕緣 層214,而在絕緣層214和絕緣層204a中的介層窗開口 216 內形成與導線208b電性耦接的插塞22〇。 綜上所述，本發明的特徵在於： 1.習知的方法在定義介層窗開口時’易因過度蝕刻的 控制不當，而造成介層窗開口深入於導線層下層之介電層 中，甚至到達導線層下層之介電層中的另一導電區，在後 續形成介層窗插塞後，此插塞會與導線層下層之介電層中 的另一導電區相接觸，因此會造成不正常的導通，即造成 短路，而引起元件的失效。 本發明以蝕刻終止層和絕緣層（例如氮化矽層和氧化 石夕層）的雙層結構，做爲第一層導線的內金屬介電層 (IMD)，在形成未接著介層窗開口時，可以暴露出導線 10 I I 裝 n I ^ n n I ^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨〇'乂297公釐） 32 1 9twfl /005 A7 B7 五、發明説明（7 ) 的上表面和部份側壁，增加導線與後續形成之介層窗插塞 的接觸面積，進而降低導線與插塞的接觸電阻値。而且由 於蝕刻終止層的存在，在蝕刻未接著介層窗開口時，可以 防止內金屬介電層的蝕穿，故可以避免介層窗與導線層下 層之介電層中的中另一導電區之間形成不正常的導通，而 引起元件的失效。 2.本發明的製程均與現有的製程相容，極適合廠商的 生產安排。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 ----------t.------ΐτ------i (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 11 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）、 1T A7 3219twfl / 〇〇5 B7 Γ ———— ~ ~ 1 _ — V. Description of the invention 〇) ~ --- Causes abnormal conduction and causes component failure. H ·-II-n # ^ in I ^ —III n —2— T (Please read the precautions on the reverse side before filling out this page) Please refer to IE ffl for the dielectric formed by the dielectric layer 106a etched in uranium · In the opening 108, a conformal adhesive / barrier layer 11 ′ which is conformed to the surface of the interlayer window opening 108 is, for example, titanium / nitride (Ti / TiN), molybdenum / nitride group ( Ta / TaN) and other conductive materials are used to increase the adhesion between the subsequently deposited conductive layer and other materials. Next, a conductive layer, such as a tungsten metal layer formed by a chemical vapor deposition (CVD) method, is deposited on the dielectric layer 106a, and the dielectric window opening 108 'is filled and then electrically connected to the metal line 102b. After that, the excess conductive layer on the dielectric layer 106a is removed, for example, using an Etching Back method or a chemical mechanical honing method (CMP) to remove a portion of the conductive layer on the dielectric layer 106a. A dielectric window plug 112 electrically coupled to the metal line 102b is formed in the dielectric window opening 108 in the dielectric layer 106a. However, due to improper control of over-etching when defining the dielectric window opening 108, it is easy to etch through the dielectric layer 106a and reach another conductive region (not shown) in the dielectric layer 100. Therefore, after the interlayer window plug 112 is formed, the interlayer window plug 112 will penetrate into the dielectric layer 100 and then contact another conductive region in the dielectric layer 100. The consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs printed the above-mentioned interlayer window plug 112 manufactured by a conventional method, which is easily caused by improper control of excessive etching, which causes the interlayer window opening 108 to penetrate into the dielectric layer 100. And even reach another conductive region in the dielectric layer 100. After the subsequent formation of the dielectric window plug 112, this plug 112 will contact another conductive region in the dielectric layer 100, which will cause Improper continuity will cause short circuit, which will cause component failure. 5 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) 32 1 9twfl / 005 A7 B7 5. Description of the Invention (f) In view of this, the main purpose of the present invention is to provide an unbonded interposer The manufacturing method of the window, the double-layer structure of the Cong Li basket etch stop layer is used as the inner metal dielectric layer of the wire layer. When the opening of the dielectric window is not formed in the inner metal dielectric layer, due to the insulating layer and etching The material of the termination layer is different, so the internal metal dielectric layer can be prevented from being corroded due to improper control of over-etching. Therefore, the dielectric window plug and another conductive region in the dielectric layer under the wire layer can be avoided. An abnormal conduction is formed between them, which causes a short circuit and causes the component to fail. According to the main purpose of the present invention, a method for manufacturing a non-adhesive window is provided. The method includes: forming an etch stop layer and a first insulating layer on the dielectric layer, and continuing to define the first insulating layer and the etch stop layer to form a trench. Thereafter, a conductive line is formed in the trench, and a second insulating layer covering the conductive line is formed on the first insulating layer. Next, the second insulating layer and the first insulating layer are etched to form a via window opening until the etch stop layer is exposed. A via plug is then formed in the via window opening, and this plug is electrically coupled to the upper surface of the wire and a part of the sidewall. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A Figures 1E to 1E are schematic cross-sectional views showing the manufacturing process of a conventional non-adhered interstitial window; and Figures 2A to 2E illustrate a manufacturing of a non-adhered interstitial window according to a preferred embodiment of the present invention. A schematic cross-sectional view of the process. 6 This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) 'I batch order (please read the precautions on the back before filling this page) Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 3219t \ vfl / 005 A 7 B7 V. Description of the invention (Γ) Symbols of the drawings: 100, 200 dielectric layer 102 conductive layer 102a, 102b, 102c, 208a, 208b, 208c conductor 106, 106a, 204, 204a, 214 insulation layer 108,216 interstitial window openings no, 218 adhesion / barrier layer 112, 220 plug 202, 202a etch stop layer 206a, 206b, 206c trench embodiment Figures 2A to 2E show a preferred implementation according to the present invention For example, a schematic cross-sectional view of a manufacturing process without an interlayer window. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, please refer to Figure 2A. First, a dielectric layer 200 with a flat surface is provided (the portion of the substrate below the dielectric layer 200 is not completely drawn). The dielectric layer 200 For example, it is a dielectric material layer such as an inner metal dielectric layer (IMD) or an inner dielectric layer (ILD), and an etch stop layer 202 is formed on the dielectric layer 200, for example, by chemical vapor deposition ( A nitrided sand layer formed by CVD) has a thickness of about 2000 Angstroms. After that, an insulating layer 204 is formed on the contact stop layer 202, for example, an oxide sand layer formed by a chemical vapor deposition (CVD) method, with a thickness of about 8000 angstroms. The sum of the thicknesses of the etch stop layer 202 and the insulating layer 204 is about the same as the height of the trenches forming the first-layer wires in the subsequent steps. Please refer to Figure 2B for the conventional lithography and etching processes. For example, the Chinese National Standard (CNS) A4 specification (210 parent 297 mm) applies to non-7 paper sizes. 3219twfl / 005 A7 3219twfl / 005 A7 Central Standard of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Bureau B7__, V. Description of the Invention (") Isotropic etching method, defines the insulating layer 204 and the etching stop layer 202, and then forms subsequent layers in the etching stop layer 202a and the insulating layer 204a to form the first layer. The trenches 206a, 206b, and 206c of the conductive lines expose part of the surface of the dielectric layer 200. Referring to FIG. 2C, a conductive layer (not shown) is formed on the dielectric layer 200, such as copper, aluminum, Metal materials such as aluminum-copper alloy, and filled the trenches 206a, 206b, and 206c. After that, remove a part of the conductive layer on the insulating layer 204a, for example, by chemical mechanical honing (CMP), until the insulating layer is exposed 204a, and the first layers of wires 208a, 208b, and 208c are formed in the trenches 206a, 206b, and 206c, respectively. Referring to FIG. 2D, an insulating layer 214 is formed on the dielectric layer 200, for example, by chemical vapor deposition (CVD) deposited oxygen Silicon layer, or Tetra-ethyl-ortho-silicate (TEOS) as the gas source, preferably using chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition; PECVD), and covers the wires 208a, 208b, 208c and the insulating layer 204a. Then, the insulating layer 214 is planarized, for example, by chemical mechanical honing (CMP) to planarize the insulation. The thickness of the surface of the layer 214 up to the thickness of the insulating layer 214 is about the same as the height of the opening of the interlayer window formed later. Then, using the traditional lithography and etching process, the etching stop layer 202a is used as the stop layer of the etching process to define the insulation layer. 214 to form an opening 216 'for example, using an anisotropic etching method, the width of this opening 216 is greater than the width of the wire 208b, and the exposed upper surface of the wire 208b and a part 8 ^ (CNS) M test (210x tear off public director ---------- ^ ------, 玎 ------ 4-/ (Please read the precautions on the back before filling in this (Page) 32l9twfl / 005 A7 B7 V. Description of the invention (7) The side wall is therefore behind After forming the via window plug, you can increase the contact area between the via window plug and the wire 208b. (Please read the precautions on the back before filling this page.) When defining the via window opening 216, The inner metal dielectric layer around the 208b is composed of a double-layered structure of the etch stop layer 202a and the insulating layer 204a, and the materials of the etch stop layer 202a and the insulation layer 204a are different, so even if over-etched Improper control. When the via window opening 216 is defined in the insulating layer 214, the insulating layer 204a, and the etch stop layer 202a, the uranium etch stop layer 202a can be used as an etch stop layer to etch the insulating layer 214 and the insulating layer 204. It will not cause the internal metal dielectric layer (IMD) to erode, or even reach another conductive region in the dielectric layer 200 below the wire layer, and the abnormal conduction such as the conventional one will occur, causing the component to fail. Therefore, 'using conventional lithography and etching processes, for example, using reactive ion etching (RIE)', an etching agent with a local etching selection ratio (the insulating layer 214 and the insulating layer 204a to the etching stop layer 202a) is used to terminate the etching. The layer 202a is a termination layer of the etching process. When the opening 216 is defined in the insulating layer 214 and the insulating layer 204a, the opening 216 exposes the upper surface of the wire 208b and a part of the sidewall. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs because the present invention uses the double-layer structure of the insulating layer 204a and the etch stop layer 202a as the inner metal dielectric layer (IMD) of the first layer of wires 208a, 208b, and 208c When the non-adhesive via window opening 216 is formed, the upper surface of the wire 208b and a part of the side wall may be exposed, increasing the contact area between the wire 208b and a subsequently formed plug, thereby reducing the contact resistance between the wire 208b and a subsequently formed plug. value. In addition, the etch stop layer 202a can be used as the uranium etch stop layer that does not follow the opening 210a of the interlayer window, so it will not cause internal metal interlayers. 9 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 3219twfl / 〇〇5 A7 B7_, V. Description of the invention (?) The electrical layer is eroded, so it can prevent abnormal conduction between the dielectric window and other conductive areas in the dielectric layer below the wire layer, which may cause the device. Of failure. Referring to FIG. 2E, in the interlayer window opening 216 in the insulating layer 214, an adhesion / barrier layer 218 conforming to the surface of the interlayer window opening 216 is deposited, for example, titanium / titanium nitride (Ti / TiN ), Molybdenum / tantalum nitride (Ta / TaN) and other conductive materials to increase the adhesion between the subsequently deposited conductive layer and other materials. Next, a conductive layer is deposited on the dielectric layer 200, for example, a tungsten metal layer formed by a chemical vapor deposition (CVD) method, and at least fills the dielectric window opening 216, and then the upper surface and a portion of the conductive line 208b. The side walls are in contact. After that, a part of the conductive layer on the insulating layer 214 is removed, for example, an etch-back method or a chemical mechanical honing method (CMP) is used until the insulating layer 214 is exposed, and the interposer in the insulating layer 214 and the insulating layer 204a A plug 22 is formed in the window opening 216 to be electrically coupled to the wire 208b. In summary, the present invention is characterized in that: 1. The conventional method, when defining the opening of the interlayer window, is apt to cause improper control of over-etching, which causes the opening of the interlayer window to penetrate into the dielectric layer below the wire layer. It even reaches another conductive region in the dielectric layer below the wire layer. After the subsequent formation of a dielectric window plug, this plug will contact another conductive region in the dielectric layer below the wire layer, which will cause Improper continuity causes short circuit and component failure. In the present invention, a double-layer structure of an etch stop layer and an insulating layer (such as a silicon nitride layer and a stone oxide layer) is used as an inner metal dielectric layer (IMD) of a first-layer wire. At the time, the wires can be exposed. 10 II Pack n I ^ nn I ^ (Please read the precautions on the back before filling out this page) Printed on the paper by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. The paper size applies to the Chinese National Standard (CNS) A4 specification. (2 丨 〇 '乂 297 mm) 32 1 9twfl / 005 A7 B7 V. The upper surface and part of the side wall of the invention description (7), increase the contact area between the wire and the subsequently formed interlayer window plug, thereby reducing the wire Contact resistance with plug 插. And because of the presence of the etch stop layer, when the etching does not follow the opening of the interlayer window, the internal metal dielectric layer can be prevented from being etched through, so that another conductive region in the dielectric layer under the interlayer window and the wire layer can be avoided. An abnormal conduction is formed between them, causing component failure. 2. The manufacturing process of the present invention is compatible with the existing manufacturing process, and is very suitable for manufacturers' production arrangements. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ---------- t .------ ΐτ ------ i (Please read the notes on the back before filling out this page) Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 11 This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm)