0 5 00TWF.doc/BL/Jonathan/0 02 A7 B7 經濟部中央棵準局属工消費合作社印裝 五、發明説明（丨） 本發明係有關於積體電路元件中連接線構造（winng structure)之製作。特定而言，本發明係有關於介層洞 (vi as)與延伸穿過介層洞而連接至埋置的連接線（wiring 1 ines)或接線墊（pads)的內連線（interconnect)之製 作。 許多高度集積的半導體電路皆使用了多層連接線的構 造，以將元件內部的各個區域互相連接起來，以及將積體 電路內的一或更多個的元件連接起來。在製作此種構造 時，習知之技術是先製成第一層的連接線，並再於其上沉 積一金屬間介電質層，穿透金屬間介電質層而形成一介層 洞，以便曝露出第一層連接線的一部份，並再將金屬沉積 於介層洞內，形成一種垂直延伸的內連線或「插塞」 _ (Plugs)。接著再於金屬間介電質層上形成一第二層的連 接線，第二層連接線中的其中一條與插塞接觸，以將第一 層連接線連接到電路中的其他導體上。習知穿透金屬間介 電質層而製作介層洞的方法，以及習知用來將金屬插塞製 成連接線層之間的垂直內連線的方法，可能會產生出具有* 令人無法接受之電阻的內連線，造成無法令人滿意的內連 線結構。 圖丨-3中顯示一種習知的多層連接線結構以及製作該 構造的一種方法。圖1中顯示處於製作過程一中間步驟的 一個半導體電路，其中一層絕緣材料12覆蓋著一半導體底 材10。第一層的連接線14係被設置於絕緣材質層12上’ 此層連接線典型係與製作於半導體底材上另一端的一或 (請先閲讀背面之注項再填寫本頁) .Γ. 訂0 5 00TWF.doc / BL / Jonathan / 0 02 A7 B7 Printed by the Industrial and Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs V. Description of the invention (丨) The present invention relates to the wiring structure (winng structure) of integrated circuit components Of production. In particular, the present invention relates to vias and interconnects extending through the vias and connected to buried wiring (wiring 1 ines) or pads (pads) Make. Many highly integrated semiconductor circuits use a multi-layer connection structure to connect the various regions inside the device to each other, and to connect one or more devices in the integrated circuit. When fabricating such a structure, the conventional technique is to first form the connecting line of the first layer, and then deposit an inter-metal dielectric layer thereon, and penetrate the inter-metal dielectric layer to form a via hole, so that Expose a portion of the first layer of connecting wires, and then deposit the metal in the via hole to form a vertically extending interconnect or "plug" (Plugs). Then, a second layer connection line is formed on the intermetal dielectric layer, and one of the second layer connection lines contacts the plug to connect the first layer connection line to other conductors in the circuit. The conventional method of making a via hole through an intermetallic dielectric layer, and the conventional method of making a metal plug into a vertical interconnection between connecting line layers, may produce Unacceptable resistance interconnection results in an unsatisfactory interconnection structure. Fig. 丨 -3 shows a conventional multi-layer connecting line structure and a method of manufacturing the structure. Fig. 1 shows a semiconductor circuit in an intermediate step of the manufacturing process, in which a layer of insulating material 12 covers a semiconductor substrate 10. The first layer of the connection line 14 is provided on the insulating material layer 12 '. This layer of connection line is typically made on the other end of the semiconductor substrate (please read the notes on the back before filling this page). . Order
C 本紙張尺度適用中國國家揉準（CNS ) A4规格（210Χ 297公嫠） 經濟部中央標準局員工消費合作社印装 t ο TWF.doc/BL/Jonathan/0 02 Α7 _Β7__— 一 五、發明说明（>) 更多個元件（未顯示）接觸。一金屬間介電質層16覆蓋 一層連接線Η與絕緣材質層12未被第一層連接線的構造 所覆蓋的部份。圖2中顯示圖1的元件其一介層洞 金屬間介電質層16而形成，並尚下到達第一層連接線14 的表面。此介層洞係利用非等向性蝕刻製成的°通胃’ # 層洞係被形成於連接線或接觸墊的尾端或邊緣之處。 是由於設計，對準或製程誤差的緣故，介層洞的一^份‘可" 能會形成於第一層連接線14的一個邊緣之上，形成了所謂 的「未接著介層洞」（unlanded via)。當未接著介層洞形 成時，特別是當介層洞蝕刻程序使用連接線14的金屬表面 做爲蝕刻阻擋時，介層洞便可能會沿著第一層連接線的側 壁延伸進入金屬間介電質層16內，形成了鄰接著連接線 14的一個空穴20。 圖3中顯示圖2的構造在進一步製程步驟之後，在介 層洞內形成一金屬插塞24以與第一層連接線14接觸的情 形。在一典型結構之中，第一層連接線14可爲鋁，銅，鋁 與矽或銅的合金，或其他製作起來不昂貴的導電材料。金 屬插塞通常是由鎢所製成的，但其他包括鋁或銅的材料亦 是可以使用的。習知技術中所瞭解的是，金屬插塞24的形 成會在一個未接著的介層洞內沿著一條連接線將任何穴 室20的內部塡充起來。事實上，圖3中所顯示型態的內連 線構造，可能會在不同批次中與在每一單一晶圓上，皆顯 現出不同程度的電阻特性。由於會損傷元件的性能及降低 產品之良率，高阻値的電阻與變動的電阻兩者皆是不能接 5 本紙張尺度適用中國國家標準(CNS ) A4規格（210 X 297公釐)~ ' (請先閲讀背面之注意事項再填寫本頁) .κ^..C This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210Χ 297 gong). Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs TWF.doc / BL / Jonathan / 0 02 Α7 _Β7 __— 15 (≫) More components (not shown) are in contact. An intermetallic dielectric layer 16 covers a portion of the connection line H and the insulating material layer 12 that is not covered by the structure of the first connection line. FIG. 2 shows that the device of FIG. 1 is formed with a via hole intermetal dielectric layer 16 and still reaches the surface of the first layer connecting line 14. This via hole system is made by anisotropic etching ° 通 胃 '# The layer hole system is formed at the end or edge of the connection line or contact pad. It is because of design, alignment, or process errors that a portion of the via hole can be formed on one edge of the first-layer connection line 14, forming a so-called "unattached via hole" (Unlanded via). When the via hole is not formed, especially when the via hole etching process uses the metal surface of the connection line 14 as an etch barrier, the via hole may extend into the intermetal via along the side wall of the first layer connection line A hole 20 adjacent to the connection line 14 is formed in the electrical layer 16. FIG. 3 shows the structure of FIG. 2 after a further process step, a metal plug 24 is formed in the via hole to contact the first layer connecting line 14. In a typical structure, the first layer of connecting wires 14 may be aluminum, copper, an alloy of aluminum and silicon or copper, or other conductive materials that are inexpensive to manufacture. Metal plugs are usually made of tungsten, but other materials including aluminum or copper can also be used. It is known in the prior art that the formation of the metal plug 24 fills the interior of any cavity 20 along a connecting line in an unconnected via. In fact, the interconnect structure shown in Figure 3 may show different levels of resistance characteristics in different batches and on each single wafer. Because it will damage the performance of the component and reduce the yield of the product, neither the high-resistance resistance nor the variable resistance can be connected. 5 The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ~ ' (Please read the notes on the back before filling out this page) .κ ^ ..
C WF.doc/BL/Jonathan/002 A7 WF.doc/BL/Jonathan/002 A7 經濟部中夬標率局員工消費合作社印製 B7 五、發明説明（3) 受的。 因此，本發明之一目的即在於提供製作金屬內連線結 構的一種方法，其具有更均勻且可預期的電阻。 本發明之一實施例提供在一半導體元件中製作內連線 構造的一種方法。於一半導體底材上，鄰接著第一絕錄層 提供一導電層，該導電層與第一絕緣層具有共同平面的上 表面。一蝕刻阻擋層被沉積於導電層與第一絕緣層之上表 面上，其係與第一絕緣層不同。第二絕緣層則被沉積於蝕 刻阻擋層上，其與蝕刻阻擋層不同，並蝕刻出一介層洞以 曝露出蝕刻阻擋層之一部份，被蝕刻之介層洞係至少局部 地形成於導電層上方。介層洞內之蝕刻阻擋層再被移除， 並再於介層洞內塡充一導電材料。 依據本發明之另一要點，於一半導體元件內製作內連 線之一種方法，其係於一半導體底材上，提供具有一邊緣 與一上表面之一絕緣層。沿著絕緣層之邊緣提供有一金屬 層，該金屬層具有一上表面，此表面並被電性地連接至半 導體底材上。一介電質層被沉積於絕緣層與金屬層之上表 面上，接著再沉積一介電質層於蝕刻阻擋層上。一介層洞 穿透介電質層而形成，以曝露出蝕刻阻擋層，並再移除介 層洞內之蝕刻阻擋層，以曝露出金屬層之至少一部份。再 於介層洞內形成一金屬插塞，以將金屬層連接至形成於介 ^ 電質層之上的一導體。 本發明之另一要點係在於爲半導體元件製作內連線， 其係於一半導體底材上提供一絕緣層，並於絕緣層上形成 6 (請先閱讀背面之注意事項再填寫本頁) 1^1^1 v^m 11.^1 m n ml> nf^ ^^^^1 B^i^f nn a^^i— ml Bull .裝—-------訂 ----c----Γ—— 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 0 5 00TWF.doc/BL/Jonathan/002 A7 B7 五、發明説明（f) 下陷的一圖案。金屬層被平坦化以在絕緣層中形成對應於 下陷之圖案的第一層金屬連接線之圖案。絕緣層與金屬線 之表面上再沉積一蝕刻阻擋層，之後再於蝕刻阻擋層上沉 積一介電質層。一介層洞穿透介電質層而形成，以曝露出 蝕刻阻擋層，之後介層洞內之蝕刻阻擋層即被移除，以曝 露出金屬連線之至少一部份。此時介層洞內即可以形成一 金屬插塞。 圖式之簡要說明： 第1-3圖顯示習知技術之第一層連接線之內連線，並用以 說明其製作之方法； 第4圖顯示當使用形成了未接著插塞構造的鎢插塞技術時 所產生的一種問題之情形；以及 第5-11圖顯示依據本發明製作多層連接線結構之製程的 特定步驟階段。 較佳實施例： 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 本發明提供一種方法可以製作不同層次的連接線之間 的內連線。本發明之較佳實施例乃是特別適用於經由一個 未接著的介層洞，亦即，只局部地製作於第一層連接線上 方的介層洞，而接觸一較低層的連接線。此種未接著介層 洞可能是由於設計不良所造成的，特別是在縮小幾何尺寸 的元件之中爲.然。未接著介層洞的過度蝕刻會沿著金屬連 接線而形成間隙，其會將經由介層洞所達成的接觸之電阻 增加到無法接受的程度。本發明可以減少因爲對未接著介 層洞所施加的過度蝕刻而出現間隙，以至影響了經由該些 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央榡準局員工消费合作社印袋 0 5 00TWF.doc/BL/Jonathan/0 02 A7 B7 五、發明説明（Ί ) 介層洞而造成接觸之電阻的可能性。此外，本發明之較佳 實施例乃是特別地適用於鎢插塞技術或其他相似的技術 被利用來塡充介層洞的情況。如同下面所將詳細描述的， 利用化學氣相沉積來製作插塞，特別是製作鎢插塞，在未 接著介層洞內可能會傾向於形成具有高達無法接受電阻 的被毒化介層洞（poisoned vias)。應用本發明之.較佳實 施例可以達到在未接著介層洞內製作更爲可靠鎢插塞的 要求。 簡言之，本發明之較佳實施例在第一層連接線以及相 鄰的第一絕緣層上提供了一層蝕刻阻擋層。第二絕緣層通 常是被沉積於第一層連接線以及第一絕緣層上方的蝕刻 阻擋層之上。對第一連接線的接觸係利用穿透第二絕緣層 而蝕刻出一介層洞而達成，其係利用蝕刻阻擋層來限制介 層洞蝕刻程序的垂直方向進行程度。在介層洞內的蝕刻阻 擋層再被除去，以在介層洞內形成在垂直方向上延伸的內 連線或插塞，之後再製成與內連結插塞接觸的第二層連接 線。 在更詳細予以說明的一實施例之中，本發明利用在第 一絕緣層的表面上形成下陷部份，而於一半導體底材的第 —絕緣層上製作出一種多層的內部連結構造。先利用化學 機械硏磨法將金屬層的多餘部份由第一絕緣層的表面去 除掉，接著再將金屬層與第一絕緣層的表面平坦化，以便 因而製成第一層連接線的圖案。一蝕刻阻擋層，其材質最 好與形成第一絕緣層的材質不同，再被沉積於第一層連接 (請先聞讀背面之注意事項再填寫本頁) -βC WF.doc / BL / Jonathan / 002 A7 WF.doc / BL / Jonathan / 002 A7 Printed by the Employee Consumer Cooperative of the Bureau of Economics and Trademarks of the Ministry of Economic Affairs B7 V. Invention Instructions (3) Accepted. Therefore, an object of the present invention is to provide a method for fabricating a metal interconnection structure, which has a more uniform and predictable resistance. An embodiment of the present invention provides a method of fabricating an interconnect structure in a semiconductor device. On a semiconductor substrate, a conductive layer is provided adjacent to the first recording layer. The conductive layer and the first insulating layer have a common planar upper surface. An etch stop layer is deposited on the upper surface of the conductive layer and the first insulating layer, which is different from the first insulating layer. The second insulating layer is deposited on the etch barrier layer, which is different from the etch barrier layer, and a via hole is etched to expose a part of the etch barrier layer, the etched via hole is formed at least partially in the conductive Above the layer. The etch stop layer in the via hole is removed again, and a conductive material is filled in the via hole. According to another aspect of the present invention, a method of fabricating interconnects in a semiconductor device is provided on a semiconductor substrate to provide an insulating layer having an edge and an upper surface. A metal layer is provided along the edge of the insulating layer. The metal layer has an upper surface which is electrically connected to the semiconductor substrate. A dielectric layer is deposited on the upper surface of the insulating layer and the metal layer, and then a dielectric layer is deposited on the etch stop layer. A via hole is formed through the dielectric layer to expose the etch stop layer, and then the etch stop layer in the via hole is removed to expose at least a part of the metal layer. A metal plug is formed in the via hole to connect the metal layer to a conductor formed on the dielectric layer. Another important point of the present invention is to make an interconnection for a semiconductor device, which provides an insulating layer on a semiconductor substrate and forms 6 on the insulating layer (please read the precautions on the back before filling this page) 1 ^ 1 ^ 1 v ^ m 11. ^ 1 mn ml > nf ^ ^^^^ 1 B ^ i ^ f nn a ^^ i— ml Bull .suit —------- book ---- c ---- Γ—— This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 0 5 00TWF.doc / BL / Jonathan / 002 A7 B7 5. Description of the invention (f) A sunken pattern. The metal layer is planarized to form a pattern of the first layer of metal connection lines corresponding to the depressed pattern in the insulating layer. An etch barrier layer is deposited on the surface of the insulating layer and the metal line, and then a dielectric layer is deposited on the etch barrier layer. A via hole is formed through the dielectric layer to expose the etch stop layer, and then the etch stop layer in the via hole is removed to expose at least a part of the metal connection. At this time, a metal plug can be formed in the via hole. Brief description of the drawings: Figures 1-3 show the interconnection of the first layer of connecting wires of the conventional technology, and are used to explain the method of its manufacture; The situation of a problem caused by the plug technology; and Figures 5-11 show the specific steps of the manufacturing process of the multilayer connection line structure according to the present invention. Preferred embodiment: Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) The present invention provides a method for making interconnections between connecting lines of different levels. The preferred embodiment of the present invention is particularly suitable for contacting a lower-level connection line via an unconnected via hole, i.e., only partially formed on the first-level connection line. Such unconnected via holes may be caused by poor design, especially in devices with reduced geometric dimensions. Over-etching without the via hole will form a gap along the metal connection, which will increase the resistance of the contact made through the via hole to an unacceptable level. The invention can reduce the gap caused by the excessive etching applied to the unconnected via hole, and even affects the application of the Chinese National Standard (CNS) A4 specification (210X297 mm) through these 7 paper standards. Employee Consumer Cooperative Printed Bag 0 5 00TWF.doc / BL / Jonathan / 0 02 A7 B7 V. Description of Invention (Ί) The possibility of contact resistance caused by interlayer holes. In addition, the preferred embodiment of the present invention is particularly applicable to the case where tungsten plug technology or other similar technologies are utilized to fill the via hole. As will be described in detail below, the use of chemical vapor deposition to make plugs, especially tungsten plugs, may tend to form poisoned vias with unacceptable electrical resistance in the unattached via vias). The application of the present invention. The preferred embodiment can meet the requirement of making a more reliable tungsten plug in the unconnected via hole. In short, the preferred embodiment of the present invention provides an etch stop layer on the first-layer connection line and the adjacent first insulating layer. The second insulating layer is usually deposited on the first layer of connection lines and the etch stop layer above the first insulating layer. The contact to the first connection line is achieved by etching a via hole through the second insulating layer, which uses an etch barrier to limit the vertical extent of the via hole etching process. The etch stop layer in the via hole is removed again to form an interconnector or plug extending vertically in the via hole, and then a second layer connecting line in contact with the interconnector plug is formed. In an embodiment described in more detail, the present invention utilizes the formation of a depressed portion on the surface of the first insulating layer to create a multilayer internal connection structure on the first insulating layer of a semiconductor substrate. First use chemical mechanical grinding to remove the excess part of the metal layer from the surface of the first insulating layer, and then flatten the surface of the metal layer and the first insulating layer, so as to make the pattern of the first layer connection . An etch barrier layer, the material of which is preferably different from the material that forms the first insulating layer, is then deposited on the first layer connection (please read the precautions on the back before filling this page) -β
本紙張尺度適用中國國家標隼（CNS ) A4规格（210X297公釐） 0 5 00TWF.doc/BL/Jonathan/002 A7 0 5 00TWF.doc/BL/Jonathan/002 A7 經濟部中央揉準扃負工消費合作社印笨 _____B7 五、發明説明（fc) 線與第一絕緣層之上。第二層的絕緣層，其材質最好與形 成蝕刻阻擋層的材質不同，則被沉積於蝕刻阻擋層之上。 再穿透絕緣層即可形成一介層洞，之後蝕刻阻擋層即由介 層洞內被除去。當介層洞未接著時，將介層洞內之蝕刻阻 擋層移除便會曝露出第一層連接線的一部份以及第一絕 緣層的一部份。由於本發明之較佳實施例之中使用有一蝕 刻阻擋層，較佳的介層洞蝕刻程序便可以形成一個介層 洞，而不致於沿著連接線而形成間隙。如同後面所將進一 步討論的，本發明此一要點在某些實施例之中具有特定的 優點。在介層洞被開挖出來之後，一黏著或黏附層便可以 沉積於介層洞內，接著便可以製成與鎢插塞接觸的第二連 接線。 本發明之要點，包括在此予以較詳細說明的實施例中 所描述者，可以避免掉至少某些介層洞毒化的機制 (mechanism)，因而可以製成更爲可靠，具有低電阻的內 連線。由本發明之特點所可以解決的一種介層洞毒化機制 係被顯現於圖4之中。圖4中顯示第一層的連接線14被形 成於覆蓋在半導體底材10上的一絕緣層12上。於如同前 述參考圖2所描述的一蝕刻程序之中，通過絕緣層16製成 一個未接著的介層洞，其結果是造成了沿著與金屬連接線 14鄰接的一個空穴20，因而形成了圖中所顯示的未接著 介層洞。爲了要達到使一鎢插塞黏結於介層洞內的目的， 通常會在介層洞內形成一黏著或黏附層22。利用選擇性地 使用諸如WF6的氣體源進行化學氣相沉積，鎢插塞24接著 9 本紙張尺度適用中國國家標率（CNS > A4規格（210X 297公釐） (請先閲讀背面之注意事項再填寫本頁)This paper scale is applicable to China National Standard Falcon (CNS) A4 specification (210X297mm) 0 5 00TWF.doc / BL / Jonathan / 002 A7 0 5 00TWF.doc / BL / Jonathan / 002 A7 Central Ministry of Economics and Labor Consumer Cooperative Yinben _____B7 V. Invention description (fc) Above the line and the first insulation layer. The material of the second insulating layer is preferably different from the material forming the etch stop layer, and is deposited on the etch stop layer. A through hole is formed through the insulating layer, and then the etch stop layer is removed from the through hole. When the via hole is not followed, removing the etch stop layer in the via hole will expose a part of the first layer connection line and a part of the first insulating layer. Since an etching barrier layer is used in the preferred embodiment of the present invention, a preferred via hole etching process can form a via hole without forming a gap along the connection line. As will be discussed further below, this point of the invention has certain advantages in certain embodiments. After the via hole is excavated, an adhesive or adhesion layer can be deposited in the via hole, and then a second connection line can be made in contact with the tungsten plug. The gist of the present invention, including those described in the embodiments described in more detail herein, can avoid at least some of the mechanism of via hole poisoning, and thus can be made into a more reliable interconnect with low resistance line. A mesoscopic poisoning mechanism that can be solved by the features of the present invention is shown in FIG. 4. FIG. 4 shows that the connection wire 14 of the first layer is formed on an insulating layer 12 covering the semiconductor substrate 10. In an etching process as described above with reference to FIG. 2, an unconnected via hole is formed through the insulating layer 16, and as a result, a cavity 20 is formed adjacent to the metal connection line 14, thereby forming It shows the unconnected via holes shown in the figure. In order to achieve the purpose of adhering a tungsten plug in the via hole, an adhesion or adhesion layer 22 is usually formed in the via hole. Using selective use of a gas source such as WF6 for chemical vapor deposition, tungsten plug 24 followed by 9 This paper scale is applicable to China ’s national standard rate (CNS> A4 specifications (210X 297 mm) (please read the notes on the back first (Fill in this page again)
1T 0S00TWF.doc/BL/Jonathan/002 A7 B7 經濟部中央榡準局員工消費合作杜印製 •^、發明説明（Ί ) 便可以形成於介層洞內。 如圖4所顯示的構造中會出現數種問題。首先，一般 是使用一種電漿蝕刻氣體來蝕刻介層洞，該電漿蝕刻氣體 是由包含有碳與氟，諸如CF*或0?6的氣體中獲得的，而這 便使得介層洞蝕刻的程序通常會造成聚合物（polymers) 的形成或沉積，此爲蝕刻反應的副產品。時常的，此些聚 合物會被陷在鄰接著金屬連接線而形成的空穴20之中，並 甚至在利用諸如ACT 935 (Ashland Chemicals公司所產製） 的溶劑進行淸洗之後仍會殘留於空穴20之內。空穴20內 的聚合物殘餘成爲內連線製程的後續每一處理步驟中的 一個污染來源。例如，黏著層的沉積，由物理氣相沉積（如 濺鍍)法所獲得的鈦或氮化鈦，便會在被污染的空穴20之 上造成極差的階狀覆蓋率。如此，在一個未接著的介層洞 內沉積一黏著層22的典型結果，便會包含一個局部封閉的 空穴之形成，其內部空間補捉住了諸如聚合物的污染物。 以WF6氣體源所進行的後續之鎢的化學氣相沉積，便可能 會與陷在空穴20內聚合物發生作用，其可能的結果爲，所 形成的鎢插塞與其下墊的第一層連接線14之間產生了不 良品質的接面。此些殘餘物亦可能會干擾鎢插塞與其上覆 蓋的第二連接線之間良好接觸的形成。 實質上，本發明係在一個未接著的介層洞蝕刻到達第 —層的連接線的期間，利用避免空穴20的形成而可以應付 解決此些問題。下面將參考圖5-11說明本發明之較佳實施 例。此些圖式之中繪述了一條內連線構造的一種特定構形 10 本紙張尺度適用中國國家標率（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填窝本頁) τ 05 00TWF.doc/BL/Jonathan/002 A7 B7_^_____ 五、發明説明（S ) 其製作成形的步驟。雖然此些實施例描述了本發明的特定 較佳實施例，但本發明之要點同樣亦可適用於其他的內連 線之構形，或使用其他製作材料的情況之中。此外’雖然 後面的討論中明確指述第一與第二層的連接線’但應要瞭 解的是，此僅係標示而已，本發明乃係可以適用於更高層 次的連接線，或者製成非相鄰層次（例如，第一與第三或 其他層）之間的連接線。 本發明可以被融入於多種不同的製作連接線與內連線 構造的方法之中。製作適當第一層連接線的圖案之一方法 係先在半導體底材上提供一金屬層，接著再使用習知的微 影技術使金屬層成像而製作成連接線。一層絕緣材料層接 著再被沉積於已成像的金屬連接線上，之後再進行化學機 械硏磨或回蝕的程序，以將第一層連接線上的絕緣層之指 定部份移除。硏磨或回蝕的程序提供了金屬連接線的一個 圖案，其具有將金屬連接線分離開的絕源區域，而連接線 的表面則在實質上是與絕緣區的表面處於同一平面上 的。圖7-11中所顯示的步驟接著即可以依下述方式進行。 依據本發明一種不同且目前爲更佳的製作連接線之方 法使用了一種選擇性沉積的製程。圖5中顯示一底材’ 其可能具有多個半導體元件形成於其中（未顯示）。雖然第 一層連接線係與底材的至少一部份或底材中的半導體元 件的至少一部份直接接觸，但通常，一護層或絕緣材料12 會被預先設置於積體電路元件的表面上。一層介電質材料 層30，諸如一層氧化矽，係利用諸如電漿增強化學氣相沉1T 0S00TWF.doc / BL / Jonathan / 002 A7 B7 Central Government Bureau of the Ministry of Economic Affairs Employee consumption cooperation du printing • ^, invention description (Ί) can be formed in the meso hole. Several problems arise in the structure shown in Figure 4. First, a plasma etching gas is generally used to etch the via hole. The plasma etching gas is obtained from a gas containing carbon and fluorine, such as CF * or 0? 6, which makes the via hole etch. The process usually results in the formation or deposition of polymers, which is a by-product of the etching reaction. Often, these polymers will be trapped in the cavity 20 formed adjacent to the metal connection line, and will remain in the liquid even after being washed with a solvent such as ACT 935 (manufactured by Ashland Chemicals). Within cavity 20. The polymer residue in the cavity 20 becomes a source of contamination in each subsequent processing step of the interconnect process. For example, the deposition of the adhesion layer, titanium or titanium nitride obtained by physical vapor deposition (such as sputtering), will cause extremely poor step coverage on the contaminated cavity 20. As such, the typical result of depositing an adhesive layer 22 in an unattached via hole would include the formation of a partially enclosed cavity whose internal space traps contaminants such as polymers. Subsequent chemical vapor deposition of tungsten with the WF6 gas source may interact with the polymer trapped in the cavity 20. The possible result is that the formed tungsten plug and the first layer under it Poor quality junctions are produced between the connecting wires 14. These residues may also interfere with the formation of a good contact between the tungsten plug and the second connecting wire overlying it. In essence, the present invention can solve these problems by avoiding the formation of the cavity 20 during the etching of an unconnected via hole to reach the connection line of the first layer. The preferred embodiments of the present invention will be described below with reference to FIGS. 5-11. In these drawings, a specific configuration of an internal connection structure is depicted. 10 paper scales are applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling the nest book Page) τ 05 00TWF.doc / BL / Jonathan / 002 A7 B7 _ ^ _____ V. Description of the invention (S) The steps of making and forming. Although these embodiments describe certain preferred embodiments of the present invention, the gist of the present invention can also be applied to other configurations of interconnects or the use of other materials. In addition, although the following discussion clearly refers to the first and second layers of the connecting line, it should be understood that this is only a mark, the present invention is applicable to higher-level connecting lines, or made Connecting lines between non-adjacent levels (for example, the first and third or other levels). The present invention can be incorporated into a variety of different methods of making connecting wires and interconnecting wires. One method of making a suitable first layer connection line pattern is to first provide a metal layer on the semiconductor substrate, and then use conventional lithography to image the metal layer to make the connection line. A layer of insulating material is then deposited on the imaged metal connection line, and then a chemical mechanical polishing or etchback process is performed to remove the specified part of the insulation layer on the first connection line. The grinding or etchback procedure provides a pattern of metal connecting lines with isolated areas that separate the metal connecting lines, and the surface of the connecting line is substantially on the same plane as the surface of the insulating area. The steps shown in Figures 7-11 can then be performed in the following manner. According to the present invention, a different and currently better method of making a connection line uses a selective deposition process. Figure 5 shows a substrate 'which may have multiple semiconductor elements formed therein (not shown). Although the first-layer connection line is in direct contact with at least a part of the substrate or at least a part of the semiconductor device in the substrate, usually, a protective layer or insulating material 12 is pre-arranged on the integrated circuit device On the surface. A layer of dielectric material 30, such as a layer of silicon oxide, is used to enhance chemical vapor deposition such as plasma
II 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)II This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (Please read the precautions on the back before filling this page)
iT 經濟部中央標準局員工消費合作社印裝 經濟部中央標準局男工消費合作社印製 3i55i)^F-d〇c/BL/j〇nathan/〇°2 a7 B7 五、發明説明（1 ) 積（PECVD, plasma-enhanced chemical vapor deposition) 法而進行沉積。接著可以執行習知的微影技術，以便形成 一光阻遮罩或硬化遮罩，其曝露出對應於所要製成連接線 之圖案區域上方的介電質層30。接著執行非等向性蝕刻， 以在介電質層30中‘形成溝渠或下陷部份，其深度係在大約 2,000-10,000 A之間。在某些情況之下，蝕刻的深度可以 延伸穿透介電質層30，並使用其下墊的護層或絕緣層1.2 做爲溝渠蝕刻的阻擋層。在其他情況之中，蝕刻的深度可 以只局部地延伸通過介電質層30，並係使用蝕刻的時間長 度來決定較厚介電質層30中的溝渠之深度。 金屬接著被沉積於元件的表面上，塡充於介電質層30 的溝渠或下陷部份內，並覆蓋了介電質層30表面的其他部 份。被沉積的金屬可爲利用化學氣相沉積法，或利用物理 氣相沉積技術所沉積的「熱」鋁。第一層連接線可包含由 不同形態的金屬所構成的層狀或複合構造，或者包含金屬 與其他材料兩者。在金屬層沉稹完成之後，多餘的材料便 由介電質層3〇的表面上，利用化學機械硏磨而除去，以提 供金屬連接線32，其上表面實質上與介電質層30的表面 同在一平面上，如圖6中所顯示的情形。較佳連接線製作 程序中的溝渠蝕刻，金屬沉積與化學機械硏磨，可以提供 狹窄的第一金屬連接線的圖案，比其他的金屬沉積與微影 技術的製程所獲得者要來得可靠。 接著，一蝕刻阻擋層34 (圖7)即被形成於元件的表面 上，覆蓋了第一層金屬連接線32，以及介電質層30的表 ____ 12 __ 本紙張尺度適财關錄準（CNS ) A4絲· ( 21GX 297公| ~ ' ί * % -------------- (請先闖讀背面之注意事項再填寫本1) 訂iT Printed by the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative Printed by the Ministry of Economic Affairs Central Standards Bureau Male Workers Consumer Cooperative 3i55i) ^ Fd〇c / BL / j〇nathan / 〇 ° 2 a7 B7 V. Invention Description (1) Product (PECVD , plasma-enhanced chemical vapor deposition) method. Then, a conventional lithography technique can be performed to form a photoresist mask or a hardened mask, which exposes the dielectric layer 30 above the pattern area corresponding to the connection line to be formed. Next, anisotropic etching is performed to 'ditch or sag in the dielectric layer 30 to a depth of about 2,000-10,000 A. In some cases, the depth of the etch may extend through the dielectric layer 30 and use the underlying protective layer or insulating layer 1.2 as a barrier for trench etching. In other cases, the depth of the etch may extend only partially through the dielectric layer 30, and the length of the etch time is used to determine the depth of the trench in the thicker dielectric layer 30. The metal is then deposited on the surface of the device, filling the trench or depression of the dielectric layer 30, and covering the rest of the surface of the dielectric layer 30. The metal to be deposited may be “hot” aluminum deposited by chemical vapor deposition or physical vapor deposition techniques. The first layer of connecting wires may include a layered or composite structure composed of different forms of metals, or both metal and other materials. After the sinking of the metal layer is completed, excess material is removed from the surface of the dielectric layer 30 by chemical mechanical polishing to provide a metal connection line 32 whose upper surface is substantially the same as that of the dielectric layer 30 The surfaces are on the same plane, as shown in Figure 6. Trench etching, metal deposition, and chemical mechanical polishing in the preferred connection line fabrication process can provide a narrow pattern of the first metal connection line, which is more reliable than those obtained by other metal deposition and photolithography processes. Next, an etch stop layer 34 (FIG. 7) is formed on the surface of the device, covering the first metal connection line 32 and the dielectric layer 30 table ____ 12 __ (CNS) A4 wire · (21GX 297 male | ~ 'ί *% -------------- (please read the notes on the back before filling in this 1) order
-C 經濟部中央標準局貝工消費合作社印製 0500TWF.doc/BL/Jonathan/002 A7 __B7 五、發明説明（w) 面上其曝露區域的表面。最好，蝕刻阻擋層34應以與介電 質層30不同的絕緣材料製成。最佳的情況是，鈾刻阻擋層 34係以與沉積於蝕刻阻擋層上的絕緣材料層36亦不同的 材料製成。使用不同的材料可以容許通過多層絕緣結構的 蝕刻程序在每一個交界面皆停止下來。通常，介電質層30 係以氧化砂製成，而被沉積於蝕刻阻擋層34表面上的絕緣 材料層36則亦爲氧化矽。蝕刻阻擋層的—種適當材料因此 即可能爲氮化砂。蝕刻的製程可在氧化矽與氮化矽兩者之 間具有高度的選擇性，特別是當使用諸如感應耦合電漿 (inductively-coupled piasma)或螺旋波電漿（hel icon wave plasma)的高密度電槳蝕刻製程時。 氮化矽蝕刻阻擋層34可以利用CVD沉積到大約200至 1，000 A之間的厚度。最好，阻擋層34應具有足夠的厚度’ 以便能夠可靠地使用做爲蝕刻之阻擋物。必要的厚度可以 小到100 A ’依據介層洞所要形成通過的介電質層36之厚 度，並依據介電質層30與金屬連接線32的表面平坦度而 定。若製成圖6中構造較佳的.硏磨程序在介電質層30與金 屬連接線32之間的表面造成了明顯的階狀高差，則可能便 需要較厚層的氮化矽來確保較佳的完全階狀覆蓋率。在每 —次蝕刻阻擋層完成時，一金屬間介電質層36便可以利 用，例如，氧化矽的PECVD程序而形成ό 接著便通過金屬間介電質層36而製成一介層洞。利用 習知的微影技術或等效的方法，在金屬間介電質層的表面 上先形成一介層洞蝕刻遮罩。接著便蝕刻製作介餍洞38， 13 本紙張尺度適用中國國家標準（CNS ) A4规格（2丨ΟΧ”7公釐） (請先閱讀背面之注$項再填寫本頁) 訂 經濟部中央標_局貝工消资合作社印製 0S00TWF.doc/BL/Jonathan/002 A7 __B7 _ 五、發明説明（丨丨） 其最好是在一高密度電漿蝕刻機內使用一種非等向性的 製程，其中之電漿係由包括CF4，（：2?6與0)2的氣體源之混 ，合氣體所獲得的。此蝕刻步驟最好應在蝕刻阻擋層34處停 止。接著，利用諸如在0^3中所進行的一次非等向性蝕刻 的程序，便可對介層洞38內的蝕刻阻擋層進行蝕刻，並在 進行至介電質（氧化矽）層30之處停止。介層洞鈾刻遮罩可 在此時除去，或在鈾刻阻擋層被除去之前先行除去。 參考圖9，其中一黏著或黏附層40最好被沉積於金屬 間介電質層36的表面上，並亦沉積於介層洞38之內。使 用此種黏著層係較佳之作法，因爲增進導電插塞與第一層 連接線之間的黏著，便可以減小剝離（lift off)的可能 性。黏著層40可以爲.單獨的鈦，氮化鈦，鈦鎢合金，氮 化钽，或其他合適的材料，或上述材料之組合，通常是利 用物理氣相沉積法沉積到達數百埃的厚度。 最好，接著便應於介層洞內形成一金屬插塞42，並與 黏著層接觸，如圖10中所顯示的情形。例如，鎢插塞可以 利用WF6氣體源進行CVD而製成。在某些情況下，使用其 他包括有，例如，鋁的材料來製成插塞42是適當的選擇。 目前較佳的鎢CVD製程可將鎢沉積於整個的黏著層上。如 此，就其黏著層覆蓋了金屬間介電質層36之一部份的元件 而言，最好應使用CMP或回蝕的程序來將介層洞外，介電 質層36表面上所沉積的鎢除去，並將鎢插塞與介電質層 36的上表面予以平坦化，以形成如圖所示的插塞。在較佳 之硏磨程序中，黏著層40由介電質層36的表面上被除去。 14 ϋ尺渡適用中國國家標準（CNS )ϋΐ# ( 210xi^釐） (請先閲讀背面之注$項再填寫本頁) _^裝. 訂 A7 B7 '15517 0 50 0TWF.doc/BL/J〇nathan/0 02 五、發明説明（丨之） 其結果，便需要在介電質層36與插塞42上沉積一第二層 的黏著層44，其組成以及沉積的程序係與第一黏著層40 相似。其所造成的構造係顯示於圖11之中。 之後，製程便可以繼續下去，以便製作第二層次的連 接線’包括與第二層黏著層44接觸的第二層連接線46， 如圖11所顧示。這裏所描述的製程係可適用於第二層連接 線的一個範圍之材質，包括有利用各種不同製程步驟所形 成的鎢與鋁。雖然本發明係針對製作第一與第二連接線層 之間的內連線而進行說明的，但應要瞭解的是，此些說明 一般性所指的乃是在不同層次上的導體或導體區之間所 進行的連—接。本發明之方法並不要求導體爲建接線或者導 體必須要形成於互相鄰接的層次上，雖然本發明某些要點 之最佳應用確係在此種構造之中無誤。 雖然本發明已以較佳實施例說明揭示如上，然其描述 並非用以限定本發明，任何熟習此技藝者，在不脫離本發 明精神的情況下，當可作各種之更動與潤飾，因此本發明 之保護範圍當以後附申請專利範圍乙節所界定者爲準。 ί* I.--------Η裝 _— (请先閲讀背面之注意事項再填寫本頁)-C Printed by Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 0500TWF.doc / BL / Jonathan / 002 A7 __B7 V. Description of the invention (w) The surface of the exposed area on the surface. Preferably, the etch stop layer 34 should be made of an insulating material different from the dielectric layer 30. Preferably, the uranium inscribed barrier layer 34 is made of a material different from the insulating material layer 36 deposited on the etch barrier layer. The use of different materials allows the etching process through the multi-layer insulation structure to stop at each interface. Generally, the dielectric layer 30 is made of oxide sand, and the insulating material layer 36 deposited on the surface of the etch stop layer 34 is also silicon oxide. An appropriate material for the etch stop layer may therefore be nitrided sand. The etching process can have a high selectivity between silicon oxide and silicon nitride, especially when using high density such as inductively-coupled piasma or hel icon wave plasma During the paddle etching process. The silicon nitride etch stop layer 34 may be deposited by CVD to a thickness between approximately 200 and 1,000 A. Preferably, the barrier layer 34 should have a sufficient thickness to allow reliable use as a barrier for etching. The necessary thickness may be as small as 100 A 'depending on the thickness of the dielectric layer 36 through which the via hole is to be formed, and on the flatness of the surface of the dielectric layer 30 and the metal connection line 32. If the structure shown in FIG. 6 is better. The grinding process causes a significant step difference in the surface between the dielectric layer 30 and the metal connection line 32, and a thicker layer of silicon nitride may be required Ensure better complete step coverage. After each etching barrier layer is completed, an intermetal dielectric layer 36 can be used, for example, a silicon oxide PECVD process to form a dielectric hole 36 and then an intermetal dielectric layer 36 is used to form a via hole. Using a conventional lithography technique or equivalent method, a via etching mask is formed on the surface of the intermetal dielectric layer. Then etch and make Jieguo hole 38, 13 paper standards are applicable to the Chinese National Standard (CNS) A4 specifications (2 丨 ΟΧ ”7mm) (please read the $ item on the back and fill in this page). _Printed 0S00TWF.doc / BL / Jonathan / 002 A7 __B7 _Bai Bei Gong Consumers Cooperative Society _ 5. Description of the invention (丨 丨) It is best to use an anisotropic process in a high density plasma etching machine , Where the plasma is obtained by mixing gas sources including CF4, (: 2? 6 and 0) 2. The etching step should preferably be stopped at the etch stop layer 34. Then, use such as The process of anisotropic etching performed in 0 ^ 3 can etch the etching barrier layer in the via hole 38 and stop at the dielectric (silicon oxide) layer 30. The dielectric layer The hole uranium etch mask can be removed at this time, or before the uranium etch barrier layer is removed. Referring to FIG. 9, one of the adhesion or adhesion layers 40 is preferably deposited on the surface of the intermetal dielectric layer 36, And also deposited in the via 38. It is better to use this adhesive layer because of the increased The adhesion between the conductive plug and the first-layer connection line can reduce the possibility of lift-off. The adhesion layer 40 can be titanium alone, titanium nitride, titanium-tungsten alloy, tantalum nitride, or Other suitable materials, or a combination of the above materials, are usually deposited by physical vapor deposition to a thickness of hundreds of angstroms. Preferably, a metal plug 42 should be formed in the via hole and contact with the adhesive layer As shown in Figure 10. For example, a tungsten plug can be made by CVD using a WF6 gas source. In some cases, it is appropriate to use other materials including, for example, aluminum to make the plug 42 The current preferred tungsten CVD process can deposit tungsten on the entire adhesion layer. Thus, for devices whose adhesion layer covers a portion of the intermetal dielectric layer 36, it is best to use CMP Or etch back to remove the tungsten deposited on the surface of the dielectric layer 36 outside the via hole, and planarize the upper surface of the tungsten plug and the dielectric layer 36 to form Plug. In the preferred grinding process, the adhesive layer 40 is The surface of the mass layer 36 is removed. 14 ϋ Chidu applies the Chinese National Standard (CNS) ϋl # (210xi ^ PCT) (please read the $ item on the back and then fill in this page) _ ^ installed. Order A7 B7 '15517 0 50 0TWF.doc / BL / J〇nathan / 0 02 V. Description of the invention (No. 1) As a result, it is necessary to deposit a second adhesive layer 44 on the dielectric layer 36 and the plug 42 And the deposition process is similar to the first adhesive layer 40. The resulting structure is shown in Figure 11. After that, the process can be continued to make the second level connection line 'including the second layer of adhesive layer The second layer connecting line 46 in contact with 44 is as shown in FIG. 11. The process described here can be applied to a range of materials for the second layer of connections, including tungsten and aluminum formed using various process steps. Although the present invention has been described for making interconnects between the first and second connection line layers, it should be understood that these descriptions generally refer to conductors or conductors at different levels Connections between districts. The method of the present invention does not require conductors to be wired or the conductors must be formed on adjacent layers, although the best application of certain points of the present invention is indeed in such a configuration. Although the present invention has been described and disclosed in the above with preferred embodiments, the description is not intended to limit the present invention. Any person who is familiar with this skill can make various modifications and retouchings without departing from the spirit of the present invention. The scope of protection of the invention shall later be as defined in Section B of the scope of patent application. ί * I .-------- Η 装 _— (Please read the precautions on the back before filling this page)
'1T 經濟部中夬橾準局貝工消费合作社印製 +紙浪凡及通用宁國國家標準（CNS ) A4规格（210 X加公釐）'1T Printed by the Beigong Consumer Cooperative of the Ministry of Economic Affairs of the Central Committee of the Ministry of Economic Affairs + Paper Langfan and General Ningguo National Standard (CNS) A4 Specification (210 X plus mm)