4443 5 2 Α7 Β7 經濟部中央標準局貝工消费合作社印裝 五、發明説明（1 ) 本發明係有關於一種半導體裝置之多重内連線 (multilevel interconnect)製程，特別是有關於先形成接觸孔 (contact via)以及導線用溝槽(trench)，再同時填入導電材料 於上述接觸孔以及溝槽所形成的内連線製程。 隨著積體電路積集度的増加，使得晶片的表面無法提 供足夠的面積來製作所需的内連線時，為了配合MOS電晶 體縮小後所增加的内連線需求，必須形成多重（層）内連 線，才得以完成各元件之間的連接》 以下舉一例子說明多重内連線之其中一層的製作方 式，習知形成内連線的方式為：在己形成例如第1金屬導 線層的半導想基底上形成一第1金屬間介電層（inter_metal dielectric ; IMD)，然後，選擇性蝕刻上述第1金屬間介電 層’以形成一露出第1金屬導線層的接辞孔（contact via)， 接著’填入例如鎢等金屬材料於上述接觸孔，以形成金屬 插塞(Plug)。然後，沈積例如鋁等金屬材料層，其次，選 擇性蝕刻上述金屬材料層，用以形成第2金屬導線層（内連 線）圓案•然後，在第2金屬導線層上方形成第2金屬間介 電層。 然而’上述形成内連線的方式為利用兩次步驟分別形 成連通第1金屬導線層與第2金屬導線層的金屬插塞，以 及第2金屬導線層，製程較為複雜β 而且’伴随第2金屬導線層的尺寸越來越小，且配置 位置越來越接近，容易導致沈積第2金屬間介電層時，因 沈積不易所產生的孔洞問題。 本紙張尺度遙用中ΗΗ5Ν*率（CNS )从祕（2|Gx297公着） (請先閱讀背面之注意事項再填寫本頁)4443 5 2 Α7 Β7 Printed by the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, V. Description of the invention (1) The present invention relates to a multilevel interconnect process for a semiconductor device, and in particular, it relates to the formation of a contact hole first. (contact via) and a trench for a wire, and then a conductive material is filled into the contact hole and the interconnect formed by the trench at the same time. With the increase of the integration degree of integrated circuits, the surface of the chip cannot provide enough area to make the required interconnects. In order to meet the increased interconnect requirements after the MOS transistor is reduced, multiple layers must be formed. ) Interconnects can complete the connection between the components. ”An example is given below to explain how to make one layer of multiple interconnects. The conventional way to form interconnects is to form, for example, the first metal wire layer. A semi-conductor substrate is formed with a first inter_metal dielectric (IMD) layer, and then the first inter-metal dielectric layer is selectively etched to form a contact hole exposing the first metal wiring layer. via), and then 'fill in the above-mentioned contact hole with a metallic material such as tungsten to form a metal plug (Plug). Then, a metal material layer such as aluminum is deposited. Secondly, the above metal material layer is selectively etched to form a second metal wire layer (interconnection) circle. Then, a second metal space is formed over the second metal wire layer. Dielectric layer. However, the above-mentioned method of forming the interconnection is to form a metal plug connecting the first metal wire layer and the second metal wire layer and the second metal wire layer by two steps, and the manufacturing process is more complicated. The size of the wire layer is getting smaller and smaller, and the arrangement position is getting closer and closer, which easily leads to the problem of holes caused by the difficulty in depositing the second intermetal dielectric layer. The 5N * rate (CNS) of this paper is used remotely (from 2 | Gx297) (Please read the precautions on the back before filling this page)
4443 52 A7 —---~______BT^ 五、發明説明（2 ) 有鑑於此’本發明提供一種連通接觸孔之内連線的製 造方法’包括下列步驟：（幻在已形成導電區域的半導體基 底上形成一第1介電層；（b)在上述第1介電層上形成一覆 蓋層；（c)選擇性蝕刻上述覆蓋層以及第1介電層，用以形 成一露出上述導電區域的接觸孔；（d)在上述接觸孔内填入 一有機材料’該有機材料的上表面與上述覆蓋層的上表面 約為等高；（e)全面性形成一第2介電層，其覆蓋上述有機 材料表面以及上述覆蓋層；（f)在上述第2介電層上形成一 光阻層’用以露出上述第2介電層部分表面；（g)以上述光 阻層為罩幕’而施以非等向性蝕刻法蝕刻未被上述光阻層 遮蔽的第2介電層，直到露出上述覆蓋層為止，用以形成 一露出上述接觸孔的溝槽；（h)施以蝕刻法，用以去除上述 光阻廣以及填入上述接觸孔的有機材料；以及⑴填入一導 電材料於上迷溝槽以及接觸孔，用以形成連通接觸孔之内 連線。 為了讓本發明之上述目的、特徵、和優點能更明顯易 僅’下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 經濟部中央標準局貝工消合作社印掣 (請先閲讀背面之注意事項再填寫本頁) 困式之簡單說明： 第1圏至第10圖為本發明較佳實施例形成多重内連 線的方法製程剖面圖。 實施例 以下利用第1圖至第10圖，以說明本發明多重内連線 的製程。 本紙張尺度適用中家揉率（> Α4规格（210Χ297公着） 經濟部中央梯準局負工消费合作社印掣 4443 52 A7 B7 五、發明说明（3 ) 首先，請參照第1圖’在已形成導電區域12的半導體 基底10上形成一介電層14 ’上述導電區域12例如為金屬 導線層，而介電層14例如為利用化學氣相沈積法（CVD)所 形成的二氧化矽層。然後’利用化學氣相沈積法在上述介 電層14上形成一復蓋層16 ’本實施例的係採用厚度小於 1500 A的氮化矽材料為覆蓋層16 ’其可當作後續的蝕刻 停止層使用。 接著，請參照第2圖’利用微影製程(photolithography) 在上述覆蓋層16上方形成一露出部分覆蓋層16表面的光 阻層18。 然後，請參照第3圖’利用光阻層18為蝕刻罩幕，而 施以非等向性蝕刻法（anisotropic etching)依序蝕刻未被光 阻層18遮蔽的氮化矽覆蓋層16、以及介電層14，直到露 出導電區域12為止，而形成一接觸孔19。 其次，請參照第4圖，利用光阻層剝除液或蝕刻法去 除光阻層18，而形成如第4 ®構造。 接著，請參照第5圈，利用旋塗方式或化學氣相沈積 法填入一有機材料20於上述接觸孔19 ’上述有機材料20 延伸於復蓋層16上方。上述有機材料20例如光阻材料、 以碳為基質之低介電常數材料、含氟氧矽之材料、含聚合 物之玻璃材料、以及旋塗玻璃等。 然後，請參照第6圓，利用蝕刻法或是化學機械磨法 (CMP)去除位於覆蓋層16上方的有機材料，而留下接觸孔 内的有機材料20a，使其上表面與覆蓋層16的上表面約為 本紙張尺度適用中國國家梂率（CNS } A4规格（2丨0 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)4443 52 A7 ———- ~ ______ BT ^ V. Description of the Invention (2) In view of this, the present invention provides a method for manufacturing interconnect lines of contact holes, which includes the following steps: (Semiconductor substrate on which a conductive region has been formed) A first dielectric layer is formed thereon; (b) a cover layer is formed on the first dielectric layer; (c) the cover layer and the first dielectric layer are selectively etched to form a conductive layer exposing the conductive region; A contact hole; (d) an organic material is filled in the contact hole; the upper surface of the organic material is about the same height as the upper surface of the cover layer; (e) a second dielectric layer is formed comprehensively and covers The surface of the organic material and the cover layer; (f) forming a photoresist layer 'on the second dielectric layer to expose a part of the surface of the second dielectric layer; (g) using the photoresist layer as a cover' An anisotropic etching method is used to etch the second dielectric layer that is not covered by the photoresist layer until the cover layer is exposed to form a trench exposing the contact hole; (h) applying an etching method To remove the photoresistor and fill the contact hole An organic material; and a conductive material filled in the upper groove and the contact hole to form an interconnecting line connecting the contact hole. In order to make the above-mentioned objects, features, and advantages of the present invention more apparent, As a preferred embodiment, and in accordance with the attached drawings, the detailed description is as follows: Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) 1 to 10 are cross-sectional views of the manufacturing process of a method for forming multiple interconnects according to a preferred embodiment of the present invention. Embodiments The following uses Figures 1 to 10 to illustrate the process of multiple interconnects of the present invention. Applicable rate of Zhongjia Kneading (> A4 specification (210 × 297)) Printed by the Central Laboratories of the Ministry of Economic Affairs and Consumer Cooperatives 4443 52 A7 B7 V. Description of the invention (3) First, please refer to Figure 1 ' A dielectric layer 14 is formed on the semiconductor substrate 10 in the region 12. The conductive region 12 is, for example, a metal wire layer, and the dielectric layer 14 is, for example, a silicon dioxide layer formed by a chemical vapor deposition (CVD) method. A chemical vapor deposition method is used to form a cover layer 16 on the above-mentioned dielectric layer 14 ′ This embodiment uses a silicon nitride material with a thickness of less than 1500 A as the cover layer 16 ′, which can be used as a subsequent etching stop layer Next, please refer to FIG. 2 'Using a photolithography process to form a photoresist layer 18 on the cover layer 16 to expose a part of the surface of the cover 16. Then, refer to FIG. 3' Using the photoresist layer 18 as The mask is etched, and anisotropic etching is used to sequentially etch the silicon nitride cover layer 16 and the dielectric layer 14 that are not shielded by the photoresist layer 18 until the conductive area 12 is exposed to form One contact hole 19. Secondly, referring to Fig. 4, the photoresist layer 18 is removed by a photoresist stripping solution or an etching method to form a structure as in Fig. 4 ®. Next, referring to the fifth circle, an organic material 20 is filled in the contact hole 19 ′ by the spin coating method or the chemical vapor deposition method, and the organic material 20 extends above the cover layer 16. The above-mentioned organic material 20 is, for example, a photoresist material, a low dielectric constant material based on carbon, a material containing fluorooxysilane, a glass material containing a polymer, and spin-on glass. Then, referring to the sixth circle, the organic material located above the cover layer 16 is removed by an etching method or a chemical mechanical polishing (CMP) method, and the organic material 20a in the contact hole is left, so that the upper surface of the cover layer 16 and the cover layer 16 The upper surface is about the size of this paper, applicable to China's national standard (CNS} A4 size (2 丨 0 X 297 mm) (Please read the precautions on the back before filling this page)
4443 52 經濟部中央樣準局貝工消費合作社印袋 A7 B7 五、發明説明（4 ) 等1¾。 緊接著，請參第7圚，利用化學氣相沈積法，在覆蓋 層16的上方形成一介電層22，介電層22例如為含硼磷之 二氡化矽材料（硼磷矽玻璃-BPSG)所構成。然後，利用微影 製程在介電層22上方形成一露出部分介電層22表面的光 阻層24。 其次，請參照第8圖，利用光阻層24為蝕刻罩幕’而 施以非等向性蝕刻法蝕刻未被光阻層24所遮蔽的介電層 22 ’直到具有蝕刻停止作用之覆蓋層16為止，而形成一 與接觸孔19相連通的溝槽25。 接著’請參照第9圖，利用蝕刻法同時去除上述光阻 層24以及填入接觸孔19的有機材料20a，直到露出導電 區域12為止，上述蝕刻法適用的蝕刻氣體例如氧氣(〇2)。 最後，請參照第10囷，利用化學氣相沈積法或是物理 氣相沈積法全面性沈積一同時填入接觸孔19以及溝槽25 的導電材料26，上述導電材料26例如為鋁或銅金屬，用 以當作内連線（interconnect)，其中，填入接觸孔19的導電 材料具有導通兩層導線之間的功能，而填入溝槽25的導電 材料具有導線的功能。後續可視需要依據上述製程在導電 材料26上方形成金屬間介電層、接觸孔、溝槽，然後填入 第二層導電材料，而完成多重内速線製程。 發明功效 根據本發明之製造方法，蝕刻形成接觸孔19、以及溝 槽25後，再利用一次步驟同時填入導電材料於接觸孔19 本紙張尺度遑用中因两家標牟（CNS ) A4*jys· ( 2丨OX297公釐） (請先聞讀背面之注意事項再填寫本頁)4443 52 Printed bags for shellfish consumer cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs A7 B7 5. Description of the invention (4), etc. 1¾. Next, please refer to Section 7 to form a dielectric layer 22 over the cover layer 16 by using a chemical vapor deposition method. The dielectric layer 22 is, for example, a silicon oxide material containing borophosphorus (borophosphosilicate glass- BPSG). Then, a photoresist layer 24 is formed on the dielectric layer 22 over the dielectric layer 22 by using a lithography process. Next, referring to FIG. 8, the photoresist layer 24 is used as an etching mask, and the dielectric layer 22 ′ that is not masked by the photoresist layer 24 is etched by an anisotropic etching method until a cover layer having an etching stop effect 16 to form a trench 25 communicating with the contact hole 19. Next, referring to FIG. 9, the photoresist layer 24 and the organic material 20a filled in the contact hole 19 are simultaneously removed by an etching method until the conductive region 12 is exposed. An etching gas suitable for the above etching method is, for example, oxygen (02). Finally, referring to Section 10, a chemical vapor deposition method or a physical vapor deposition method is used to comprehensively deposit a conductive material 26 that simultaneously fills the contact holes 19 and the trenches 25. The conductive material 26 is, for example, aluminum or copper metal. Is used as an interconnect, wherein the conductive material filled in the contact hole 19 has the function of conducting between two layers of wires, and the conductive material filled in the trench 25 has the function of wires. According to the subsequent requirements, an intermetallic dielectric layer, a contact hole, and a trench may be formed on the conductive material 26 according to the above process, and then a second layer of conductive material is filled to complete a multiple internal speed line process. EFFECT OF THE INVENTION According to the manufacturing method of the present invention, after the contact holes 19 and the trenches 25 are formed by etching, a conductive material is simultaneously filled into the contact holes 19 in one step. Two paper standards (CNS) A4 * jys · (2 丨 OX297mm) (Please read the notes on the back before filling in this page)
A7 4443 52 B7 五、發明説明（5 ) 以及溝槽25，以當作内連線的製程又稱為dual damascene 製程，有別於習知以二次步驟分別形成導電材料於接觸孔 (如金屬插塞）以及溝槽的方法。其可達到簡化製程步驟且 降低成本的效果。 再者，根據本發明之製造方法，可避免習知形成金屬 間介電層時沈積不易所衍生的問題。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内，當可作更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。 {請先閲讀背面之注意事項再填寫本頁) 、1 經濟部中央梯準局男工消费合作社印$A7 4443 52 B7 V. Description of the invention (5) and groove 25. The process used as interconnects is also called the dual damascene process, which is different from the conventional method of forming conductive materials in contact holes (such as metal) in two steps. Plug) and groove method. It can achieve the effect of simplifying the process steps and reducing costs. Furthermore, according to the manufacturing method of the present invention, the problems caused by the difficulty in deposition when forming the intermetal dielectric layer can be avoided. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling this page) 、 1 Printed by the Male Workers Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs
• - I I 本紙張尺度適用中困困家標準< CNS ) A4规格（210X297公嫠）•-I I This paper size is applicable to the standard of the impoverished homes < CNS) A4 size (210X297cm)