3 798t\vr.doc/006 A7 B7 經浹部中央標準局只工消费合作社印製 五、發明説明（/ ) 本發明和在積體電路中遮蔽訊號線以防止雜訊干擾有 關，且特別是有關於一種在訊號線旁邊形成接地的遮蔽線 之方法。 在超大型積體電路（Very Large Scale Integration, VLSI) 中，金屬內連線（metal interconnect)結構是十分重要的一部 份。金屬內連線結構通常包括金屬導線和介層窗(vm)。介 層窗的用途爲連接上下兩層金屬導線。複雜的積體電路可 以包括好幾層金屬內連線的結構。在VLSI的金屬導線通 常用來傳遞數位訊號、類比訊號或偏壓電源(bias power)。 攜帶訊號的金屬線稱之爲訊號線。因爲在VLSI和極 大型積體電路（Ultra Large Scale Integration, ULSI)中，訊號 線之間的空間十分小，因此相鄰金屬線之間的電容耦合 (capacitive coupling)會製造出一些雜訊或互相干擾的（crosstalk)訊號 。當積體電路 的尺寸 —直下降，關鍵尺寸(critical dimension)也跟著變小，則相鄰訊號線之間的電容耦合和 雜訊之問題，也就越嚴重了。 一種用來遮蔽訊號線，以防止雜訊干擾的習知方法是 在訊號線的兩側提供遮蔽線。遮蔽線通常是和訊號線同時 在沈積蝕刻金屬內連線時完成的。然而，遮蔽線是和直流 電壓(Vss或Vcc)相接’所以和微弱的交流訊號比起來，遮 敝線是「fee地」的，即父流接地（AC grounded)。因此，遮 蔽線不和任何輸入或輸出用的半導體元件連接。在此習知 技術中’每條訊號線需要兩條和訊號線絕緣的遮蔽線才能 達成隔絕雜訊的目的’因此需要很大的面積。訊號線和遮 4 (1¾先閱讀背而之注意事項/}填寫本頁) 、-0 本紙张尺度適用中國國家標準（)以現格（2丨Ox ) Α7 137 3798t\vi'.d〇c/^°6 五、發明説明（上） 蔽線之間所需的絕緣空間大小，主要是受限於微影製程的 解析度。例如，在0.25 μπι的互補式金氧半電晶體(CMOS) 技術中’訊號線和遮蔽線之間的間隔距離約0.3 μηι°而且 因爲訊號線和接地的遮蔽線之間的電容耦合之故，兩者之 間的電容也隨著"元件的尺寸降低而增加° 在要#胃速 的電路中’特別不喜歡和地線之間的電$@合° 第1圖係繪示習知遮蔽方法的等角示意圖。半導體基 底101可以是下列各項的組合：矽基底、電晶體元件、邏 輯元件、電容元件、或任何半導體元件。這些元件需要和 其他半導體元件或輸出/輸入電路互相電性連接。習知中’ 介電層103是用來隔離不同層的半導體電路。介電層1〇3 通常爲層間介電層（interlayer dielectric, ILD)或金屬間介電 層（intermetal dielectric，IMD)。介電層103可由硼憐砂玻璃 (BPSG)、用矽酸四乙酯（TEOS)爲氣源所沈積的氧化矽、磷 矽玻璃（PSG)、二氧化矽、旋塗式玻璃（SOG) '氮化矽、氧 化鋁、氧化鉅等單層物質所構成，或這些物質層的任意組 合。對本發明來說，介電層103通常指的是氧化矽。 在介電層103之上爲金屬內連線的結構’材質爲可導 電的金屬，例如鋁、鎢、多晶矽或銅。內連線結構包括金 屬導線組成的網路和介層窗，這些內連線經由和在其下層 的接觸窗來連接半導體元件。 在習知中，金屬內連線至少包括訊號線105和遮蔽線 107。遮蔽線107是經由交流電的方式接地，而訊號線丨05 則攜帶元件之間的溝通電訊。如以上所述，遮蔽線丨07和 ,I裝------訂------線 (計先閱讀背而之注意事項洱填寫本頁) 經漪部中央標準局另工消费合作社印％ 本紙張尺度適用中國國家標率（CNS ) ( 2丨0X21^公公> 3798twf.(joc/〇〇6 Α7 Β7 經濟部中央標準局只工消费合作社印^ 五、發明説明（彡） 訊號線105是彼此相鄰的。通常遮蔽線107和訊號線105 之間的空間會比微影的關鍵尺寸稍大一點。而且在金屬內 連線的結構製作完成後，在遮蔽線1〇7和訊號線1〇5的上 $還有一層絕緣用的氧化矽層。因此遮蔽線107和訊號線 1〇5之間的空間是被氧化矽所塡滿的。 医1此本發明的目的就是在提供一種遮蔽線的製造方 法’使遮蔽線可以和訊號線更靠近，而且具有更低的電容 稱合。 根據本發明之目的，提出一種半導體元件中靠近訊號 '線的遮蔽線之製作方法。本方法包括在訊號線之上沈積一 層氧化矽層，回蝕氧化矽層，在訊號線的側壁形成氧化矽 間隙壁。在訊號線和間隙壁的上方沈積一層金屬，去除金 屬層的頂端部份，使得剩下的金屬層表面低於訊號線的上 表面。剩下的金屬層形成遮蔽線，再移除氧化矽間隙壁。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖係繪示習知一種積體電路中之遮蔽訊號線的技 術； 第2〜7圖係繪示本發明之一較佳實施例，一種半導 體積體電路中之遮蔽線的製造流程剖面圖。 圖式之標記說明： 101、201 :基底 6 張尺心用巾® CNS) η -)................ ----------裝------訂------線 ("先閱讀背而之注意事項洱填寫本頁) 3798t\vr.doc/006 A7 3798t\vr.doc/006 A7 短濟部中央標莩局只工消费合作社印聚 Η 7 ------------------ 五、發明説明（y) 103 :介電層 105、205 :訊號線 107、211 :遮蔽線 203 :氧化矽層 207 :硼磷矽玻璃 209 :間隙壁 213 :空氣溝渠 實施例 S靑參照桌2〜7 Η ,其繪不本發明之一較佳實施例’ 一種半導體積體電路中之遮蔽線的製造流程剖面圖。請參 照第2圖，在基底201之上形成絕緣的氧化砂曾203。基 底201可包含各式各樣的半導體元件，元件彼此之間需要 互相電性連接’而且實質上和上述第1圖的基底1〇1類似。 同樣的，氧化矽層203爲絕緣的，用來在積體電路中隔絕 不同的金屬導線。 在氧化矽層203的上方形成一層金屬層，再利用習知 的微影蝕刻製程來形成訊號線205。例如，訊號線205的 製作方法可先沈積一層鋁、鎢或銅在氧化矽層203的上方， 在金屬層上方再形成一層圖案化的光阻層（圖上未示出）， 以此光阻層爲罩幕來進行蝕刻的步驟。如一般習知所熟知 的情況，這層金屬層還會將氧化矽層203中的介層窗開口 (圖上未示出）塡滿，讓訊號線205和位在其下方的半導體 元件電性相連。而訊號線205本身的材質包括鋁、鎢、多 晶矽或銅。 7 本纸张尺度適/f]中國國家椋準（CNS ) Λ4ΪΚΜ, (210X297^# ) --裝------訂------線 ' . (对先閱讀背而之注意事項再填寫本頁) 經漪部中央標準局貝工消費合作社印¾ 3 798twf.doc/006 -- --- - ·'——----- I'· II . _ 五、發明説明（r ) 接著，請參照第3圖，利用電漿化學氣相沈積法 (PECVD)，在400 °C下沈積一層約2000 A厚的硼磷矽玻璃 207。可再使用快速熱製程（rapid thermal process, RTP)來密 實化硼磷矽玻璃207。 再來，請參照第4圖，對207進行乾蝕刻步驟，在每 條訊號線205的側壁上形成間隙壁209的構造。乾蝕刻步 驟例如可用反應性離子蝕刻法（reactive ion etching, RIE)來 進行之。不過，就熟知此技藝者來說，並不是所有的訊號 線205需要遮蔽。在此種情況下，可利用罩幕保護不需要 遮蔽的訊號線205，就不會在這些訊號線205的側壁上形 成硼磷矽玻璃間隙壁209。因此，第4圖主要是顯示積體 電路中需要遮蔽訊號線205的區域。 請參照第5圖，在整個結構的上方沈積金屬層211。 金屬層211最佳爲約5000 A厚，但是至少要和需要遮蔽的 訊號線205之厚度一樣。此外，金屬層211的材質較佳爲 金屬鎢，但是也可使用其他的導電材質。至於金屬層211 的形成方法，因爲化學氣相沈積法對於微小空隙的塡溝能 力較其他的方法爲佳，如物理氣相沈積法，所以較佳爲利 用化學氣相沈積法來進行共形（conformal)沈積，而金屬鎢 爲其中塡溝能力非常高的一種材質。 然後，請參照第6圖，對金屬層211進行化學機械硏 磨法（chemical mechanical polishing, CMP)，並稍微有點過 鈾刻，至間隙壁209的頂端再停止，使金屬層211的表面 低於訊號線205的上表面。若訊號線205和金屬層211是 8 本紙張尺度適用中國國家枕準（CNS ) Λ4規彳Μ 公公) 誚先閲讀背面之注意事項再填寫本頁) 裝 線 3 7 9 8 l w Γ. cl oc/〇〇6 A7 H7 五、發明説明（6 ) 由不同的導電材質所組成的，則二者的硏磨速率會稍微有 些不同。如此可保證在後續欲去除間隙壁209之時，間隙 壁209是暴露出來的，以利將其完全去除之。所以此硏磨 步驟最重要是暴露出間隙壁209的上端。在後續步驟當中 將會瞭解唯有如此才能將間隙壁209完全去除。 硏磨步驟完成之後，形成的遮蔽線211和訊號線205 彼此是互相絕緣的。而且遮蔽線211和訊號線205彼此是 以間隙壁209來分隔的。 請參照第7圖，利用對硼磷矽玻璃具有高度選擇性的 蝕刻方法，移除間隙壁209。此高選擇性的蝕刻方法較佳 爲利用低壓HF氣體來蝕刻硼磷矽玻璃構成的間隙壁209， 此方法對硼磷矽玻璃間隙壁209和氧化矽層203的選擇比 局達約 1000 左右’請黎照”Gas Phase Selective Etching of Native Oxide55 (Mike et al. IEEE Electron Device, 37(1), p. 107-115，1990)。所以硼磷矽玻璃間隙壁209可以在氧化矽 層203、訊號線205和遮蔽線211完全不被破壞的情況下 將其移除之。此低壓HF蝕刻技術的細節在”A New Cylindrical Capacitor Using Hemispherical Grain Si (HSG-Si) for 256 Mb DRAMs”（Watanabe 92-259，1992)中 有討論之。 遮蔽線211則經由習知一般交流電的方式接地，而訊 號線205和遮蔽線211之間爲比氧化矽介電係數還低的空 氣，使訊號線205和遮蔽線211的電容耦合程度大幅降低。 最後，如一般的狀況，在訊號線205和遮蔽線211的 9 ------------------- -_____ '埼用中國國家榡準（CNS〉Λ4岘梢（210x2㈧公坫） ---------lu-h------訂------線 (誚先間讀背面之注意事項孙填寫本頁) 3 7 98uvt，.d〇c/006 A7 3 7 98uvt，.d〇c/006 A7 經漓部中央標準扃只工消费合作社印製 Η 7 一____ 五、發明説明（7 ) 上方沈積一層絕緣層’例如氮化砂或氧化砍。形成适層絕 緣層的方法，必須選擇塡溝能力較差的方法，以免將訊號 線2 0 5和遮敝線211之間的空Μ溝渠213填滿。 由上述本發明較佳實施例可知，應用本發明具有下列 優點。第一、遮蔽線211爲自動對準至訊號線205 ’不需 要用任何的先進微影技術。第二、訊號線205和遮蔽線211 之間的間隔非常小。第三、空氣溝渠2Π提供非常低的電 容，使得訊號線205和遮蔽線211之間的電容耦合得以降 低。 訊號線的材質可以爲CMOS中所常使用的導電材料’ 例如多晶矽、金屬矽化物、鎢、鋁、銅等等。遮蔽線的材 質一般也和訊號線的材質相同，只是一般會受限於容易使. 用化學氣相沈積法所形成的材質，如多晶矽、鎢、銅等。 最後本發明的方法可應用於多重金屬內連線的製程上’提 供更多的遮蔽效應給金屬內連線。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 用中國國家榡準（CNS ) ( 21 Ox 297,：,) I I i . I— I I -IT111 (誚先閱讀背而之注意事項再填寫本頁)3 798t \ vr.doc / 006 A7 B7 Printed by the Central Standards Bureau of the People ’s Republic of China and printed by a consumer cooperative. V. Description of the invention (/) This invention is related to shielding signal lines in integrated circuits to prevent noise interference, and in particular It relates to a method of forming a grounded shield line beside a signal line. In very large scale integration (VLSI), metal interconnect structure is a very important part. Metal interconnect structures typically include metal wires and vias (vms). The purpose of the via is to connect the upper and lower metal wires. Complex integrated circuits can include several layers of metal interconnect structures. Metal wires in VLSI are commonly used to carry digital signals, analog signals, or bias power. The metal wires that carry signals are called signal wires. Because in VLSI and Ultra Large Scale Integration (ULSI), the space between signal lines is very small, the capacitive coupling between adjacent metal lines will create some noise or mutual interference. Crosstalk signals. As the size of the integrated circuit decreases straight down and the critical dimension decreases, the problems of capacitive coupling and noise between adjacent signal lines become more serious. A known method for shielding signal lines to prevent noise interference is to provide shielding lines on both sides of the signal lines. The shield line is usually completed at the same time as the signal line when the inner wiring of the deposited metal is etched. However, the shielded line is connected to a DC voltage (Vss or Vcc) ’, so compared to a weak AC signal, the shielded line is“ fee ground ”, that is, AC grounded. Therefore, the shield line is not connected to any input or output semiconductor element. In this conventional technique, 'each signal line needs two shielded lines insulated from the signal line to achieve the purpose of isolating noise' and therefore requires a large area. Signal line and cover 4 (1¾Read the back notice /} Fill this page), -0 This paper size applies the Chinese national standard () to the standard (2 丨 Ox) Α7 137 3798t \ vi'.d〇c / ^ ° 6 V. Description of the Invention (above) The size of the insulation space required between the shield wires is mainly limited by the resolution of the lithography process. For example, in the 0.25 μπm complementary metal-oxide-semiconductor (CMOS) technology, the separation distance between the signal line and the shielded line is about 0.3 μηι and because of the capacitive coupling between the signal line and the grounded shielded line, The capacitance between the two also increases with the decrease in the size of the element. In the circuit that requires # stomach speed, I do n’t particularly like the electricity between the ground and the ground. $ @ 合 ° Figure 1 shows the conventional shielding Isometric illustration of the method. The semiconductor substrate 101 may be a combination of the following: a silicon substrate, a transistor element, a logic element, a capacitor element, or any semiconductor element. These components need to be electrically connected to other semiconductor components or output / input circuits. The conventional dielectric layer 103 is used to isolate semiconductor circuits of different layers. The dielectric layer 103 is usually an interlayer dielectric (ILD) or an intermetal dielectric (IMD). The dielectric layer 103 may be made of borosilicate glass (BPSG), silicon oxide deposited using tetraethyl silicate (TEOS) as a gas source, phosphosilicate glass (PSG), silicon dioxide, and spin-on-glass (SOG) '' It is composed of a single layer of silicon nitride, aluminum oxide, or oxide, or any combination of these layers. For the present invention, the dielectric layer 103 is generally referred to as silicon oxide. The structure of a metal interconnect on the dielectric layer 103 is made of a conductive metal, such as aluminum, tungsten, polycrystalline silicon, or copper. The interconnect structure includes a network of metal wires and vias, and these interconnects connect semiconductor elements via contact windows below it. In the prior art, the metal interconnect includes at least a signal line 105 and a shield line 107. The shielded wire 107 is grounded by means of AC power, and the signal wire 05 carries communication telecommunications between components. As mentioned above, the shielding line 丨 07 and, I installed -------- order ---- line (counting the precautions before reading the first 洱 fill in this page) by the Central Bureau of Standards and other consumption Cooperative cooperative seal% This paper standard applies to China's National Standards Rate (CNS) (2 丨 0X21 ^ Public Father > 3798twf. (Joc / 〇〇6 Α7 Β7) Printed by the Central Standards Bureau of the Ministry of Economic Affairs only for consumer cooperatives ^ 5. Description of the invention (彡) The signal line 105 is adjacent to each other. Generally, the space between the shield line 107 and the signal line 105 is slightly larger than the key size of the lithography. After the metal interconnect structure is completed, the shield line 107 There is also a layer of silicon oxide for insulation on the signal line 105. Therefore, the space between the shielding line 107 and the signal line 105 is filled with silicon oxide. The purpose of the present invention is to A method for manufacturing a shielded wire is provided, so that the shielded wire can be closer to the signal wire and has a lower capacitance. According to the purpose of the present invention, a method for manufacturing a shielded wire near a signal wire in a semiconductor device is proposed. The method includes depositing a silicon oxide layer on a signal line. The silicon oxide layer is etched to form a silicon oxide spacer on the sidewall of the signal line. A layer of metal is deposited on the signal line and the spacer to remove the top portion of the metal layer so that the surface of the remaining metal layer is lower than the upper surface of the signal line The remaining metal layer forms a shielding line, and then the silicon oxide spacer is removed. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and cooperates with all The drawings are described in detail as follows: Brief description of the drawings: Figure 1 shows a conventional technique for shielding signal lines in integrated circuits; Figures 2-7 show a preferred implementation of the present invention. For example, a cross-sectional view of the manufacturing process of a shielded line in a semiconductor integrated circuit. Marking description of the drawings: 101, 201: 6 base towels on the base ® CNS) η-) ......... ... ---------- install ------ order ------ line (" read the precautions first and fill in this page) 3798t \ vr. doc / 006 A7 3798t \ vr.doc / 006 A7 The Central Standards Bureau of the Ministry of Economy, Trade and Industry Cooperatives, Yin JuΗ 7 ------------------ V. Description of the invention ( y) 103: Dielectric Layers 105 and 205: signal lines 107 and 211: shield lines 203: silicon oxide layer 207: borophosphosilicate glass 209: partition wall 213: air trench embodiment S 靑 Refer to Tables 2 to 7Η, which does not depict one of the inventions Preferred Embodiment A cross-sectional view of a manufacturing process of a shield line in a semiconductor integrated circuit. Referring to FIG. 2, an insulating oxide sand 203 is formed on the substrate 201. The substrate 201 may include various kinds of semiconductor elements, and the elements need to be electrically connected to each other 'and are substantially similar to the substrate 101 of the above-mentioned FIG. 1. Similarly, the silicon oxide layer 203 is insulated to isolate different metal wires in the integrated circuit. A metal layer is formed on the silicon oxide layer 203, and the signal line 205 is formed by a conventional lithography etching process. For example, the method of manufacturing the signal line 205 may be to deposit a layer of aluminum, tungsten, or copper on the silicon oxide layer 203, and then form a patterned photoresist layer (not shown in the figure) over the metal layer to use the photoresist The layer is a mask to perform the etching step. As is well known in the general practice, this metal layer will also fill the interstitial window openings (not shown) in the silicon oxide layer 203, so that the signal lines 205 and the semiconductor elements located below them are electrically conductive. Connected. The material of the signal line 205 itself includes aluminum, tungsten, polysilicon or copper. 7 The size of this paper is suitable / f] China National Standards (CNS) Λ4ΪΚΜ, (210X297 ^ #) --installation ------ order ------ line '. (Notes for reading first (Fill in this page again) Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Yi ¾ 3 798twf.doc / 006-----· '——----- I' · II. _ 5. Description of the invention (r ) Next, referring to Figure 3, a layer of borophosphosilicate glass 207 with a thickness of about 2000 A is deposited at 400 ° C by plasma chemical vapor deposition (PECVD). A rapid thermal process (RTP) can then be used to compact the borophosphosilicate glass 207. Next, referring to FIG. 4, a dry etching step is performed on 207 to form a structure of the partition wall 209 on the side wall of each signal line 205. The dry etching step can be performed by, for example, reactive ion etching (RIE). However, to those skilled in the art, not all signal lines 205 need to be shielded. In this case, a shield can be used to protect the signal lines 205 that do not need to be shielded, so that a borophosphosilicate glass spacer 209 is not formed on the side walls of these signal lines 205. Therefore, Fig. 4 mainly shows the area of the integrated circuit that needs to shield the signal line 205. Referring to FIG. 5, a metal layer 211 is deposited over the entire structure. The metal layer 211 is preferably about 5000 A thick, but at least as thick as the signal line 205 to be shielded. In addition, the material of the metal layer 211 is preferably metal tungsten, but other conductive materials may be used. As for the method of forming the metal layer 211, the chemical vapor deposition method is better than other methods for the trenches with small voids, such as physical vapor deposition, so it is better to use chemical vapor deposition for conformal ( conformal), and metal tungsten is a material in which trenching ability is very high. Then, referring to FIG. 6, a chemical mechanical polishing (CMP) method is performed on the metal layer 211, and the uranium is slightly etched, and then stopped at the top of the spacer 209, so that the surface of the metal layer 211 is lower than The upper surface of the signal line 205. If the signal line 205 and the metal layer 211 are 8 sheets of paper, the Chinese National Pillow Standard (CNS) Λ4 Rule 彳 彳)) 诮 Read the precautions on the back before filling in this page) Installation line 3 7 9 8 lw Γ. Cl oc / 〇〇6 A7 H7 V. Description of the invention (6) Composed of different conductive materials, the honing rate of the two will be slightly different. This can ensure that when the spacer wall 209 is to be removed subsequently, the spacer wall 209 is exposed to facilitate its complete removal. Therefore, the honing step is most important to expose the upper end of the spacer 209. In the next steps, it will be understood that only in this way can the spacer 209 be completely removed. After the honing step is completed, the formed shielding lines 211 and the signal lines 205 are insulated from each other. The shielding line 211 and the signal line 205 are separated from each other by a partition wall 209. Referring to FIG. 7, the spacer 209 is removed by using a highly selective etching method for borophosphosilicate glass. This highly selective etching method is preferably to use a low-pressure HF gas to etch the partition wall 209 made of borophosphosilicate glass, and the selection ratio of this method to the borophosphosilicate glass partition wall 209 and the silicon oxide layer 203 is about 1,000. Please Li Zhao "Gas Phase Selective Etching of Native Oxide55 (Mike et al. IEEE Electron Device, 37 (1), p. 107-115, 1990). Therefore, the borophosphosilicate glass spacer 209 can be used in the silicon oxide layer 203, signal Line 205 and shield line 211 are removed without damage. Details of this low-voltage HF etching technology are in "A New Cylindrical Capacitor Using Hemispherical Grain Si (HSG-Si) for 256 Mb DRAMs" (Watanabe 92- 259, 1992). The shielded wire 211 is grounded by the conventional AC method, and the signal line 205 and the shielded wire 211 are air with a lower dielectric constant than silicon oxide, so that the signal wire 205 and the shielded The degree of capacitive coupling of the line 211 is greatly reduced. Finally, as in the general situation, the signal line 205 and the shield line 211 are 9 ------------------- -_____ 'Use China National Standards (CNS> Λ4 Daxuan (210x2㈧ 公 坫) --- ------ lu-h ------ order ------ line (read the notes on the back first and fill in this page) 3 7 98uvt, .d〇c / 006 A7 3 7 98uvt, .d〇c / 006 A7 is printed by the central standard of the Ministry of Justice (printed by the workers' cooperatives) 7 ______ V. Description of the invention (7) An insulating layer is deposited on the top, such as nitrided sand or oxidized chop. Forms a suitable layer For the insulating layer method, a method with a poor trenching ability must be selected so as not to fill the empty M trench 213 between the signal line 205 and the shielding line 211. As can be seen from the foregoing preferred embodiments of the present invention, the present invention has The following advantages: First, the shielding line 211 is automatically aligned to the signal line 205 'does not require any advanced lithography technology. Second, the interval between the signal line 205 and the shielding line 211 is very small. Third, the air trench 2Π provides very low capacitance, which reduces the capacitive coupling between the signal line 205 and the shield line 211. The material of the signal line can be a conductive material commonly used in CMOS 'such as polycrystalline silicon, metal silicide, tungsten, aluminum, copper Etc. The material of the shield line is generally the same as the material of the signal line, but it is generally limited Easy to use. Materials formed by chemical vapor deposition, such as polycrystalline silicon, tungsten, copper, etc. Finally, the method of the present invention can be applied to the process of multi-metal interconnects to provide more shielding effects for metal interconnects. . Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. Use China National Standards (CNS) (21 Ox 297,:,) I I i. I— I I -IT111 (Please read the precautions before filling in this page)