4391 82 A7 _ 5。。3:上 d〇C，j__B7_ 五、發明說明（/ ) 本發明是有關於一種介電層之製造方法，且特別是有關 Μ雙金屬鑲嵌內連線之具有低介電常數之介電層的 _^；^法’此介電層可以降低導線之間以及多重金屬內連 線之間的電阻電容時間延遲。 在超大型積體電路（ULSI)的製程上，可以在1至2平方 公分面積的矽表面上配置數量多達數十萬的電晶體。並 £ ’胃7增加積體電路的積集度，將提高連接各個電晶體 或是其他元件的金屬線之密度。所以，以往單一金屬層的 設:計’將無法完成整個積體電路的連線工作，兩層以上的4391 82 A7 _ 5. . 3: above doc, j__B7_ V. Description of the invention (/) The present invention relates to a method for manufacturing a dielectric layer, and particularly to a dielectric layer with a low dielectric constant, which is related to an M-bimetal damascene interconnect. _ ^; ^ Method 'This dielectric layer can reduce the resistance-capacitance time delay between wires and between multiple metal interconnects. In the ultra-large integrated circuit (ULSI) process, hundreds of thousands of transistors can be arranged on a silicon surface with an area of 1 to 2 square centimeters. In addition, the increase in the integration degree of the integrated circuit will increase the density of the metal wires connecting the transistors or other components. Therefore, in the past, the design of a single metal layer could not complete the wiring work of the integrated circuit.
AilJlf受計，便逐漸成爲許多積體電路製造所必需採用的 方'式°以邏輯電路爲例，目前積體電路所使用的金屬已達 六層。 隨著元件尺寸的縮小，相鄰之導線的間距亦隨之縮小， 若1做爲導線間之電性隔離的介電層之介電常數無法有效 降低’在窄小的空間中，平行的導線會在相鄰接的導線間 產生不必要的電容式（capacitive)與電感式（inductive) 奉禹接（couplmg)，造成導線之間相互干擾，導致導線之間 的電阻-電谷時間延遲（RC Time Del ay)增加，特別是在經 由平行導線進行較高的傳輸資料速率時，電容式與電感式 稱接將降低資料的傳輸速率，而以此方式增加能量的耗損 量’同時亦限制了元件的效能。 習知雙金屬鑲嵌製程中，利用介電常數較小之材質，例 如是氟化砂酸玻璃（fluorosilicate glass，FSG)，來形 成金屬線間介電層（inter-metal dielectric layer)以及 3 {請先閱讀背面之注意事項再填窝本頁)AilJlf has gradually become the formula necessary for many integrated circuit manufacturing. Taking logic circuits as an example, the metal used in integrated circuits has reached six layers. As the component size shrinks, the distance between adjacent wires also decreases. If 1 is used as the dielectric constant of the dielectric layer for the electrical isolation between the wires, the dielectric constant cannot be effectively reduced. 'In a small space, parallel wires Will cause unnecessary capacitive and inductive couplmg connections between adjacent wires, causing mutual interference between the wires, resulting in the resistance-electric valley time delay between the wires (RC Time Del ay) increase, especially at higher data transmission rates via parallel wires. Capacitive and inductive weighing will reduce the data transmission rate and increase the energy consumption in this way. It also limits the components. Performance. In the conventional bimetal damascene process, a material with a smaller dielectric constant, such as fluorosilicate glass (FSG), is used to form an inter-metal dielectric layer and 3 {Please (Read the notes on the back before filling in this page)
τ · n I— f I 經濟部智慧財產局員工消費合作社印製 本紙張Μ翻中國國家標準（CNS)M規格（21〇 X 297公楚） 4391 82 5003twf. doc/006 A7 B7 五、發明說明（Λ_) 金屬線內介電層（intra-metal dieiectric layei.}，众 低金屬導線層之間以及導線之間的RC時間延遲。然^降 氟化政酸玻璃之介電常數約爲3 5，僅較氧化物之介〜 數（4.1)略低15%，因此RC時間延遲的降低幅度亦受到^ 制。此外，其他低介電常數之材料，包括有機介電^ ^ 及無機介電材料，在目前介電常數低於3的要求下，其j 用於產品上之製程技術仍未臻於成熟，因此亦少做爲現二 積體電路中之介電層材料。 … ^ 因此本發明就是在提供一種雙金屬鑲嵌內連線之介電 層的製造方法’其方法簡述如下：首先提供一基底。接著， 於基底上形成一雙重金屬鑲嵌結構，其中雙金屬鑲嵌結構 中，形成有位於基底上方之第一導線與第二導線以及位於 第一導線與第二導線之間的第一介電層。之後，去除第一 介電層’接著’於基底上方形成共形之阻障頂蓋層'續之， 於阻障頂蓋層上，形成〜層第二介電層，在第二介電層、 第-與第—導線所界定的區域中形成一空氣間隙。繼之， 於第一介電層上，形成〜平坦化之第三介電層。 依fk本發酬較佳簡例，其巾，第二介賴係爲階梯 覆盖目匕力較差之介電層，其包括由電漿加強型化學氣相沉 積法所形成的無機介電材料層。 本發明中，在基底上形成雙金屬鑲嵌內連線結構之後， 去除第與第一導線之間的第一介電層，接著，以階梯覆 蓋性較差的第二介電層，覆蓋第一與第二導線之間的空 間，並在此空間中形成空氣間隙，由於空氣間隙中之空氣 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297 經濟部智慧財產局員工消費合作社印製 4391 82 A7 5003twf.doc/006 B7 五、發明說明（$ ) 的介電常數約爲1.0，所以可有效降低導線之間的電容式 與電感式耦接，以及RC時間延遲，減少導線之間的相互 雜訊干擾程度，同時降低多重金屬內連線之間的介電常 數，因此，多重金屬內連線之間的RC時間延遲以及干擾 亦會降低，進而提高資料傳輸速度以及元件性能。 .爲讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下= 圖式之簡單說明： 第1A圖至第1E圖所示，爲根據本發明一較佳實施例之 一種雙金屬鑲嵌內連線之介電層的製造方法。 其中，各圖標號與構件名稱之關係如下： 100 :基底 102，122a，124a :導線 104，1Q8，134，140 :介電層 106 :蝕刻終止層 110 :硬罩幕層 120 :圖案化光阻 122，124 :溝渠 126 :介層窗開口 126a :介層窗插塞 128，128a :阻障層 130 :導電層 132 :阻障頂蓋層 5 本紙張尺度適用中國國家標準（CNS)Al規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ----訂----- T. 經濟部智慧財產局員工消費合作杜印製 4 3 91 82」 A7 50 03tvvf.doc/006 ㈤ 五、發明說明（令） 134a :懸突結構 136 :空氣間隙 實施例 第1A圖至第1E圖所示’爲根據本發明一較佳實施例之 一種雙金屬鑲嵌內連線之介電層的製造方法。 請參照第1A圖，首先，提供一基底1〇〇，在其上已形成 有導線102以及元件（未繪出）等結構。接著，在基底1〇0 上形成一層介電層104，其中，介電層104例如是以旋轉 塗佈（spin coating)的方.式所形成之有機介電材料層，或 是以化學氣相沉積法所形成之氟氧化矽層、多孔隙氧化矽 層或是一般使用的無機材料層。 接著，於介電層104上形成一鈾刻終止層106，此蝕刻 終止層106對於介電層104具有較大的蝕刻選擇比，其例 如是以化學氣相沉積法所形成之氮氧化矽層、氮化矽層、 碳化砂層或是氧化砍層。 之後，定義蝕刻終止層106，以在對應於導線102之蝕 刻終止層106中形成一開口（未繪示），並裸露出位於導線 102上方之部分介電層1〇4。 續之，於蝕刻終止層106以及裸露之介電層104上，形 成一介電常數較低之介電層108，此介電層108對於蝕刻 終止層106具有較大的蝕刻選擇比，其之材質係爲有機高 分子介電材料，較佳的有機高分子介電材料包括A11 i e d Signal 之 FLARE(fluonirated poly(arylene ethers))、 6 (請先閱讀背面之注意事項#;填寫本頁) 裝 訂·---- f. 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4391 82 ' 5003twf.doc/006 五、發明說明（女） BCB (benzocyclobutene)、非晶系碳（amorphous carbon) 或是Dow Chemica丨之SILK，且其形成方式例如是旋塗法^ 繼之，於介電層108上形成一層硬罩幕層11〇，此硬罩 幕層110例如是以化學氣相沉積法所形成之氮氧化矽層、 氧化矽層或是氮化矽層。之後，於硬罩幕層110上形成一 層圖案化光阻120，並裸露出部分硬罩幕層11〇。 接著，於硬罩幕層110與介電層108中形成溝渠122與 124，以及於蝕刻終止層106與介電層104中形成與溝渠 124相連，並裸露出基底中欲導通之導線1〇2的介層窗開 口 126 ° 其中，形成溝渠122與124之方法包括以蝕刻終止層106 爲蝕刻終點，去除部分硬罩幕層110以及介電層108，直 到裸露出部分蝕刻終止層106之表面，而形成介層窗開口 126之方法係由蝕刻終止層106之開口（未繪示）去除部分 介電層1(M，直到裸露出部分導線102之表面。 續之，請參照第1B圖，去除圖案化光阻120。接著，於 基底100上方形成一層共形的阻障層128，此阻障層128 之材質包括氮化钽、鉬金屬、氮化鎢或是氮化鈦。此阻障 層128係保護介電層108與104,於後續在溝渠122與124 以及介層窗開口 126中塡滿導電材料時，不會受到導電材 料的擴散侵襲，造成元件電性問題，並藉此可以提高導電 材料與介電層104與106之間的黏著性。 之後，於阻障層128上形成一層導電層130，且此導電 層130塡滿溝渠122與124以及介層窗開口 126。其中， 7 (請先閱讀背面之注意事項再填寫本頁) 裝------ 訂----- 本紙張尺度適用·中國國家標準（CNS)A..l規格（210 x 297公釐） 經濟部智慧財產局員工消費合作社印製 4 3 918 2、 A7 5003twf.doc/006 五、發明說明（έ) 導電層130之材質包括金屬銅或是銅合金。 繼之，請參照第1C圖，去除部分導電層130、阻障層 128以及硬罩幕層110，直到裸露出介電層108之表面， 以將溝渠122與124以及介層窗開口 126中所殘留的阻障 層標示爲阻障層128a，且在溝渠122與124中分別形成導 線122a與124a，以及在介層窗開口 126中形成介層窗插 塞126a等雙金屬鑲嵌結構。 其中，導線124a與102係經由介層窗插塞126a形成電 性耦接。而去除部分導電層130、阻障層128以及硬罩幕 層110之方法包括化學機械硏磨法。 由於介電層108上有硬罩幕層110之保護，因此可防止 在進行去除部分導電層130時，導電層130所產生的導電 材質微粒，例如是金屬銅微粒，對介電層108之擴散侵入， 造成兀件漏電以及短路的現象。 之後，請參照第1D圖，去除介電層108，直到裸露出部 分蝕刻終止層106，此去除介電層108之方法包括溶劑去 除法，或是乾式蝕刻法。續之，於蝕刻終止層106、導線 122a與124a以及阻障層128a之表面及側壁上形成共形的 阻障頂蓋層（barrier cap layer) 132。此阻障頂蓋層132 之材質包括氮化砂、碳化砂或是氮氧化砂。 接著，請參照第1E圖，於阻障頂蓋層132上，形成一 層介電常數較低之介電層134，且在介電層134於導線 122a與124a之間的空間（space)中形成空氣間隙136。 其中，介電層134是一階梯覆蓋性較差之介電層，較佳 8 本紙張尺度適用中國國家標準（CNS)Al規格（210 X 297公釐） -----------裝—--訂--------1 I (請先閱讀背面之注意事項再填窝本頁) A7 B7 43 91 82 5003twf.doc/006 五、發明說明（?） 的是以電漿加強型化學氣相沉積法（plasma-enhanced chemical vapor deposition，PECVD)，所形成之無機介 電材料層，較佳的無機介電材料包括氟化矽酸玻璃或是 Applied Materials 之黑鑽石（black diamond)材料或 NoveUus 之 Coroal。 利用形成階梯覆蓋性較差之介電層134，使在導線122a 與124a之間的空間中塡入介電層134時，會在導線122a 與124a之間的空間上方，先形成懸突結構134a，導致後 續沉積之介電層134之材質不易塡入導線122a與124a之 間的空間，並在形成介電層134過程中，彼此連結，以在 導線122a與124a之間的空間中形成空氣間隙136。 由於空氣間隙136中所具有之介電常數約略爲1.0，比 氧化矽的介電常數低，因此可降低導線122a與124a之間 的介電常數，故可以有效降低導線122a與124a之間以及 多重金屬內連線之間的電阻-電容時間延遲。 接著，於介電層134上形成一層平坦之介電層140，此 介電層140之材質包括無機介電材料，較佳的包括氟化矽 酸玻璃或是黑鑽石。而介電層140之平坦化方法包括化學 機械硏磨法。之後，於介電層140上，進行另一次雙金屬 鑲嵌製程（未繪示），以完成積體電路之多重金屬內連線之 製造。 於本發明之較佳實施例中，所使用之雙金屬鑲嵌內連線 製程方法，係爲眾多雙金屬鑲嵌內連線製程方法之一種， 熟習此技藝者於實際應用上，亦可選擇適用之雙金屬鑲嵌 9 本紙張尺度適用中國國家標準（CNS)A4規格<210x297公笈) (請先閲讀背面之注意事項再填寫本頁)τ · n I— f I Printed paper by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Chinese government standard (CNS) M (21〇X 297) Chu 4391 82 5003twf. doc / 006 A7 B7 V. Description of the invention (Λ_) intra-metal dieiectric layei.}, The RC time delay between low metal wire layers and between wires. However, the dielectric constant of the fluorinated acid glass is about 3 5 , Which is only 15% lower than the dielectric number of the oxide (4.1), so the reduction of the RC time delay is also restricted. In addition, other materials with low dielectric constant, including organic dielectric materials and inorganic dielectric materials Under the current requirement of dielectric constant below 3, the process technology of its j for products has not yet matured, so it is also rarely used as the material of the dielectric layer in the current dual-semiconductor circuit... ^ Therefore, the present invention It is to provide a method for manufacturing a dielectric layer of a bimetal mosaic interconnect. The method is briefly described as follows: First, a substrate is provided. Then, a dual metal mosaic structure is formed on the substrate. The bimetal mosaic structure is formed with A first wire above the substrate And the second conductive line and the first dielectric layer between the first conductive line and the second conductive line. After that, the first dielectric layer is removed, and then a conformal barrier cap layer is formed over the substrate. On the barrier cap layer, a second dielectric layer is formed, and an air gap is formed in the area defined by the second dielectric layer, the first and the first wires. Then, on the first dielectric layer, Forming ~ flattened third dielectric layer. According to fk's better pay example, the second dielectric layer is a dielectric layer with a poor coverage of the step coverage, which includes a plasma-enhanced chemical gas. A layer of an inorganic dielectric material formed by a phase deposition method. In the present invention, after a bimetal damascene interconnect structure is formed on a substrate, the first dielectric layer between the first and first wires is removed, and then step coverage is performed. The poor second dielectric layer covers the space between the first and second wires and forms an air gap in this space. Because of the air in the air gap, this paper is sized to Chinese National Standard (CNS) A4 (210 X 297 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4391 82 A7 5003twf.doc / 006 B7 5. The dielectric constant of the invention ($) is about 1.0, so it can effectively reduce the capacitive and inductive coupling between the wires, and the RC time delay, and reduce the mutual interference between the wires. It can reduce the interference level of the signals and reduce the dielectric constant between the multiple metal interconnects. Therefore, the RC time delay and interference between the multiple metal interconnects will be reduced, which will improve the data transmission speed and component performance. The above and other objects, features, and advantages of the invention can be more clearly understood. A preferred embodiment is described below in detail with the accompanying drawings as follows. = Brief description of the drawings: Figures 1A to 1E The figure shows a method for manufacturing a dielectric layer of a bi-metal damascene interconnect according to a preferred embodiment of the present invention. The relationship between each icon number and the component name is as follows: 100: substrate 102, 122a, 124a: wire 104, 1Q8, 134, 140: dielectric layer 106: etch stop layer 110: hard cover curtain layer 120: patterned photoresist 122, 124: trenches 126: interstitial window openings 126a: interstitial window plugs 128, 128a: barrier layer 130: conductive layer 132: barrier top cover layer 5 This paper standard applies to China National Standard (CNS) Al specifications ( 210 X 297 mm) (Please read the notes on the back before filling out this page) ---- Order ----- T. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Printing Du 3 4 91 2 "A7 50 03tvvf .doc / 006 ㈤ 5. Description of the invention (Order) 134a: Overhang structure 136: Air gap embodiment shown in Figures 1A to 1E 'is a bimetal mosaic interconnect according to a preferred embodiment of the present invention Manufacturing method of the dielectric layer. Referring to FIG. 1A, first, a substrate 100 is provided, on which a conductor 102 and components (not shown) have been formed. Next, a dielectric layer 104 is formed on the substrate 100. The dielectric layer 104 is, for example, an organic dielectric material layer formed by a spin coating method or a chemical vapor phase. A silicon oxyfluoride layer, a porous silicon oxide layer formed by a deposition method, or an inorganic material layer generally used. Next, a uranium etch stop layer 106 is formed on the dielectric layer 104. The etch stop layer 106 has a large etching selectivity ratio for the dielectric layer 104, such as a silicon oxynitride layer formed by a chemical vapor deposition method. , Silicon nitride layer, carbonized sand layer, or oxide cut layer. After that, the etch stop layer 106 is defined to form an opening (not shown) in the etch stop layer 106 corresponding to the conductive line 102, and expose a part of the dielectric layer 104 above the conductive line 102. Continuing, a lower dielectric constant dielectric layer 108 is formed on the etch stop layer 106 and the exposed dielectric layer 104. The dielectric layer 108 has a larger etch selection ratio for the etch stop layer 106. The material is an organic polymer dielectric material. The preferred organic polymer dielectric materials include FLARE (fluonirated poly (arylene ethers)) of A11 ied Signal, 6 (please read the precautions on the back first #; fill in this page) binding · ---- f. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4391 82 '5003twf.doc / 006 V. Description of the invention (female ) BCB (benzocyclobutene), amorphous carbon, or Silk of Dow Chemica 丨, and the formation method is, for example, spin coating method ^ followed by forming a hard mask layer 11 on the dielectric layer 108, The hard mask layer 110 is, for example, a silicon oxynitride layer, a silicon oxide layer, or a silicon nitride layer formed by a chemical vapor deposition method. After that, a patterned photoresist 120 is formed on the hard mask layer 110, and a part of the hard mask layer 110 is exposed. Next, trenches 122 and 124 are formed in the hard mask layer 110 and the dielectric layer 108, and the trenches 124 and 124 are formed in the etch stop layer 106 and the dielectric layer 104, and the conductive wires 102 to be conducted in the substrate are exposed. The opening of the dielectric window is 126 °. The method of forming the trenches 122 and 124 includes removing the hard mask layer 110 and the dielectric layer 108 by using the etch stop layer 106 as the end point of the etch, until the surface of the etch stop layer 106 is partially exposed. The method of forming the dielectric window opening 126 is to remove a part of the dielectric layer 1 (M) from the opening (not shown) of the etching stopper layer 106 until the surface of part of the conductive wire 102 is exposed. Continued, please refer to FIG. 1B to remove Patterned photoresist 120. Next, a conformal barrier layer 128 is formed over the substrate 100. The material of the barrier layer 128 includes tantalum nitride, molybdenum metal, tungsten nitride, or titanium nitride. This barrier layer The 128-series protective dielectric layers 108 and 104 will not be affected by the diffusion of conductive materials when the conductive materials are filled in the trenches 122 and 124 and the dielectric window openings 126 in the subsequent period, which may cause electrical problems of the components, and thereby improve Conductive materials and dielectric layers 104 Adhesiveness to 106. Then, a conductive layer 130 is formed on the barrier layer 128, and this conductive layer 130 fills the trenches 122 and 124 and the via window opening 126. Among them, 7 (Please read the note on the back first Please fill in this page for more details) Packing ------ Ordering ----- This paper size is applicable · Chinese National Standard (CNS) A..l specifications (210 x 297 mm) Employees ’Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printed 4 3 918 2. A7 5003twf.doc / 006 V. Description of the Invention (Hand) The material of the conductive layer 130 includes metal copper or copper alloy. Next, please refer to Figure 1C to remove part of the conductive layer 130 and the barrier Layer 128 and hard cover curtain layer 110 until the surface of the dielectric layer 108 is exposed, so as to mark the barrier layers remaining in the trenches 122 and 124 and the dielectric window opening 126 as the barrier layer 128a, and in the trenches 122 and The wires 122a and 124a are formed in 124, and a bimetal mosaic structure such as a via window plug 126a is formed in the via window opening 126. Among them, the wires 124a and 102 are electrically coupled through the via window plug 126a. Method for removing part of conductive layer 130, barrier layer 128 and hard cover curtain layer 110 Chemical mechanical honing method. Because the dielectric layer 108 is protected by the hard cover curtain layer 110, the conductive material particles generated by the conductive layer 130, such as metallic copper particles, can be prevented when removing a part of the conductive layer 130. Diffusion and intrusion of the dielectric layer 108 causes leakage and short circuit of the element. After that, please refer to FIG. 1D to remove the dielectric layer 108 until the etch stop layer 106 is partially exposed. This method for removing the dielectric layer 108 includes a solvent Removal or dry etching. Continuing, a conformal barrier cap layer 132 is formed on the surface and sidewalls of the etch stop layer 106, the wires 122a and 124a, and the barrier layer 128a. The material of the barrier capping layer 132 includes nitrided sand, carbide sand, or oxynitride sand. Next, referring to FIG. 1E, a dielectric layer 134 having a lower dielectric constant is formed on the barrier cap layer 132, and a dielectric layer 134 is formed in a space between the conductive lines 122a and 124a. Air gap 136. Among them, the dielectric layer 134 is a dielectric layer with poor step coverage, preferably 8 paper sizes are applicable to the Chinese National Standard (CNS) Al specification (210 X 297 mm) ----------- Packing --- order -------- 1 I (Please read the notes on the back before filling in this page) A7 B7 43 91 82 5003twf.doc / 006 V. The description of the invention (?) Is based on electricity Plasma-enhanced chemical vapor deposition (PECVD), an inorganic dielectric material layer formed. Preferred inorganic dielectric materials include fluorinated silicate glass or black diamonds from Applied Materials. diamond) material or Coroal by NovelUus. By forming the dielectric layer 134 with poor step coverage, when the dielectric layer 134 is inserted into the space between the wires 122a and 124a, an overhang structure 134a is formed above the space between the wires 122a and 124a. As a result, the material of the subsequently deposited dielectric layer 134 does not easily penetrate into the space between the wires 122a and 124a, and is connected to each other during the formation of the dielectric layer 134 to form an air gap 136 in the space between the wires 122a and 124a. . Since the air gap 136 has a dielectric constant of approximately 1.0, which is lower than the dielectric constant of silicon oxide, the dielectric constant between the wires 122a and 124a can be reduced, so the space between the wires 122a and 124a and more can be effectively reduced. Resistance-capacitance time delay between heavy metal interconnects. Next, a flat dielectric layer 140 is formed on the dielectric layer 134. The material of the dielectric layer 140 includes an inorganic dielectric material, preferably fluorinated silicate glass or black diamond. The planarization method of the dielectric layer 140 includes a chemical mechanical honing method. After that, another bimetal damascene process (not shown) is performed on the dielectric layer 140 to complete the fabrication of the multi-metal interconnects of the integrated circuit. In a preferred embodiment of the present invention, the bimetal mosaic inlay interconnect process method used is one of many bimetal mosaic inlay interconnect process methods. Those skilled in the art may choose the applicable one in practical applications Bimetal inlay 9 This paper size is applicable to Chinese National Standard (CNS) A4 specifications (210x297 cm) (Please read the precautions on the back before filling this page)
裝--------訂I 線}. 經濟部智慧財產局員工消費合作社印製 4 3 91 8.2.€ A7 5003twf\doc/006 五、發明說明（沒） 內連線製程方法以進行本發明之製程。 在本發明中，在基底上形成雙金屬鑲嵌內連線結構之 後，去除導線之間的介電材質，接著，形成階梯覆蓋性較 差的介電層，例如是以電漿加強型化學氣相沉積法所形成 之低介電常數之無機介電材質，覆蓋導線之間的空間，並 在此空間中形成空氣間隙，由於空氣間隙中之空氣的介電 常數約爲1.0，所以可有效降低導線之間的電容式與電感 式耦接，以及RC時間延遲，減少導線之間的相互雜訊干 擾程度，同時降低多重金屬內連線之間介電層之介電常 數，因此多重金屬內連線之間的RC時間延遲以及干擾將 大幅降低，進而提高資料傳輸速度以及元件性能。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 震---- 訂--------- 經濟部智慧財產局員工消費合作社印製 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Installation -------- Order I line}. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 3 91 8.2. € A7 5003twf \ doc / 006 V. Description of the invention (none) Inner connection process method to carry out The process of the invention. In the present invention, after a bi-metal damascene interconnect structure is formed on the substrate, the dielectric material between the wires is removed, and then a dielectric layer with poor step coverage is formed, such as by plasma enhanced chemical vapor deposition. The low dielectric constant inorganic dielectric material formed by the method covers the space between the wires and forms an air gap in this space. Since the dielectric constant of the air in the air gap is about 1.0, it can effectively reduce the Between capacitive and inductive coupling, and RC time delay, reduce the degree of mutual noise interference between the wires, and reduce the dielectric constant of the dielectric layer between the multiple metal interconnections. The RC time delay and interference will be greatly reduced, which will improve the data transmission speed and component performance. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling this page) Zhen ---- Order --------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 10 This paper size is applicable to China National Standard (CNS) A4 Specifications (210 X 297 mm)