TW444343B - Manufacturing method of inter-level dielectrics - Google Patents

Abstract

The present invention provides a manufacturing method of inter-level dielectrics, which is able to obtain a dielectric layer with a good gap filling capability and also avoid damaging the device by plasma charging. In accordance with the present invention, an undoped silicon glass layer is deposited by high-density plasma CVD. Then, a mobile ion gettering layer is deposited. If required, another undoped silicon glass layer can be deposited to make the subsequent CMP process easy.

Description

4443 43 Factory V. Description of Invention '' '' --- [Field of Invention] The present invention relates to semiconductor process technology, and particularly relates to a novel manufacturing method of an inner dielectric layer (ILD). [Background of the Invention] The fabrication of semiconductor integrated circuits is an extremely complicated process; its purpose is to reduce the production of various electronic components and circuits required for specific circuits on a small-area substrate. Among them, each component on the substrate must be effectively isolated, but must be electrically connected by a suitable metal wire in order to perform the desired function. In order to prevent the conductive layers or metal layers from directly contacting and causing a short circuit, they must be separated by an insulating layer, and the dielectric material used for isolation is called an interlayer dielectric layer, such as interlayer dielectric layers (ILd; inter_Level Dielectrics), It can be used to isolate semiconductor components such as transistors and capacitors and other wires; or internal metal dielectric layers (IMD; Inter-Metal Dielectrics) can be used to isolate the multilayer metal interconnects of the three-dimensional structure. A good inner dielectric layer (ILD) must have many conditions, including seamless trench filling, effective gettering of mobile ions, low thermal budget, and less plasma damage. In the conventional technology, the boron-phosphorus 03-TE0S oxide layer formed by the sub-atmospheric pressure chemical vapor deposition (SACVD) method has good step coverage properties, and is currently used to produce inner dielectric layers on production lines. Technology one. However, when the process technology enters the field of 0.18 microns or even finer dimensions, the gap-filling capability of boron-phosphorus 03-TE0S is no longer sufficient, and its densification treatment process also makes it suitable for

5. Explanation of the invention (2) The use is restricted. Therefore, the current trend is to use high-density plasma chemical vapor deposition (HDPCVD) deposition of phosphosilicate glass (PSG) with better gap-filling capability and no densification as the inner dielectric. However, with high density Plasma CVD deposition of phosphosilicate glass will accumulate the plasma charge and easily lead to severe shift of VFB. Therefore, how to deposit a dielectric layer with good filling ability by high-density plasma CVD to cope with the shrinking polycrystalline silicon (or metal) gap 'while avoiding the damage caused by the accumulation of electric charge has become the focus of the present invention. . [Summary of the Invention] In view of this, the main object of the present invention is to provide a method for manufacturing an inner dielectric layer, in order to obtain a dielectric layer with a good gap filling ability, and at the same time reduce plasma charging. In order to achieve the above-mentioned object, the present invention provides a method for manufacturing an inner dielectric layer. 'Firstly, an undoped silica glass layer (USG) is deposited by high-density plasma CVD method' and then a layer of mobile ion watering is deposited. Layer: If necessary, a layer of undoped silica glass can be deposited to facilitate subsequent chemical mechanical polishing (CMP). The manufacturing method of the present invention includes the following main steps: (a) depositing an undoped silica glass layer (USG) by high-density plasma chemical vapor deposition (HDPCVD) and filling gaps on the surface of the substrate; (b) deposition A doped oxide layer on the undoped silica glass layer as a trapping layer for mobile ions; and, optionally ('c) depositing another undoped silica glass layer

Page 5 4443 43 V. Description of the invention (3) (USG) on the doped oxide layer to form the inner dielectric layer. According to the above, the method of the present invention replaces the HDP phosphosilicate glass layer (PSG), which may cause plasma damage, with an HDP undoped silica glass layer (USG), and is supplemented with a doped oxide layer as an ion trap. Poly layer. Therefore, 'the inner dielectric layer of the present invention has excellent gap-filling ability of high-density plasma CVD, and at the same time, it can avoid the accumulation of charge to cause damage to the device. Among them, the above-mentioned doped hafnium layer used as the ion trapping layer may be a phosphosilicate glass layer (psG) or a borophosphosilicate glass layer (BPSG), which may be subjected to atmospheric pressure chemical vapor deposition (APCVD), It is formed by various methods such as compression chemical vapor deposition (SACVD), plasma chemical vapor deposition (PECVD), and high-density plasma chemical vapor deposition (HDPCVD). In order to make the above and other objects, features, and advantages of the present invention more comprehensible, hereinafter, the preferred embodiments are listed, and the detailed descriptions are as follows: Figure 3 is a series of cross-sectional views, which are used to explain the process of making the inner dielectric layer without examples. A good practice [Symbol description] 10 ~ semiconductor substrate; 1 MOS transistor; 12 ~ undoped silicon deposited by high-density plasma CVD 14 ~ doped oxide layer; spray layer; 16-undoped silicon glass Floor.

Page 6 4443 43 V. Description of the invention (4) [Example] ° Refer to Figure 1 for reference. This shows the initial steps of this example. The manufacturing method of the inner dielectric layer of the present invention is applicable to a semiconductor substrate 10 on which a desired semiconductor element such as a JJOS transistor, a resistor, a logic element, etc. is formed. For example, 'a thermal oxidation process can be used first', such as a regionalization process (L0C0S) or a shallow trench isolation process (STI), to isolate the active area. On the active area, another semiconductor process such as deposition, lithography, ion Fabrication and other processes to make semiconductor devices. For the sake of convenience, only the MOS transistor is shown in the figure. Next, according to the method of the present invention, an inner dielectric layer 'is formed on the surface of the element as an insulation coating between the isolation element and the subsequent conductive layer. First, a high-density plasma chemical vapor deposition (HDPCVD) method is used to deposit an undoped silicon glass layer (USG) 1 2 'to fill the gaps on the substrate surface. For example, using oxygen (〇2) and silicon methane (SiH4) as reactants, and simultaneously applying ΑΓ plasma sputtering to form an undoped silica glass layer 12 covering the MOS transistor 11 and the substrate 10 The thickness on the exposed surface is, for example, 1500-2500A. Among them, due to the auxiliary effect of Ar electrocracking, the undoped oxide layer 12 has a good step coverage force. As shown in FIG. 2, next, a doped oxide layer is deposited on the undoped silica glass layer 12 ′ as a trapping layer for mobile ions, and the thickness is, for example, 2000 to 300 Å. According to the method of the present invention, the doped oxide layer 14 used as the ion trapping layer can be a saucer glass layer (ps (j) or collar filling glass layer (BPSG)), but considering the thermal budget, Phosphosilicate glass layer (PSG)

Page 7 4443 43 V. Description of the invention (5) '— ~ Good. In addition, the doped oxide layer 14 may be formed by atmospheric pressure chemical vapor deposition (APCVD), sub-normal pressure chemical vapor deposition (SACVD), plasma chemical vapor deposition (PECVD), or high-density plasma chemical vapor deposition (HDPCVD). ) And other methods to form 'but considering the reduction of plasma damage, the deposition method is better by thermal CVD method and PEC VD method (at this time the filling capacity is no longer important < the next process can be directly chemical mechanical polishing CCMP ) To get a flat surface. Alternatively, as shown in FIG. 3, another undoped silica glass layer 16 is deposited, for example, an oxide layer deposited by plasma chemical vapor deposition (PECVD), and then planarized. According to the above, in the present invention, the HDP filled glass layer (PSG) ', which may cause plasma damage, has been replaced with an HDP undoped silica glass layer (USG), and supplemented with a doped oxide layer as an ion trap. Poly layer. Therefore, the inner dielectric layer of the present invention has a high-density plasma]]) excellent gap filling ability t, and at the same time, it can avoid the accumulation of tritium charge to cause damage to the element. To further support the above argument of the present invention ', please refer to the data of Tables 1 and 2 below. Table 1 shows that phosphor-silicon-silicon glass (pSG) deposited with HDpcvD will cause severe VFB offset, while the VFB offset using undoped silica glass (USG) of the present invention is smaller. Table I

Page 8 4443 43 V. Description of the invention (6)

Vfb (V) HDP USG -6.9 HDP PSG -10 SACVD BP 03-TE0S -3.5 Table 2 shows the measured mobile charge (Qm) of various dielectric layers under different pollution conditions. From the data in Table 2, it can be seen that the phosphosilicate glass layer (PSG) is an excellent ion trapping layer, while the undoped silica glass (USG) has no ion trapping effect. Table 2 Thin film non-pollution, low pollution, high pollution, 940A thermal oxidation eyebrows <5E10 1-2E11 1-5E11 2-6E11 940A thermal gasification 厝 + 2000A SACVD BPSG 1.72E11 No greater than 1.72E11 2.1E11 940A thermal gasification detected Layer + 200〇A HDP PSG (3vt%) 4. Anal 10 No detected no detected No detected thermal oxide layer + 200〇A HDP PSO (4wtft) 5.6E10 No detected No detected No detected 94 ° A thermal gasification layer + 200 ° A HDP USG 3.8E10 2E11 2-4E11 2-4E11 94 ° A boiled layer + 2000A silicon-rich silicon nitride oxide 5.7E10 not detected not detected not detected Exothermic gasification layer + 2000A silicon nitride 1.21E10 No value detected No value detected * No value detected indicates that the measured Qm value is close to the Qm value of the uncontaminated area

Page 94443 43 I. Description of the Invention (7) Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit and scope of the present invention. Various modifications and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. *

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Claims (1)

4 ^ 43 43 VI. Scope of patent application 1. A method for manufacturing an inner dielectric layer is suitable for a semiconductor substrate on which a desired semiconductor element is formed. The method includes the following steps: (a) High Density Plasma Chemical Vapor Deposition (HDPCVD) deposits an undoped silica glass layer (USG) 'to fill gaps on the surface of the substrate; and (b) deposits a doped oxide layer on the undoped silica glass The layer serves as a gettering layer for mobile ions. 2. The manufacturing method described in item 1 of the scope of patent application, wherein the doped oxide layer is a phosphosilicate glass layer (PSG) »3. The manufacturing method described in item 1 of the scope of patent application 'where the doped rolling The chemical conversion layer is a borophosphosilicate glass layer (BPSG). I The manufacturing method according to item 1, 2, or 3 of the scope of patent application, wherein the doped oxide layer is deposited by atmospheric pressure chemical vapor deposition (APCVD). 5. The manufacturing method as described in claims 1, 2 or 3, wherein the doped oxide layer is deposited by a sub-atmospheric pressure chemical vapor deposition (Sac VD) method. 6. The manufacturing method as described in claims 1, 2 or 3, wherein the doped oxide layer is deposited by plasma chemical vapor deposition (pECVD). 7. The manufacturing method as described in claims 1, 2, or 3, wherein the doped oxide layer is deposited by high-density plasma chemical vapor deposition (HDPCVD). 8. The manufacturing method according to item 1 of the patent application scope, wherein after step (b) further comprises: performing chemical mechanical polishing to obtain a flat surface. Page 11 44 ^ 343 9. A method for manufacturing an inner dielectric layer, which is suitable for manufacturing a semiconductor substrate with a MOS transistor. The manufacturing method includes the following steps: (a) depositing a high-density plasma chemical vapor deposition (HDPCVD) method; Doped silica glass layer (USG), filling the gap on the surface of the substrate; and (b) depositing a doped oxide layer on the undoped silica glass layer as a gettering layer of mobile ions And '(c) depositing another undoped silica glass layer on the doped oxide layer. 10. The manufacturing method according to item 9 of the scope of the patent application, wherein the doped oxide layer is a phosphosilicate glass layer (PSG). Π_ The manufacturing method according to item 9 of the scope of the patent application, wherein the doped oxide layer is a borophosphosilicate glass layer (BPSG). 12. The manufacturing method according to item 9, 10, or 11 of the scope of the patent application, wherein the doped oxide layer is deposited by an atmospheric pressure chemical vapor deposition method (APCVD). 13. The manufacturing method according to claim 9, 10 or 11, wherein the doped oxide layer is deposited by a sub-normal pressure chemical vapor deposition (SACVD) method. 14. The manufacturing method according to item 9, 10, or 11 of the scope of the patent application, wherein the doped oxide layer is deposited by plasma chemical vapor deposition (PECVD). 15. The manufacturing method as described in claim 9, 10 or Η, wherein the doped oxide layer is deposited by high-density plasma chemical vapor deposition (HDPCVD). 16. The manufacturing method as described in item 9 of the scope of patent application ’ Page 12 4443 4 3 I 6. Scope of patent application (c) The plasma chemical vapor deposition (PECVD) method is used to deposit another undoped silicon glass layer. 17. The manufacturing method according to item 9 of the scope of patent application, wherein after step (c) further comprises: performing chemical mechanical polishing to obtain a flat surface. Page 13