CN112018241A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112018241A CN112018241A CN201910471955.8A CN201910471955A CN112018241A CN 112018241 A CN112018241 A CN 112018241A CN 201910471955 A CN201910471955 A CN 201910471955A CN 112018241 A CN112018241 A CN 112018241A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate; forming a first electrode layer on a substrate, wherein the first electrode layer is of a single-layer or multi-layer structure; forming a dielectric layer on the first electrode layer; forming a second electrode layer on the dielectric layer, wherein the second electrode layer is of a single-layer or multi-layer structure; the first electrode layer is in contact with the dielectric layer and is a first electrode contact layer, the second electrode layer is in contact with the dielectric layer and is a second electrode contact layer, and at least one of the first electrode contact layer and the second electrode contact layer is formed by adopting an atomic layer deposition process. The surface roughness of the layer structure formed by the atomic layer deposition process is low, in the same region, protruding points protruding towards the dielectric layer at the same time are not prone to exist in the first electrode layer contact layer and the second electrode layer contact layer, the shortest distance between the first electrode layer contact layer and the second electrode layer contact layer is increased, the dielectric layer is not prone to breakdown, and the electrical performance of the semiconductor structure is improved.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
A capacitor is a passive two-terminal electrical device used to store energy within an electric field. The capacitor comprises at least two electrodes separated by a dielectric layer. The capacitance of a capacitor is proportional to the area between two electrodes and inversely proportional to the distance between the two electrodes (e.g., the thickness of the dielectric layer). Thus, the capacitance of the capacitor can be increased by increasing the area of the electrodes, and/or by decreasing the distance between them.
In today's Very Large Scale Integration (VLSI) circuits, capacitors are commonly used passive devices. Because of the need for higher capacitance density, higher reliability capacitors in analog RF circuits, analog capacitors have been shifted from Polysilicon-Insulator-Polysilicon (PIP) to Metal-Insulator-Metal (MIM) capacitors.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize electrical properties of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a first electrode layer on the substrate, wherein the first electrode layer is of a single-layer or multi-layer structure; forming a dielectric layer on the first electrode layer; forming a second electrode layer on the dielectric layer, wherein the second electrode layer is of a single-layer or multi-layer structure; the first electrode layer is in contact with the dielectric layer and is a first electrode contact layer, the second electrode layer is in contact with the dielectric layer and is a second electrode contact layer, and at least one of the first electrode contact layer and the second electrode contact layer is formed by adopting an atomic layer deposition process.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the first electrode layer is positioned on the substrate and is of a single-layer or multi-layer structure; a dielectric layer on the first electrode layer; the second electrode layer is positioned on the dielectric layer and is of a single-layer or multi-layer structure; the first electrode layer is in contact with the dielectric layer and is a first electrode contact layer, the second electrode layer is in contact with the dielectric layer and is a second electrode contact layer, and at least one of the first electrode contact layer and the second electrode contact layer is formed by adopting an atomic layer deposition process.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, a first electrode contact layer is arranged in the first electrode layer and is contacted with the dielectric layer, a second electrode contact layer is arranged in the second electrode layer and is contacted with the dielectric layer, and at least one of the first electrode contact layer and the second electrode contact layer is formed by adopting an atomic layer deposition process. The first electrode layer contact layer, the second electrode layer contact layer, or the first electrode layer contact layer and the second electrode contact layer are formed by adopting an atomic layer deposition process. Compared with a process method that the roughness of the first electrode contact layer and the second electrode contact layer is larger than that of atomic layer deposition, in the same region, protruding points protruding towards the dielectric layer at the same time are not prone to existing in the first electrode contact layer and the second electrode contact layer, the shortest distance between the first electrode contact layer and the second electrode contact layer is increased, the dielectric layer is not prone to breakdown, and the electrical performance of the semiconductor structure is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 5 are schematic structural views corresponding to steps in a method for forming a semiconductor structure according to a first embodiment of the present invention;
FIG. 6 is a schematic structural diagram illustrating a method of forming a semiconductor structure according to a second embodiment of the present invention;
fig. 7 is a schematic structural diagram illustrating a method for forming a semiconductor structure according to a third embodiment of the present invention.
Detailed Description
As can be seen from the background art, the performance of the devices formed at present is still not good. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1, a schematic diagram of a semiconductor structure is shown.
As shown in fig. 1, the semiconductor structure includes: a substrate and a capacitor 1 located on the substrate. Specifically, the capacitor 1 includes a first metal layer 11, a dielectric layer 12 on the first metal layer 11, and a second metal layer 13 on the dielectric layer 12.
The capacitor 1 is an MIM capacitor structure, the thickness of the dielectric layer 12 is only ten nanometers or even several nanometers, and the first metal layer 11 and the second metal layer 13 are usually formed by Physical Vapor Deposition (PVD), the surfaces of the first metal layer 11 and the second metal layer 13 are in a columnar crystalline state, so that the roughness of the surfaces of the first metal layer 11 and the second metal layer 13 is high, and protruding points protruding to the dielectric layer 12 easily exist in the first metal layer 11 and the second metal layer 13 in the same region on the substrate, in which case, the shortest distance between the first metal layer 11 and the second metal layer 13 is far smaller than a designed value, and the dielectric layer 12 is easily broken down, so that the MIM capacitor structure is easily broken down.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a first electrode layer on the substrate, wherein the first electrode layer is of a single-layer or multi-layer structure; forming a dielectric layer on the first electrode layer; forming a second electrode layer on the dielectric layer, wherein the second electrode layer is of a single-layer or multi-layer structure; the first electrode layer is in contact with the dielectric layer and is a first electrode contact layer, the second electrode layer is in contact with the dielectric layer and is a second electrode contact layer, and at least one of the first electrode contact layer and the second electrode contact layer is formed by adopting an atomic layer deposition process.
In order to solve the technical problem, in the first electrode layer, a first electrode contact layer is in contact with the dielectric layer, in the second electrode layer, a second electrode contact layer is in contact with the dielectric layer, and at least one of the first electrode contact layer and the second electrode contact layer is formed by using an atomic layer deposition process. The first electrode layer contacts the layer, or the second electrode layer contacts the layer, or the first electrode layer contacts the layer and the second electrode layer adopt an atomic layer deposition process. Compared with a process method that the roughness of the first electrode contact layer and the second electrode contact layer is larger than that of atomic layer deposition, in the same region, protruding points protruding towards the dielectric layer at the same time are not prone to existing in the first electrode contact layer and the second electrode contact layer, the shortest distance between the first electrode contact layer and the second electrode contact layer is increased, the dielectric layer is not prone to breakdown, and the electrical performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 2 to 5 are schematic structural diagrams corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention.
Referring to fig. 2, a substrate is provided.
The substrate provides a process foundation for subsequently forming the semiconductor structure.
Specifically, the substrate includes an interlayer dielectric layer 100, a connection metal layer 101 located in the interlayer dielectric layer 100, and an anti-etching layer 102 located on the interlayer dielectric layer 100 and the connection metal layer 101.
The connection metal layer 101 is a structure to be connected, and the connection metal layer 101 is used for electrically connecting a capacitor formed subsequently.
In this embodiment, the material of the connection metal layer 101 is Cu. In other embodiments, the material of the connecting metal layer includes Al, Co, or W.
The number of the connection metal layers 101 is plural.
The interlayer dielectric layer 100 is used to realize electrical isolation between the plurality of connection metal layers 101.
The interlayer dielectric layer 100 is made Of an ultra low K dielectric material (ULK), where the ultra low K dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6, and the interlayer dielectric layer 100 is made Of the ultra low K dielectric material, so that the parasitic capacitance Of the connection metal layer 101 can be effectively reduced, and the Back End Of Line (BEOL) RC delay is further reduced.
In this embodiment, the interlayer dielectric layer 100 is made of porous silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be SiOCH.
And forming a capacitor connected with the connecting metal layer 101 on the anti-etching layer 102, wherein the etching stop layer 102 is used for defining the position of etching stop in the process of forming the capacitor and protecting the connecting metal layer 101 and the interlayer dielectric layer 100.
Specifically, the material of the etch-resistant layer 102 includes one or more of silicon oxide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, and silicon nitride containing C. In this embodiment, the material of the anti-etching layer 102 is silicon nitride containing C.
It should be noted that the difference between the thermal expansion coefficients of the material of the anti-etching layer 102 and the material of the first electrode layer in the capacitor to be formed later is large, and if the first electrode layer is formed directly on the anti-etching layer 102, the first electrode layer is prone to Delamination (Delamination) and even cracking (crack) with the anti-etching layer 102, resulting in poor formation quality of the capacitor. Therefore, in this embodiment, the forming method further includes: a buffer layer 103 is formed between the etch resist layer 102 and the first electrode layer, and the buffer layer 103 serves as a stress buffer.
In this embodiment, the buffer layer 103 is made of silicon oxide.
It should be noted that the density of the buffer layer 103 is greater than that of the interlayer dielectric layer 100, and the higher density of the silicon oxide is beneficial to improving the adhesion between the buffer layer 103 and the anti-etching layer 102 and the subsequent first electrode layer, and improving the formation quality of the semiconductor structure.
In other embodiments, the material of the buffer layer includes a low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6). For example: SiOH, SiOCH, FSG, BSG, PSG, BPSG, hydridosilsesquioxane or methylsilsesquioxane.
Referring to fig. 3, a first electrode layer 104 is formed on the substrate, and the first electrode layer 104 has a single-layer or multi-layer structure.
The first electrode layer 104, a dielectric layer to be formed later, and a second electrode layer together constitute a capacitor, which is an MIM capacitor.
The first electrode layer 104 is used as a bottom plate (bottom plate) of the MIM capacitor. The first electrode layer 104 is connected to the connection metal layer 101.
In addition, a first electrode contact layer 1041 is in contact with the dielectric layer formed later in the first electrode layer 104.
In this embodiment, the first electrode contact layer 1041 is made of a metal material.
Specifically, the first electrode contact layer 1041 is made of a metal nitride, and the metal nitride is an inert metal, so that the first electrode contact layer 1041 has high stability, and metal ions are not easy to diffuse.
In this embodiment, the material of the first electrode contact layer 1041 is one or two of TiN and TaN. TaN and TiN have higher work functions, so that electrons are not easy to jump, and a subsequently formed capacitor is not easy to leak electricity. In this embodiment, the material of the first electrode contact layer 1041 includes TiN.
In this embodiment, the first electrode contact layer 1041 is formed by using an Atomic Layer Deposition (ALD) process. The atomic layer deposition process includes performing multiple atomic layer deposition cycles to form the first electrode contact layer 1041 of a desired thickness. By selecting the atomic layer deposition process, the thickness uniformity of the first electrode contact layer 1041 is improved, so that the thickness of the first electrode contact layer 1041 can be accurately controlled; in addition, the gap filling performance and step coverage of the atomic layer deposition process are good, and accordingly, the conformal coverage capability of the first electrode contact layer 1041 is improved. In other embodiments, other deposition processes may be used to form the first electrode contact layer, such as: organometallic chemical vapor deposition, and the like.
Note that the first electrode contact layer 1041 is not too thick nor too thin. If the first electrode contact layer 1041 is too thick, the process time is too long, and the height of the formed device is too large, which is not favorable for the subsequent semiconductor process. If the first electrode contact layer 1041 is too thin, the thickness uniformity and film quality of the first electrode contact layer 1041 and the covering capability of the first electrode contact layer 1041 on the substrate are easily reduced, the first electrode contact layer 1041 is not easy to cover the rough points of the layer structure below the first electrode contact layer 1041, so that the protruding points protruding toward the dielectric layer 106 are easily present in the first electrode contact layer 1041, a second electrode layer is formed on the dielectric layer subsequently, and the second electrode contact layer is in contact with the dielectric layer in the second electrode layer, so that the distance between the first electrode contact layer 1041 and the second electrode contact layer is shortest and closer in the same region, and the dielectric layer 106 is easily broken down. In this embodiment, the thickness of the first electrode contact layer 1041 is 1 nm to 15 nm.
The step of forming the first electrode layer 104 further comprises: before the first electrode contact layer 1041 is formed, a third electrode film 1042 is formed on the substrate.
The first electrode contact layer 1041 and the third electrode film 1042 function together as a lower plate of the MIM capacitor.
In this embodiment, the third electrode film 1042 is made of a metal material.
Specifically, the third electrode film 1042 is made of a metal nitride, which is an inert metal, so that the third electrode film 1042 has high stability, and metal ions are not easily diffused.
In this embodiment, the third electrode film 1042 is made of one or two of TiN and TaN. TaN and TiN have higher work functions, so that electrons are not easy to jump, and the subsequently formed capacitor is not easy to leak electricity. In this embodiment, the material of the third electrode film 1042 includes TiN.
The first electrode contact layer 1041 and the third electrode film 1042 are made of the same material, so that the interface problem and the electrical property degradation problem caused by different materials are effectively avoided, and the compatibility of the process and the stability of the semiconductor structure are improved.
The thickness of the third electrode film 1042 is not necessarily too small or too large. If the thickness of the third electrode film 1042 is too small, the film quality of the third electrode film 1042 is liable to be poor, and the formation quality of the first electrode contact layer 1041 is liable to be reduced; if the thickness of the third electrode film 1042 is too large, the height of the device is too large, which may adversely affect the subsequent semiconductor process. For this reason, in this embodiment, the thickness of the third electrode film 1042 is 30 nm to 80 nm.
In this embodiment, the third electrode film 1042 is formed by a physical vapor deposition process. The physical vapor deposition process has the advantages of simple process, less pollution, low process cost, compact formed film, strong bonding force with other film structures and the like.
It should be noted that the MIM capacitor is formed between adjacent metal layers in a back-end-of-line process, so that the first electrode layer 104 is located in a partial region on the substrate.
It should be noted that after the third electrode film 1042 is formed, the third electrode film 1042 is further subjected to a cleaning process, and then dried by an inert gas, so that the surface of the third electrode film 1042 is not easily contaminated, which is beneficial to improving the reliability of the semiconductor MIM capacitor.
As shown in fig. 4, a dielectric layer 106 is formed on the first electrode layer 104.
The dielectric layer 106 is used as an insulating layer in a MIM capacitor.
In this embodiment, the dielectric layer 106 is made of a high-k dielectric material; wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. The high-k dielectric material is selected, so that the capacitance value of the MIM capacitor is improved.
Specifically, the dielectric layer 106 is a stacked high-k dielectric layer, that is, the dielectric layer 106 is a high-k composite dielectric layer. After the forming thickness of the high-k dielectric layer reaches a certain value, the forming quality of the high-k dielectric layer is easy to be deteriorated, and therefore, the thickness of the dielectric layer 106 meets the process requirement and has good forming quality at the same time by adopting the high-k composite dielectric layer.
The material of the dielectric layer 106 includes binary oxide and ternary oxide.
Specifically, the binary oxide includes: one or more of hafnium oxide, tantalum oxide, titanium oxide, hafnium oxide, or lanthanum oxide; the ternary oxide includes: SrTiO3、Zn2GeO4、NiCo2O4、Zn2SnO4、ZnFe2O4、ZnMnO3And Fe2GeO4One or more of (a). In this embodiment, the material of the dielectric layer 106 includes hafnium oxide.
It should be noted that the dielectric layer 106 is not too thick or too thin. As can be seen from the capacitance formula, the capacitance value of a single capacitor is inversely proportional to the thickness of the dielectric layer 106, and if the dielectric layer 106 is too thick, the density of the capacitor becomes small, which is not easy to meet the device requirement. If the dielectric layer 106 is too thin, the thickness uniformity and film quality of the dielectric layer 106 and the covering capability of the dielectric layer 106 on the first electrode layer 104 are easily reduced, and problems such as a decrease in linearity between the capacitance and the thickness of the dielectric layer 106, breakdown, etc. are easily caused. In this embodiment, the thickness of the material of the dielectric layer 106 is 5 nm to 12 nm.
In this embodiment, the dielectric layer 106 is formed by an atomic layer deposition process. The atomic layer deposition process includes performing multiple atomic layer deposition cycles to form the dielectric layer 106 to a desired thickness. By selecting the atomic layer deposition process, the thickness uniformity of the dielectric layer 106 can be improved, so that the thickness of the dielectric layer 106 can be accurately controlled; in addition, the atomic layer deposition process has good gap filling performance and step coverage, which correspondingly improves the conformal coverage capability of the dielectric layer 106. In other embodiments, when the dielectric layer is thicker, other deposition processes may be used, such as: chemical vapor deposition, and the like.
Referring to fig. 5, a second electrode layer 105 is formed on the dielectric layer 106, and the second electrode layer 105 has a single-layer or multi-layer structure.
The second electrode layer 105, the first electrode layer 104 and the dielectric layer 106 together constitute a capacitor, which is a MIM capacitor.
The second electrode layer 105 is used as a top plate (top plate) of the MIM capacitor. The second electrode layer 105 is connected to a metal layer subsequently formed on the capacitor.
In the second electrode layer 105, a second electrode contact layer 1051 is in contact with the dielectric layer 106.
In this embodiment, the second electrode contact layer 1051 is formed by an atomic layer deposition process. The atomic layer deposition process includes performing multiple atomic layer deposition cycles to form the second electrode contact layer 1051 to a desired thickness. By selecting the atomic layer deposition process, the thickness uniformity of the second electrode contact layer 1051 can be improved, so that the thickness of the second electrode contact layer 1051 can be accurately controlled; in addition, the atomic layer deposition process has good gap filling performance and step coverage, and accordingly improves conformal coverage capability of the second electrode contact layer 1051. In other embodiments, other deposition processes may be used to form the second electrode contact layer, such as: organometallic chemical vapor deposition, and the like.
The first electrode contact layer 1041 and the second electrode contact layer 1051 are both formed by adopting an atomic layer deposition process, so that the surface roughness of the first electrode contact layer 1041 and the second electrode contact layer 1051 is lower, compared with a process method that the roughness of the first electrode contact layer and the roughness of the second electrode contact layer are larger than that of the atomic layer deposition process, in the same region, protruding points protruding towards the dielectric layer 106 at the same time are not easy to exist in the first electrode layer 104 contact layer and the second electrode layer 105 contact layer, the shortest distance between the first electrode layer 104 contact layer and the second electrode layer 105 contact layer is increased, the dielectric layer 106 is not easy to break down, and the electrical performance of the semiconductor structure is improved.
In this embodiment, the shortest distance refers to a distance between the upper surface of the first electrode contact layer 1041 and the lower surface of the second electrode contact layer 1051.
In this embodiment, the second electrode contact layer 1051 is made of a metal material.
Specifically, the second electrode contact layer 1051 is made of a metal nitride, and the metal nitride is an inert metal, so that the second electrode contact layer 1051 has high stability, and metal ions are not easily diffused.
In this embodiment, the material of the second electrode contact layer 1051 is one or two of TiN and TaN. TaN and TiN have higher work functions, so that electrons are not easy to jump, and a subsequently formed capacitor is not easy to leak electricity. In this embodiment, the material of the second electrode contact layer 1051 includes TiN.
Note that the second electrode contact layer 1051 is not too thick nor too thin. If the second electrode contact layer 1051 is too thick, the process time is too long, and the height of the formed device is too large, which is not favorable for the subsequent semiconductor process. If the second electrode contact layer 1051 is too thin, the thickness uniformity and film quality of the second electrode contact layer 1051 and the coverage capability of the second electrode contact layer 1051 on the dielectric layer 106 are easily reduced, and the second electrode contact layer 1051 is not easy to cover rough points on a subsequently formed fourth electrode film, so that the shortest distance between the second electrode contact layer 1051 and the second electrode contact layer is relatively short in the same region, and the dielectric layer 106 is easy to break down. In this embodiment, the thickness of the second electrode contact layer 1051 is 1 nm to 15 nm.
The step of forming the second electrode layer 105 further comprises: after the second electrode contact layer 1051 is formed, a fourth electrode film 1052 is formed on the second electrode contact layer 1051.
The second electrode contact layer 1051 and the fourth electrode film 1052 together serve as an upper plate of the MIM capacitor. The second electrode layer 105 is connected to a metal that is subsequently formed on the capacitor.
For this purpose, the material of the fourth electrode film 1052 is a metal material.
Specifically, the material of the fourth electrode film 1052 is metal nitride, and the metal nitride is an inert metal, so that the fourth electrode film 1052 has high stability, and metal ions are not easy to diffuse.
In this embodiment, the material of the fourth electrode film 1052 is one or two of TiN and TaN. TaN and TiN have higher work functions, so that electrons are not easy to jump, and a subsequently formed capacitor is not easy to leak electricity. In this embodiment, the material of the fourth electrode film 1052 includes TiN.
The second electrode contact layer 1051 and the fourth electrode film 1052 are made of the same material, so that the interface problem and the electrical property degradation problem caused by different materials are effectively avoided, and the compatibility of the process and the stability of the semiconductor structure are improved.
In this embodiment, the fourth electrode film 1052 is formed by a physical vapor deposition process. For specific advantages, reference may be made to the corresponding description of the third electrode film 1042, which is not repeated herein.
The thickness of the fourth electrode film 1052 is not necessarily too small, and is not necessarily too large. If the thickness of the fourth electrode film 1052 is too small, the quality of the thin film of the fourth electrode film 1052 is easy to be poor, and the formation quality of the formed MIM capacitor is easy to be reduced; if the thickness of the fourth electrode film 1052 is too large, the process time is too long, and the height of the formed device is too large, which is not favorable for the subsequent semiconductor process. For this reason, in the present embodiment, the thickness of the fourth electrode film 1052 is 30 to 80 nm.
It should be noted that after the fourth electrode film 1052 is formed, the fourth electrode film 1052 is further cleaned and dried by inert gas treatment after the cleaning treatment, so that the surface of the fourth electrode film 1052 is not easily contaminated, which is beneficial to improving the reliability of the semiconductor MIM capacitor.
In other embodiments, the method for forming the semiconductor structure may further include: forming a first electrode contact layer and a second electrode contact layer which are in contact with the dielectric layer by adopting an atomic layer deposition process, wherein a third electrode film and a fourth electrode film are not formed, and correspondingly, the thicknesses of the first electrode contact layer and the second electrode contact layer are adaptively adjusted according to design requirements;
or, a third electrode film is not formed, a fourth electrode film is formed, and the thickness of the first electrode contact layer is adaptively adjusted according to design requirements;
alternatively, the third electrode film is formed, the fourth electrode film is not formed, and the thickness of the second electrode contact layer is adaptively adjusted according to design requirements.
Referring to fig. 6, the invention further provides a method for forming a second semiconductor structure, which includes the following specific steps:
the same points of the embodiment of the present invention as those of the first embodiment are not described herein again. The present embodiment is different from the first embodiment in that: the first electrode layer 204 in contact with the dielectric layer 206 is a first electrode contact layer 2041, the second electrode layer in contact with the dielectric layer 206 is a second electrode contact layer 2051, and the first electrode contact layer 2041 is formed by an atomic layer deposition process.
The first electrode contact layer 2041 is formed by adopting an atomic layer deposition process, the surface roughness of the first electrode contact layer 2041 is low, compared with a process method that the roughness of the first electrode contact layer and the roughness of the second electrode contact layer are larger than that of the atomic layer deposition process, in the same region, protruding points which protrude towards the dielectric layer 206 at the same time are not easy to exist in the first electrode contact layer 2041 and the second electrode contact layer 2051, the shortest distance between the first electrode contact layer 2041 and the second electrode contact layer 2051 is increased, the dielectric layer 206 is not easy to break down, and the electrical performance of the semiconductor structure is improved.
In this embodiment, the material, thickness, and forming method of the first electrode contact layer 2041 are the same as those of the first embodiment, and are not described herein again.
In this embodiment, the material, thickness, and formation method of the third electrode film are as described in the first embodiment, and are not described herein again.
In this embodiment, the second electrode contact layer 2051 is formed by a physical vapor deposition process. The physical vapor deposition process has the advantages of simple process, less pollution, low process cost, compact formed film, strong bonding force with other film structures and the like.
Note that the thickness of the second electrode contact layer 2051 is not necessarily too small or too large. If the thickness of the second electrode contact layer 2051 is too small, the quality of the film of the second electrode contact layer 2051 is poor, and the formation quality of the formed MIM capacitor is easily reduced; if the thickness of the second electrode contact layer 2051 is too large, the process time is too long, and the height of the formed device is too large, which is not favorable for the subsequent semiconductor process. For this reason, in this embodiment, the thickness of the second electrode contact layer 2051 is 31 nm to 95 nm.
In this embodiment, the material of the second electrode contact layer 2051 is not described herein again.
In this embodiment, the fourth electrode film is not formed.
In other embodiments, the method for forming the semiconductor structure may further include: and forming a first electrode contact layer only by adopting an atomic layer deposition process, and not forming a third electrode film and a fourth electrode film, wherein the thicknesses of the first electrode contact layer and the second electrode contact layer are adaptively adjusted.
Referring to fig. 7, the present invention further provides a method for forming a third semiconductor structure, which includes the following steps:
the same points of the embodiment of the present invention as those of the first embodiment are not described herein again. The present embodiment is different from the first embodiment in that: the first electrode layer is in contact with the dielectric layer 306 is a first electrode contact layer 3041, the second electrode layer 305 is in contact with the dielectric layer 306 is a second electrode contact layer 3051, and the second electrode contact layer 3051 is formed by using an atomic layer deposition process.
The second electrode contact layer 3051 is formed by an atomic layer deposition process, the surface roughness of the second electrode layer contact layer 3051 is relatively low, compared with a process method that the roughness of the first electrode contact layer and the roughness of the second electrode contact layer are larger than that of the atomic layer deposition process, in the same region, protruding points protruding towards the dielectric layer 306 at the same time are not easy to exist in the first electrode layer contact layer 3041 and the second electrode layer contact layer 3051, the shortest distance between the first electrode layer contact layer 3041 and the second electrode layer contact layer 3051 is increased, the dielectric layer 306 is not easy to break down, and the electrical performance of the semiconductor structure is improved.
In this embodiment, the material, thickness, and formation method of the second electrode contact layer 3051 are as described in the first embodiment, and are not described herein again.
In this embodiment, the material, thickness, and formation method of the fourth electrode film are as described in the first embodiment, and are not described herein again.
In this embodiment, the first electrode contact layer 3041 is formed by a physical vapor deposition process. The physical vapor deposition process has the advantages of simple process, less pollution, low process cost, compact formed film, strong bonding force with other film structures and the like.
Note that the thickness of the first electrode contact layer 3041 should not be too small or too large. If the thickness of the first electrode contact layer 3041 is too small, the film quality of the first electrode contact layer 3041 is poor, and the formation quality of the dielectric layer 306 is easily reduced; if the thickness of the first electrode contact layer 3041 is too large, the process time is too long, and the height of the formed device is too large, which is not favorable for the subsequent semiconductor process. For this reason, in the present embodiment, the thickness of the first electrode contact layer 3041 is 31 nm to 95 nm.
In this embodiment, the material of the first electrode contact layer 3041 is not described herein.
In this embodiment, the third electrode film is not formed.
In other embodiments, the method for forming the semiconductor structure may further include: and forming a second electrode contact layer only by adopting an atomic layer deposition process, and not forming a third electrode film and a fourth electrode film, wherein the thicknesses of the first electrode contact layer and the second electrode contact layer are adaptively adjusted.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Fig. 5 shows a schematic structural diagram of a first embodiment of the semiconductor structure of the present invention.
Referring to fig. 5, a semiconductor structure includes: a substrate; a first electrode layer 104 disposed on the substrate, wherein the first electrode layer 104 has a single-layer or multi-layer structure; a dielectric layer 106 on the first electrode layer 104; a second electrode layer 105 disposed on the dielectric layer 106, wherein the second electrode layer 105 has a single-layer or multi-layer structure; the first electrode layer 104 is in contact with the dielectric layer 106 and is a first electrode contact layer 1041, the second electrode layer 105 is in contact with the dielectric layer 106 and is a second electrode contact layer 1051, and at least one of the first electrode contact layer 1041 and the second electrode contact layer 1051 is formed by an atomic layer deposition process.
In the embodiment of the present invention, the first electrode layer 104 is a first electrode contact layer 1041 in contact with the dielectric layer 106, the second electrode layer 105 is a second electrode contact layer 1051 in contact with the dielectric layer 106, and the first electrode contact layer 1041 and the second electrode contact layer 1051 are both formed by using an atomic layer deposition process, so that the surface roughness of the first electrode contact layer 1041 and the second electrode contact layer 1051 is low, and compared with a process method in which the first electrode contact layer and the second electrode contact layer are simultaneously formed by using a process method having a roughness greater than that of atomic layer deposition, in the same region, protruding points protruding toward the dielectric layer 106 are not easily present in the first electrode layer 104 contact layer and the second electrode layer 105 contact layer, and the shortest distance between the first electrode layer 104 contact layer and the second electrode layer 105 contact layer is increased, so that the dielectric layer 106 is not easily broken down, the electrical performance of the semiconductor structure is improved.
The substrate provides a process foundation for forming the semiconductor structure.
Specifically, the substrate includes an interlayer dielectric layer 100, a connection metal layer 101 located in the interlayer dielectric layer 100, and an anti-etching layer 102 located on the interlayer dielectric layer 100 and the connection metal layer 101.
The connection metal layer 101 is a structure to be connected, and the connection metal layer 101 is used for being electrically connected with a capacitor.
In this embodiment, the material of the connection metal layer 101 is Cu. In other embodiments, the material of the connecting metal layer includes Al, Co, or W.
The number of the connection metal layers 101 is plural.
The interlayer dielectric layer 100 is used to realize electrical isolation between the plurality of connection metal layers 101.
The interlayer dielectric layer 100 is made of an ultralow-K dielectric material, the ultralow-K dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6, and the ultralow-K dielectric material is selected for the interlayer dielectric layer 100, so that the parasitic capacitance of the connection metal layer 101 can be effectively reduced, and the RC delay at the rear end is further reduced.
In this embodiment, the interlayer dielectric layer 100 is made of porous silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be SiOCH.
The etching stop layer 102 is used for defining the position of etching stop in the process of forming the capacitor and protecting the connecting metal layer 101 and the interlayer dielectric layer 100.
Specifically, the material of the etch-resistant layer 102 includes one or more of silicon oxide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, and silicon nitride containing C. In this embodiment, the material of the anti-etching layer 102 is silicon nitride containing C.
It should be noted that, the material of the anti-etching layer 102 is different from the material of the first electrode layer 104 in thermal expansion coefficient, and if the first electrode layer 104 is directly formed on the anti-etching layer 102, the first electrode layer 104 is easily delaminated (Delamination) and even cracked (crack) from the anti-etching layer 102, resulting in poor formation quality of the capacitor. Therefore, a buffer layer 103 is formed between the etch resist layer 102 and the first electrode layer 104, and the buffer layer 103 serves as a stress buffer.
In this embodiment, the buffer layer 103 is made of silicon oxide.
It should be noted that the density of the buffer layer 103 is greater than that of the interlayer dielectric layer 100, and the higher density of the silicon oxide is beneficial to improving the adhesion between the buffer layer 103 and the anti-etching layer 102 and the first electrode layer 104, and improving the formation quality of the semiconductor structure.
In other embodiments, the material of the buffer layer includes a low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6). For example: SiOH, SiOCH, FSG, BSG, PSG, BPSG, hydridosilsesquioxane or methylsilsesquioxane.
The first electrode layer 104, the dielectric layer 106, and the second electrode layer 105 together constitute a capacitor, which is an MIM capacitor.
The first electrode layer 104 is used as a lower plate of the MIM capacitor. The first electrode layer 104 is connected to the connection metal layer 101.
In addition, a first electrode contact layer 1041 is formed in the first electrode layer 104 and is in contact with the dielectric layer 106.
In this embodiment, the first electrode contact layer 1041 is made of a metal material.
Specifically, the first electrode contact layer 1041 is made of a metal nitride, and the metal nitride is an inert metal, so that the first electrode contact layer 1041 has high stability, and metal ions are not easy to diffuse.
In this embodiment, the material of the first electrode contact layer 1041 is one or two of TiN and TaN. TaN and TiN have a relatively high work function, so that electrons are not easy to jump, and the capacitor is not easy to leak electricity. In this embodiment, the material of the first electrode contact layer 1041 includes TiN.
In this embodiment, the first electrode contact layer 1041 is formed by an atomic layer deposition process, the atomic layer deposition process includes performing multiple atomic layer deposition cycles, and the surface roughness of the first electrode contact layer 1041 is low.
Note that the first electrode contact layer 1041 is not too thick nor too thin. If the first electrode contact layer 1041 is too thick, the process time is too long, and the height of the formed device is too large, which is not favorable for the subsequent semiconductor process. If the first electrode contact layer 1041 is too thin, the thickness uniformity and the film quality of the first electrode contact layer 1041 are easily reduced, the first electrode contact layer 1041 is not easy to cover the rough points of the layer structure below the first electrode contact layer 1041, so that the protruding points protruding toward the dielectric layer 106 are easily present in the first electrode contact layer 1041, the second electrode contact layer 1041 is in contact with the dielectric layer 106 in the second electrode layer 105, and thus in the same region, the shortest distance between the first electrode contact layer 1041 and the second electrode contact layer is close, and the dielectric layer 106 is easily broken down. In this embodiment, the thickness of the first electrode contact layer 1041 is 1 nm to 15 nm.
The first electrode layer 104 further includes: a third electrode film 1042 under the first electrode contact layer 1041.
The first electrode contact layer 1041 and the third electrode film 1042 function together as a lower plate of the MIM capacitor.
In this embodiment, the third electrode film 1042 is made of a metal material.
Specifically, the third electrode film 1042 is made of a metal nitride, which is an inert metal, so that the third electrode film 1042 has high stability, and metal ions are not easily diffused.
In this embodiment, the third electrode film 1042 is made of one or two of TiN and TaN. TaN and TiN have a relatively high work function, so that electrons are not easily transited, and thus electric leakage is not easily generated in the capacitor. In this embodiment, the material of the third electrode film 1042 includes TiN.
The first electrode contact layer 1041 and the third electrode film 1042 are made of the same material, so that the interface problem and the electrical property degradation problem caused by different materials are effectively avoided, and the compatibility of the process and the stability of the semiconductor structure are improved.
The thickness of the third electrode film 1042 is not necessarily too small or too large. If the thickness of the third electrode film 1042 is too small, the film quality of the third electrode film 1042 is poor, and the formation quality of the first electrode contact layer 1041 is poor; if the thickness of the third electrode film 1042 is too large, the height of the device is too large, which may adversely affect the subsequent semiconductor process. For this reason, in this embodiment, the thickness of the third electrode film 1042 is 30 nm to 80 nm.
It should be noted that the MIM capacitor is formed between adjacent metal layers, so that the first electrode layer 104 is located in a partial region on the substrate.
The dielectric layer 106 is used as an insulating layer in a MIM capacitor.
In this embodiment, the dielectric layer 106 is made of a high-k dielectric material; wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. The high-k dielectric material is selected, so that the capacitance value of the MIM capacitor is improved.
Specifically, the dielectric layer 106 is a stacked high-k dielectric layer, that is, the dielectric layer 106 is a high-k composite dielectric layer. After the forming thickness of the high-k dielectric layer reaches a certain value, the forming quality of the high-k dielectric layer is easy to be deteriorated, and therefore, the thickness of the dielectric layer 106 meets the process requirement and has good forming quality at the same time by adopting the high-k composite dielectric layer.
The material of the dielectric layer 106 includes binary oxide and ternary oxide.
Specifically, the binary oxide includes: one or more of hafnium oxide, tantalum oxide, titanium oxide, hafnium oxide, or lanthanum oxide; the ternary oxide includes: SrTiO3、Zn2GeO4、NiCo2O4、Zn2SnO4、ZnFe2O4、ZnMnO3And Fe2GeO4One or more of (a). In this embodiment, the material of the dielectric layer 106 includes hafnium oxide.
It should be noted that the dielectric layer 106 is not too thick or too thin. As can be seen from the capacitance formula, the capacitance value of a single capacitor is inversely proportional to the thickness of the dielectric layer 106, and if the dielectric layer 106 is too thick, the density of the capacitor becomes small, which is not easy to meet the device requirement. If the dielectric layer 106 is too thin, the thickness uniformity and film quality of the dielectric layer 106 are poor, and the linearity between the capacitance and the thickness of the dielectric layer 106 is decreased, and the breakdown is also easily caused. In this embodiment, the thickness of the material of the dielectric layer 106 is 5 nm to 12 nm.
The second electrode layer 105 is used as an upper plate of the MIM capacitor. The second electrode layer 105 is connected to a metal layer subsequently formed on the capacitor.
In the second electrode layer 105, a second electrode contact layer 1051 is in contact with the dielectric layer 106.
In this embodiment, the second electrode contact layer 1051 is made of a metal material.
Specifically, the second electrode contact layer 1051 is made of a metal nitride, and the metal nitride is an inert metal, so that the second electrode contact layer 1051 has high stability, and metal ions are not easily diffused.
In this embodiment, the material of the second electrode contact layer 1051 is one or two of TiN and TaN. TaN and TiN have a relatively high work function, so that electrons are not easy to jump, and the capacitor is not easy to leak electricity. In this embodiment, the material of the second electrode contact layer 1051 includes TiN.
In this embodiment, the second electrode contact layer 1051 is formed by an atomic layer deposition process, and the atomic layer deposition process includes performing multiple atomic layer deposition cycles, so that the surface roughness of the second electrode contact layer 1051 is low.
Note that the second electrode contact layer 1051 is not too thick nor too thin. If the second electrode contact layer 1051 is too thick, the process time is too long, and the height of the formed device is too large, which is not favorable for the subsequent semiconductor process. If the second electrode contact layer 1051 is too thin, the thickness uniformity and film quality of the second electrode contact layer 1051 and the coverage capability of the second electrode contact layer 1051 on the dielectric layer 106 are easily reduced, and the second electrode contact layer 1051 does not easily cover the rough points on the fourth electrode film 1052, so that the shortest distance between the second electrode contact layer 1051 and the first electrode contact layer 1041 is short in the same region, and the dielectric layer 106 is easily broken down. In this embodiment, the thickness of the second electrode contact layer 1051 is 1 nm to 15 nm.
The second electrode layer 105 further includes: and a fourth electrode film 1052 on the second electrode contact layer 1051.
The second electrode contact layer 1051 and the fourth electrode film 1052 together serve as an upper plate of the MIM capacitor. The second electrode layer 105 is connected to a metal that is subsequently formed on the capacitor.
For this purpose, the material of the fourth electrode film 1052 is a metal material.
Specifically, the material of the fourth electrode film 1052 is metal nitride, and the metal nitride is an inert metal, so that the fourth electrode film 1052 has high stability, and metal ions are not easy to diffuse.
Specifically, the material of the fourth electrode film 1052 is one or two of TiN and TaN. TaN and TiN have a relatively high work function, so that electrons are not easy to jump, and the capacitor is not easy to leak electricity. In this embodiment, the material of the fourth electrode film 1052 includes TiN.
The materials of the second electrode contact layer 1051 and the fourth electrode film 1052 are the same, so that the problems of interface and electrical property degradation caused by different materials are effectively avoided, and the compatibility of the process and the stability of the semiconductor structure are improved.
The thickness of the fourth electrode film 1052 is not necessarily too small, and is not necessarily too large. If the thickness of the fourth electrode film 1052 is too small, the quality of the thin film of the fourth electrode film 1052 is easy to be poor, and the formation quality of the formed MIM capacitor is easy to be reduced; if the thickness of the fourth electrode film 1052 is too large, the process time is too long, and the height of the formed device is too large, which is not favorable for the subsequent semiconductor process. For this reason, in the present embodiment, the thickness of the fourth electrode film 1052 is 30 to 80 nm.
In other embodiments, the semiconductor structure includes: forming a first electrode contact layer and a second electrode contact layer which are in contact with the dielectric layer by adopting an atomic layer deposition process, wherein the first electrode contact layer and the second electrode contact layer do not comprise a third electrode film and a fourth electrode film, and correspondingly, the thicknesses of the first electrode contact layer and the second electrode contact layer are adaptively adjusted;
or, the thickness of the first electrode contact layer is adaptively adjusted without including the third electrode film but including the fourth electrode film;
or, the third electrode film is included, the fourth electrode film is not included, and the thickness of the second electrode contact layer is adaptively adjusted.
Fig. 6 is a schematic structural diagram of a semiconductor structure according to a second embodiment of the present invention.
The same parts of this embodiment as those of the first embodiment will not be described herein again. The present embodiment is different from the first embodiment in that: the first electrode layer 204 in contact with the dielectric layer 206 is a first electrode contact layer 2041, the second electrode layer in contact with the dielectric layer 206 is a second electrode contact layer 2051, and the first electrode contact layer 2041 is formed by an atomic layer deposition process.
The first electrode contact layer 2041 is formed by adopting an atomic layer deposition process, the surface roughness of the first electrode contact layer 2041 is low, compared with a process method that the roughness of the first electrode contact layer and the roughness of the second electrode contact layer are larger than that of the atomic layer deposition process, in the same region, protruding points which protrude towards the dielectric layer 206 at the same time are not easy to exist in the first electrode contact layer 2041 and the second electrode contact layer 2051, the shortest distance between the first electrode contact layer 2041 and the second electrode contact layer 2051 is increased, the dielectric layer 206 is not easy to break down, and the electrical performance of the semiconductor structure is improved.
In this embodiment, the material and thickness of the first electrode contact layer 2041 are the same as those of the first embodiment, and are not described herein again.
In this embodiment, the material, thickness, and the like of the third electrode film are as described in the first embodiment, and are not described herein again.
Note that the thickness of the second electrode contact layer 2051 is not necessarily too small or too large. If the thickness of the second electrode contact layer 2051 is too small, the quality of the film of the second electrode contact layer 2051 is poor, and the formation quality of the formed MIM capacitor is easily reduced; if the thickness of the second electrode contact layer 2051 is too large, the process time is too long, and the height of the formed device is too large, which is not favorable for the subsequent semiconductor process. For this reason, in this embodiment, the thickness of the second electrode contact layer 2051 is 31 nm to 95 nm.
In this embodiment, the material of the second electrode contact layer 2051 is not described herein again.
In this embodiment, the fourth electrode film is not included.
In other embodiments, the semiconductor structure includes: and only the first electrode contact layer is formed by adopting an atomic layer deposition process and does not comprise a third electrode film and a fourth electrode film, and the thicknesses of the first electrode contact layer and the second electrode contact layer are adaptively adjusted.
Fig. 7 is a schematic structural diagram of a semiconductor structure according to a second embodiment of the present invention.
The same parts of this embodiment as those of the first embodiment will not be described herein again. The present embodiment is different from the first embodiment in that: the first electrode layer is in contact with the dielectric layer 306 is a first electrode contact layer 3041, the second electrode layer 305 is in contact with the dielectric layer 306 is a second electrode contact layer 3051, and the second electrode contact layer 3051 is formed by using an atomic layer deposition process.
The second electrode contact layer 3051 is formed by an atomic layer deposition process, the surface roughness of the second electrode layer contact layer 3051 is relatively low, compared with a process method that the roughness of the first electrode contact layer and the roughness of the second electrode contact layer are larger than that of the atomic layer deposition process, in the same region, protruding points protruding towards the dielectric layer 306 at the same time are not easy to exist in the first electrode layer contact layer 3041 and the second electrode layer contact layer 3051, the shortest distance between the first electrode layer contact layer 3041 and the second electrode layer contact layer 3051 is increased, the dielectric layer 306 is not easy to break down, and the electrical performance of the semiconductor structure is improved.
In this embodiment, the material and thickness of the second electrode contact layer 3051 are as described in the first embodiment, and are not described herein again.
In this embodiment, the material, thickness, and the like of the fourth electrode film are as described in the first embodiment, and are not described herein again.
Note that the thickness of the first electrode contact layer 3041 should not be too small or too large. If the thickness of the first electrode contact layer 3041 is too small, the film quality of the first electrode contact layer 3041 is poor, and the formation quality of the dielectric layer 306 is easily reduced; if the thickness of the first electrode contact layer 3041 is too large, the process time is too long, and the height of the formed device is too large, which is not favorable for the subsequent semiconductor process. For this reason, in the present embodiment, the thickness of the first electrode contact layer 3041 is 31 nm to 95 nm.
In this embodiment, the material of the first electrode contact layer 3041 is not described herein.
In this embodiment, the third electrode film is not included.
In other embodiments, the semiconductor structure includes: and only the second electrode contact layer is formed by adopting an atomic layer deposition process and does not comprise a third electrode film and a fourth electrode film, and the thicknesses of the first electrode contact layer and the second electrode contact layer are adaptively adjusted.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a first electrode layer on the substrate, wherein the first electrode layer is of a single-layer or multi-layer structure;
forming a dielectric layer on the first electrode layer;
forming a second electrode layer on the dielectric layer, wherein the second electrode layer is of a single-layer or multi-layer structure;
the first electrode layer is in contact with the dielectric layer and is a first electrode contact layer, the second electrode layer is in contact with the dielectric layer and is a second electrode contact layer, and at least one of the first electrode contact layer and the second electrode contact layer is formed by adopting an atomic layer deposition process.
2. The method of forming a semiconductor structure of claim 1, wherein the first electrode contact layer and the second electrode contact layer are each formed using an atomic layer deposition process;
the step of forming the first electrode layer further comprises: forming a third electrode film on the substrate before forming the first electrode contact layer;
the step of forming the second electrode layer further comprises: after the second electrode contact layer is formed, a fourth electrode film is formed on the second electrode contact layer.
3. The method of forming a semiconductor structure of claim 2, wherein the first electrode contact layer has a thickness of 1 nm to 15 nm.
4. The method of forming a semiconductor structure of claim 2, wherein the second electrode contact layer has a thickness of 1 nm to 15 nm.
5. The method of forming a semiconductor structure of claim 1, wherein the first electrode contact layer is a metal film.
6. The method of forming a semiconductor structure of claim 1, wherein the second electrode contact layer is a metal film.
7. The method for forming a semiconductor structure according to claim 5 or 6, wherein a material of the metal film is a metal nitride.
8. The method of forming a semiconductor structure of claim 7, wherein the metal nitride comprises: one or two of TiN and TaN.
9. The method for forming a semiconductor structure according to claim 2, wherein the third electrode film is formed by a physical vapor deposition process;
and forming the fourth electrode film by adopting a physical vapor deposition process.
10. The method for forming a semiconductor structure according to claim 2, wherein the third electrode film is a metal film;
the fourth electrode film is a metal film.
11. A semiconductor structure, comprising:
a substrate;
the first electrode layer is positioned on the substrate and is of a single-layer or multi-layer structure;
a dielectric layer on the first electrode layer;
the second electrode layer is positioned on the dielectric layer and is of a single-layer or multi-layer structure;
the first electrode layer is in contact with the dielectric layer and is a first electrode contact layer, the second electrode layer is in contact with the dielectric layer and is a second electrode contact layer, and at least one of the first electrode contact layer and the second electrode contact layer is formed by adopting an atomic layer deposition process.
12. The semiconductor structure of claim 11, wherein the first electrode contact layer and the second electrode contact layer are both formed using an atomic layer deposition process;
the first electrode layer further includes: a third electrode film between the substrate and the first electrode contact layer;
the second electrode layer further includes: and a fourth electrode film on the second electrode contact layer.
13. The semiconductor structure of claim 12, wherein the first electrode contact layer has a thickness of 1 nm to 15 nm.
14. The semiconductor structure of claim 12, wherein the second electrode contact layer has a thickness of 1 nm to 15 nm.
15. The semiconductor structure of claim 11, wherein the first electrode contact layer is a metal film.
16. The semiconductor structure of claim 12, wherein the second electrode contact layer is a metal film.
17. The semiconductor structure according to claim 15 or 16, wherein a material of the metal film is a metal nitride.
18. The semiconductor structure of claim 17, wherein the metal nitride comprises: one or two of TiN and TaN.
19. The semiconductor structure according to claim 12, wherein the third electrode film is a metal film;
the fourth electrode film is a metal film.
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| CN113380147A (en) * | 2021-06-17 | 2021-09-10 | 云谷（固安）科技有限公司 | Display panel, display panel preparation method and display device |
| CN116723762A (en) * | 2023-08-08 | 2023-09-08 | 荣芯半导体(淮安)有限公司 | MIM capacitor and preparation method thereof |
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